JPS61189619A - Compound semiconductor device - Google Patents
Compound semiconductor deviceInfo
- Publication number
- JPS61189619A JPS61189619A JP2996385A JP2996385A JPS61189619A JP S61189619 A JPS61189619 A JP S61189619A JP 2996385 A JP2996385 A JP 2996385A JP 2996385 A JP2996385 A JP 2996385A JP S61189619 A JPS61189619 A JP S61189619A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- substrate
- compound semiconductor
- single crystal
- gaas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02441—Group 14 semiconducting materials
- H01L21/0245—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/02546—Arsenides
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Junction Field-Effect Transistors (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はＳｉ基板上にＧａＡｓ等のｍ−ｖ族化合物半導
体層を積層した化合物半導体装置に関し。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a compound semiconductor device in which an m-v group compound semiconductor layer such as GaAs is stacked on a Si substrate.
化合物半導体デバイス作成の基幹技術として利用される
。It is used as a core technology for creating compound semiconductor devices.
（従来の技術）
ＧａＡｓ等の化合物半導体は、その優れた特徴を生かし
て光半導体デバイスおよび高速デバイスに利用されてい
る。しかし、化合物半導体基板はＳｉ基板に比べて一般
に高価であり、さらに大面積の高品質基板結晶が得にく
い等の欠点がある。(Prior Art) Compound semiconductors such as GaAs are utilized in optical semiconductor devices and high-speed devices by taking advantage of their excellent characteristics. However, compound semiconductor substrates are generally more expensive than Si substrates, and have drawbacks such as difficulty in obtaining high-quality substrate crystals with large areas.
このような欠点を補うために良質で軽量なシリコン（Ｓ
ｉ）を基板とし、このＳｉ基板上に化合物半導体層を積
層し、当該化合物半導体層にデバイスを構成する試みが
なされている。従来、Ｓｉ基板上にＧａＡ３層を形成す
るためには１例えば゛以下に示す２つの方法が用いられ
ている。To compensate for these shortcomings, high-quality and lightweight silicon (S
Attempts have been made to use i) as a substrate, stack a compound semiconductor layer on this Si substrate, and construct a device on the compound semiconductor layer. Conventionally, in order to form a GaA three layer on a Si substrate, two methods, for example, shown below, have been used.
第１の方法として２分子線エピタキシー（ＭＢＥ）法ま
たは有機金属気相成長（ＭＯＣＶＤ）法を用いてＳｉ基
板上に直接ＧａＡｓ層を形成する方法である。このよう
にして形成された化合物半導体装置を第３図に示し２図
中５はＳｉ基板、６は化合物半導体層である。The first method is to form a GaAs layer directly on a Si substrate using bimolecular beam epitaxy (MBE) or metal organic chemical vapor deposition (MOCVD). The compound semiconductor device thus formed is shown in FIG. 3, and in FIG. 2, 5 is a Si substrate and 6 is a compound semiconductor layer.
第２の方法として、電子ビーム蒸着（ＥＢ）法。The second method is electron beam evaporation (EB).
イオンクラスタビーム（Ｉ ＣＢ）法２分子線エピタキ
シー（ＭＢＥ）法または気相成長（ＣＶＤ）法等を用い
てＳｉ基板上に単結晶Ｇｅ層を形成したのちに９分子線
エピタキシー（ＭＢＥ）法または有機金属気相成長（Ｍ
ＯＣＶＤ）法を用いてＧａＡｓ層を形成する方法である
。このようにして形成された化合物半導体装置を第４図
に示し９図中７はＳｉ基板、８は単結晶Ｇｅ層、９はＧ
ａＡｓ層である。After forming a single crystal Ge layer on a Si substrate using the ion cluster beam (I CB) method, two molecular beam epitaxy (MBE) method, or vapor phase epitaxy (CVD) method, etc., Metal-organic vapor phase epitaxy (M
This is a method of forming a GaAs layer using the (OCVD) method. The compound semiconductor device thus formed is shown in FIG. 4, in which 7 is a Si substrate, 8 is a single crystal Ge layer, and 9 is a G
It is an aAs layer.
（発明が解決しようとする問題点）
しかるに、上述した第１の方法では、熱膨張係数の相違
に基づく残留格子ひずみの問題は解決されておらず、格
子ひずみの少ない良質なＧａＡｓ単結晶を得ることはで
きない。また、第２の方法においても、熱膨張係数の相
違から形成温度からの冷却過程で生じる大きな格子ひず
みがＧａＡｓ層９に残留する。特にＧａＡｓ層９を３μ
ｍ以上に厚く形成した場合、ＧａＡｓ層９中に割れが発
生するという問題があり、良質なＧａＡｓ単結晶を形成
することができなかった。(Problems to be Solved by the Invention) However, the first method described above does not solve the problem of residual lattice distortion due to the difference in thermal expansion coefficients, and it is difficult to obtain a high-quality GaAs single crystal with little lattice distortion. It is not possible. In the second method as well, large lattice strain generated during the cooling process from the formation temperature remains in the GaAs layer 9 due to the difference in thermal expansion coefficients. In particular, the GaAs layer 9 is
If it is formed thicker than m, there is a problem that cracks occur in the GaAs layer 9, making it impossible to form a high quality GaAs single crystal.
（発明の目的）
本発明はかかる点に鑑み、Ｓｉ単結晶を基板材料とし、
ｍ−ｖ族の混晶系単結晶を活性層とする化合物半導体装
置において、基板と化合物半導体層との間に熱膨張係数
の相違に基づく格子ひずみを吸収し、かつＳｉとＧａＡ
ｓの格子定数の相違を緩和させることを目的とする。(Object of the invention) In view of the above, the present invention uses Si single crystal as a substrate material,
In a compound semiconductor device having an m-v group mixed single crystal as an active layer, lattice strain due to the difference in thermal expansion coefficient between the substrate and the compound semiconductor layer is absorbed, and Si and GaA
The purpose is to alleviate the difference in the lattice constant of s.
（発明の構成）
本発明は、格子状にＧｅイオンが注入されたＳｉ基板上
にＧｅ単結晶層が形成され、このＧｅ単結晶層上に化合
物半導体層が形成された化合物半導体装置に係わる。(Structure of the Invention) The present invention relates to a compound semiconductor device in which a Ge single crystal layer is formed on a Si substrate into which Ge ions are implanted in a lattice pattern, and a compound semiconductor layer is formed on the Ge single crystal layer.
（実施例）
以下１本発明の実施例について図面を参照して説明する
。(Example) An example of the present invention will be described below with reference to the drawings.
第１図に本発明に係わる化合物半導体装置を示し２本例
ではＳｉ基板ｌ上にｍ−ｖ族化合物半導体層としてＧａ
Ａｓ層２を格子ひずみなく形成したものである。このた
めにＳｉ基板１上へ格子状にＧｅイオンを打ち込んでＧ
ｅ４１７層４を形成したのち、Ｇｅ単結晶層３を形成し
ている。FIG. 1 shows a compound semiconductor device according to the present invention. In this example, Ga is formed as an m-v group compound semiconductor layer on a Si substrate l.
The As layer 2 is formed without lattice distortion. For this purpose, Ge ions are implanted into the Si substrate 1 in a lattice pattern.
After forming the e417 layer 4, the Ge single crystal layer 3 is formed.
次に、上記構成からなる化合物半導体装置の製造方法に
ついて説明する。Next, a method for manufacturing a compound semiconductor device having the above structure will be described.
まず、Ｓｉ基板１の表面に格子状にＧｅイオンを注入し
てＧｅ４１７層４を形成する。このＧｅ４１７層４は格
子一本の線幅が１０μｍ程度であり、格子間隔を１００
μｍ程度とした。このようにして、Ｇｅイオンが注入さ
れたＳｉ基板１上にイオンクラスタビーム（Ｉ ＣＢ）
法でＧｅ単結晶層３を成長する。この成長条件として例
えば基板温度５００℃、成長速度５人／秒１層厚１００
０人に設定している。First, Ge417 layer 4 is formed by implanting Ge ions into the surface of Si substrate 1 in a grid pattern. In this Ge417 layer 4, the line width of one grating is about 10 μm, and the grating interval is 100 μm.
It was about μm. In this way, an ion cluster beam (I CB) is applied onto the Si substrate 1 into which Ge ions are implanted.
A Ge single crystal layer 3 is grown by the method. The growth conditions include, for example, a substrate temperature of 500°C, a growth rate of 5 people/sec, and a layer thickness of 100°C.
It is set to 0 people.
なお、Ｇｅ単結晶層３上に形成する化合物半導体単結晶
層としては、上述したＧａＡｓに限らず。Note that the compound semiconductor single crystal layer formed on the Ge single crystal layer 3 is not limited to the above-mentioned GaAs.
ＧａＰ、ＩｎＰ等の二元系化合物、さらにＧａＡｌＡｓ
、ＩｎＧａＰ、ＧａＡｓＰ等の三元系化合物、およびＩ
ｎＧａＡｓ Ｐ等の多元系化合物であってもよい。Binary compounds such as GaP and InP, as well as GaAlAs
, InGaP, ternary compounds such as GaAsP, and I
It may also be a multicomponent compound such as nGaAs P.
（本例と従来例の比較結果）
上述した化合物半導体装置からなる試料Ａと従来の成長
法によって得られた試料ＢとをＸ線２結晶法による回折
ピークの半値幅を測定することによって結晶性を比較し
た。(Results of comparison between this example and the conventional example) Crystallinity was determined by measuring the half-value width of the diffraction peak using the X-ray two-crystal method of sample A made of the compound semiconductor device described above and sample B obtained by the conventional growth method. compared.
なお１本例の試料Ａでは、Ｇｅ単結晶層３上にＭＯＣＶ
Ｄ法を用いて７３０℃の温度で３μｍの厚さのＧａＡｓ
層２をエピタキシャル成長したものであり、試料ＢはＳ
ｉ基板上に５００ ’Ｃで、厚さ１０００人のＧｅ単結
晶層を形成し、その上にＭＯＣＶＤ法を用いて３μｍの
厚さのＧａＡｓ層を成長したものである。In addition, in sample A of this example, MOCV was applied on the Ge single crystal layer 3.
GaAs with a thickness of 3 μm at a temperature of 730 °C using the D method.
Layer 2 is epitaxially grown, and sample B is S.
A Ge single-crystal layer with a thickness of 1000 nm was formed on an i-substrate at 500'C, and a GaAs layer with a thickness of 3 μm was grown thereon using the MOCVD method.
この結果、試料Ａの半値幅が試料Ｂの半値幅より小さく
、試料Ａの方が試料Ｂより優れた結晶性を有することが
確認された。As a result, it was confirmed that the half-width of Sample A was smaller than that of Sample B, and that Sample A had better crystallinity than Sample B.
（発明の効果）
以上述べたように２本発明によればＳｉ基板上に格子ひ
ずみの少ないＧａＡｓ、ＧａＡｌＡｓ等のｍ−ｖ族化合
物半導体単結晶層を形成することができ、高品質、低価
格、かつ軽量な化合物半導体装置の製造が可能となり、
化合物半導体装置の多機能化、高性能化を図ることがで
きる。また。(Effects of the Invention) As described above, according to the present invention, it is possible to form an m-v group compound semiconductor single crystal layer such as GaAs, GaAlAs, etc. with little lattice strain on a Si substrate, resulting in high quality and low cost. , and makes it possible to manufacture lightweight compound semiconductor devices.
Multifunctionality and high performance of compound semiconductor devices can be achieved. Also.
このような化合物半導体装置を太陽電池用の基板として
用いれば、軽量でしかも高効率のものを提供することが
できる。If such a compound semiconductor device is used as a substrate for a solar cell, it is possible to provide a lightweight and highly efficient device.
第１図は本発明に係わる化合物半導体装置を示す断面図
、第２図は同化合物半導体装置においてイオン注入直後
のＳｉ基板を示す平面図、第３図および第４図は従来例
を示す断面図である。
１・・・Ｓｉ基板 ２・・・ＧａＡｓ層３・・・
Ｇｅ単結晶層 ４・・・Ｇｅイオン層第１図
り
第２図
第３図
窮４ｆｇFIG. 1 is a cross-sectional view showing a compound semiconductor device according to the present invention, FIG. 2 is a plan view showing a Si substrate immediately after ion implantation in the same compound semiconductor device, and FIGS. 3 and 4 are cross-sectional views showing a conventional example. It is. 1...Si substrate 2...GaAs layer 3...
Ge single crystal layer 4...Ge ion layer 1st drawing 2nd figure 3rd figure 4fg
Claims (1)
単結晶層が形成され、このＧｅ単結晶層上にIII−Ｖ族
化合物半導体層が形成されたことを特徴とする化合物半
導体装置。1) Ge on a Si substrate into which Ge ions are implanted in a lattice pattern.
1. A compound semiconductor device comprising a single crystal layer and a III-V group compound semiconductor layer formed on the Ge single crystal layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2996385A JPS61189619A (en) | 1985-02-18 | 1985-02-18 | Compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2996385A JPS61189619A (en) | 1985-02-18 | 1985-02-18 | Compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61189619A true JPS61189619A (en) | 1986-08-23 |
Family
ID=12290625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2996385A Pending JPS61189619A (en) | 1985-02-18 | 1985-02-18 | Compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61189619A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01189909A (en) * | 1988-01-26 | 1989-07-31 | Nippon Telegr & Teleph Corp <Ntt> | Composite semiconductor substrate |
| US5108947A (en) * | 1989-01-31 | 1992-04-28 | Agfa-Gevaert N.V. | Integration of gaas on si substrates |
| JPH0729825A (en) * | 1993-07-08 | 1995-01-31 | Nec Corp | Semiconductor substrate and production thereof |
| US8686472B2 (en) | 2008-10-02 | 2014-04-01 | Sumitomo Chemical Company, Limited | Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate |
-
1985
- 1985-02-18 JP JP2996385A patent/JPS61189619A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01189909A (en) * | 1988-01-26 | 1989-07-31 | Nippon Telegr & Teleph Corp <Ntt> | Composite semiconductor substrate |
| US5108947A (en) * | 1989-01-31 | 1992-04-28 | Agfa-Gevaert N.V. | Integration of gaas on si substrates |
| JPH0729825A (en) * | 1993-07-08 | 1995-01-31 | Nec Corp | Semiconductor substrate and production thereof |
| US5549749A (en) * | 1993-07-08 | 1996-08-27 | Nec Corporation | Substrate with a compound semiconductor surface layer and method for preparing the same |
| US8686472B2 (en) | 2008-10-02 | 2014-04-01 | Sumitomo Chemical Company, Limited | Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate |
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