JPS61188939A - Method for mounting semiconductor element - Google Patents

Method for mounting semiconductor element

Info

Publication number
JPS61188939A
JPS61188939A JP2915585A JP2915585A JPS61188939A JP S61188939 A JPS61188939 A JP S61188939A JP 2915585 A JP2915585 A JP 2915585A JP 2915585 A JP2915585 A JP 2915585A JP S61188939 A JPS61188939 A JP S61188939A
Authority
JP
Japan
Prior art keywords
semiconductor element
film
hardness
protective resin
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2915585A
Other languages
Japanese (ja)
Other versions
JPH0376781B2 (en
Inventor
Junichi Okamoto
準市 岡元
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2915585A priority Critical patent/JPS61188939A/en
Publication of JPS61188939A publication Critical patent/JPS61188939A/en
Publication of JPH0376781B2 publication Critical patent/JPH0376781B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

PURPOSE:To eliminate short-circuit and assurs a high yield by coating semiconductor element surface and entire part of a plurality of leads extended up to an aperture on an insulated film with a thermosetting type protection resin, executing the primary hardening for the hardness 2H of pencil and then executing the secondary hardening. CONSTITUTION:A plurality of lead wires 2 extended up to an aperture of a flexible insulation film 1 and a gold bump 6 which is electrode of semicoductor element are connected and the surface of semiconductor element 4 and entire part of lead wire 2 are coated with the thermosetting type protection resin 7. This flexible insulation film 1 is a polyimide film and the primary hardening temperature for protection resin is set to 80-130 deg.C. The thermosetting type protection resin has a hardness of 3H in terms of a hardness of pencil after the secondary hardening process. After the primary hardening process, the film of protection resin must have the hardness of 2H or higher in terms of the hardness of pencil. If it is lower than such hardness, the reinforcement for lead wires by film carrier is not sufficient.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、フィルムキャリヤ方式による半導体素子の実
装方法に関し、特に半導体素子の保護樹脂形成方法に関
するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for mounting a semiconductor element using a film carrier method, and more particularly to a method for forming a protective resin for a semiconductor element.

(従来の技術) 一般に、半導体素子の実装方式の中で、高速で量産性に
富み、且つ高い信頼性を有する方式として、複数本のリ
ードを一度にボンディングすることができるフィルムキ
ャリヤによる実装方式が広く知られている。
(Prior Art) In general, among the mounting methods for semiconductor elements, a mounting method using a film carrier that can bond multiple leads at once is a method that is fast, mass-producible, and highly reliable. widely known.

このフィルムキャリヤ実装方式は、第4図に示すように
、デバイス孔が形成された可とう性絶縁フィルム1に、
デバイス孔まで延在するように形成された複数本のり−
ド2が接着剤3により接着されたフィルムキャリヤを使
用し、半導体素子4のアルミニウムパッド5上に形成さ
れた金バンプ6とフィルムキャリヤのり−ド2の先端と
が熱圧着あるいは超音波ボンディングにより接合され。
As shown in FIG. 4, this film carrier mounting method uses a flexible insulating film 1 in which device holes are formed.
Multiple glues formed to extend to the device hole.
The gold bumps 6 formed on the aluminum pads 5 of the semiconductor element 4 and the tip of the film carrier glue 2 are bonded by thermocompression bonding or ultrasonic bonding using a film carrier to which the glue 2 is bonded with the adhesive 3. It is.

次いで第5図に示すように、半導体素子4の表面とフィ
ルムキャリヤのり−ド2に熱硬化形保護樹脂7を塗布し
、硬化、あるいは乾燥により溶媒のみを揮発させてから
硬化させるものであった。
Next, as shown in FIG. 5, a thermosetting protective resin 7 was applied to the surface of the semiconductor element 4 and the film carrier glue 2, and the resin was cured or dried to volatilize only the solvent and then cured. .

(発明が解決しようとする問題点) しかしながら、従来の方法では、熱硬化形の保護樹脂7
を硬化させる時、第6図に示すように、可とう仕給縁フ
ィルム1の熱変形が発生し、それにともないフィルムキ
ャリヤのリード2が半導体素子4のエツジ部と短絡して
良品の半導体素子でも不良品となり、歩留りが著しく低
下するという問題点があった。
(Problem to be solved by the invention) However, in the conventional method, the thermosetting protective resin 7
When curing, as shown in FIG. 6, thermal deformation of the flexible feeding edge film 1 occurs, and as a result, the leads 2 of the film carrier are short-circuited with the edges of the semiconductor element 4, causing even good semiconductor elements to be damaged. There was a problem in that the product was defective and the yield was significantly reduced.

本発明は、上記従来例の欠点に鑑みてなされたもので、
可とう仕給縁フィルムの熱変形が硬化時に発生してもフ
ィルムキャリヤのリードと、半導体素子のエツジ部とが
短絡することなく、高歩留りを図ることができ、さらに
容易に製造することができる半導体素子の実装方法を提
供するものである。
The present invention has been made in view of the drawbacks of the above-mentioned conventional examples, and
Even if thermal deformation of the flexible edge film occurs during curing, the lead of the film carrier and the edge of the semiconductor element will not be short-circuited, making it possible to achieve high yields and facilitate manufacturing. A method for mounting semiconductor elements is provided.

(問題点を解決するための手段) 上記目的を達成するために、本発明は、可とう性絶縁フ
ィルム上の開孔部まで延設された複数本のリードと、半
導体素子の電極とを接合し、熱硬体形保護樹脂を少なく
とも前記半導体素子表面と、前記絶縁フィルム上の開孔
部まで延設された複数本のリード全面に塗布したのち、
鉛筆硬度2H以上を有する一次硬化を行ない、次いで二
次硬化を行なうようにしたものである6 (作 用) 一次硬化を行なうことにより、フィルムキャリヤの熱変
形がない状態でリードを保持・固定することができる。
(Means for Solving the Problems) In order to achieve the above object, the present invention connects a plurality of leads extending to an opening on a flexible insulating film and an electrode of a semiconductor element. After applying a thermosetting protective resin to at least the surface of the semiconductor element and the entire surface of the plurality of leads extending to the openings on the insulating film,
Primary curing with a pencil hardness of 2H or higher is performed, followed by secondary curing.6 (Function) By performing primary curing, the lead is held and fixed without thermal deformation of the film carrier. be able to.

(実施例) 以下、図面により本発明の実施例を詳細に説明する。第
1図及び第2図は、本発明の一実施例を示したも°ので
、第4.5.6図と同一符号のものは同一のものを示し
ている。
(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. 1 and 2 show one embodiment of the present invention, so the same reference numerals as in FIGS. 4, 5 and 6 indicate the same parts.

第1図及び第2図において、可とう仕給縁フィルム1の
開孔部まで延設された複数本のリード2と、半導体素子
の電極である金バンプ6とが接続され、半導体素子4の
表面と、リード2の全面に熱硬化形の保護樹脂7が塗布
・形成される。この可とう仕給縁フィルム1は厚さが7
5〜250μmのポリイミドフィルムであり、保護樹脂
の一次硬化温度は80〜130℃とする。また、熱硬体
形保護樹脂は、二次硬化後、鉛筆硬度で3)1以上を有
するものである。
1 and 2, a plurality of leads 2 extending to the opening of the flexible supply edge film 1 are connected to gold bumps 6, which are electrodes of the semiconductor element, and the semiconductor element 4 is connected to the gold bumps 6, which are the electrodes of the semiconductor element. A thermosetting protective resin 7 is applied and formed on the surface and the entire surface of the lead 2. This flexible feeding edge film 1 has a thickness of 7
It is a polyimide film with a thickness of 5 to 250 μm, and the primary curing temperature of the protective resin is 80 to 130°C. Further, the thermosetting protective resin has a pencil hardness of 3) or more after secondary curing.

本実施例では、可とう仕給縁フィルムとしてポリイミド
材を使用する。ポリエステル、ポリエチレン、ポリスル
ホンフィルム等は耐熱性に乏しく、熱変形を生じやすい
ので本発明の目的を達成できない。また、ポリイミドフ
ィルムでも厚さ75〜250μmを必要とし、75μm
より薄ければフィルムの機械的強度が著しく低下し、フ
ィルムキャリヤのリード間ピッチが狂って、半導体素子
の電極との位置合わせが非常に困難となり、接続不良が
発生する。また250μmより厚ければ、可とう性が失
われフィルムキャリヤが製造できない。
In this embodiment, a polyimide material is used as the flexible feed edge film. Polyester, polyethylene, polysulfone films, etc. have poor heat resistance and are susceptible to thermal deformation, making it impossible to achieve the object of the present invention. In addition, polyimide film also requires a thickness of 75 to 250 μm, and 75 μm
If it is thinner, the mechanical strength of the film will be significantly reduced, the pitch between the leads of the film carrier will be out of order, and alignment with the electrodes of the semiconductor element will be extremely difficult, resulting in poor connection. Further, if the thickness is more than 250 μm, flexibility is lost and a film carrier cannot be manufactured.

さらにまた、ポリイミド材のフィルムキャリヤでも51
30℃以上の温度で熱処理すれば、1〜2分の間に熱変
形し、フィルムの曲がりが生ずる。
Furthermore, a polyimide film carrier may also be used.
If the film is heat-treated at a temperature of 30° C. or higher, the film will undergo thermal deformation within 1 to 2 minutes, causing the film to bend.

そのために、熱硬化形の保護樹脂の一次硬化温度は80
〜130℃で処理する必要がある6130℃より高温で
保護樹脂を処理すると、フィルムの熱変形にともなって
フィルムキャリヤのリードも変形し、フィルムキャリヤ
のリードと半導体素子のエツジとが短絡し、半導体素子
が誤動作する。また80℃より低温で処理すれば、硬化
時間が非常に長くなる。
For this reason, the primary curing temperature of the thermosetting protective resin is 80°C.
If the protective resin is processed at a temperature higher than 6130°C, which requires processing at ~130°C, the leads of the film carrier will also be deformed as the film is thermally deformed, resulting in a short circuit between the leads of the film carrier and the edges of the semiconductor element, and the semiconductor Element malfunctions. Furthermore, if the treatment is performed at a temperature lower than 80° C., the curing time becomes very long.

また、一次項化後において、保護樹脂の皮膜硬度が鉛筆
硬度で2H以上を有する必要があり、それ以下であれば
、フィルムキャリヤのリード補強が十分とれなく、二次
硬化時にフィルムの変形にともなってフィルムキャリヤ
のリードと半導体素子のエツジとが短絡する。また、熱
硬体形保護樹脂は、二次硬化後、皮膜硬度が鉛筆硬度で
3H以上を示さねばならない。それ以下であれば、外部
の力によりフィルムキャリヤのリードと半導体素子のエ
ツジとが短絡したり、フィルムキャリヤのリード切れが
生ずる。
In addition, after primary conversion, the film hardness of the protective resin must be 2H or more on a pencil hardness; if it is less than that, the lead reinforcement of the film carrier will not be sufficient and the film will deform during secondary curing. This causes a short circuit between the leads of the film carrier and the edges of the semiconductor element. Further, the thermosetting protective resin must exhibit a film hardness of 3H or more on a pencil hardness scale after secondary curing. If it is less than that, the leads of the film carrier and the edges of the semiconductor element may be short-circuited or the leads of the film carrier may be broken due to external force.

次に本実施例をを具体的に説明する。Next, this example will be explained in detail.

まず、長尺の可とう仕給縁フィルム1として、幅35m
m、厚さ125μmのポリイミドフィルムを使用して、
第3図に示すフィルムキャリヤを作った。
First, a long flexible supply edge film 1 with a width of 35 m
m, using a polyimide film with a thickness of 125 μm,
A film carrier shown in FIG. 3 was made.

次に、半導体素子4のアルミニウムパッド5上に金バン
プ6を形成した。そして、フィルムキャリヤのり−ド2
の先端部と半導体素子の金バンプ6を顕微鏡により位置
合わせした後、熱圧着することにより、フィルムキャリ
ヤのリードと半導体素子の電極とを接続した。
Next, gold bumps 6 were formed on the aluminum pads 5 of the semiconductor element 4. And film carrier glue 2
After positioning the tip of the film carrier and the gold bumps 6 of the semiconductor element using a microscope, the leads of the film carrier and the electrodes of the semiconductor element were connected by thermocompression bonding.

次に、シリコン変性エポキシ樹脂(北陸塗料株式会社製
 商品名セラコート)を保護樹脂7として使用し、半導
体素子4の表面と、フィルムキャリヤのリード2の全面
に塗布した。
Next, a silicone-modified epoxy resin (trade name: Cerakote, manufactured by Hokuriku Paint Co., Ltd.) was used as a protective resin 7, and was applied to the surface of the semiconductor element 4 and the entire surface of the lead 2 of the film carrier.

その後、表のような一次硬化条件及び二次硬化条件にて
保護樹脂を硬化した。
Thereafter, the protective resin was cured under the primary curing conditions and secondary curing conditions as shown in the table.

以上のように、一次項化によりフィルムキャリヤの熱変
形がない状態でフィルムキャリヤのリードを保護樹脂に
て固め、次いで二次硬化により保護樹脂を完全硬化させ
ることにより、フィルムキャリヤのリードと半導体素子
エツジとの短絡がない、確実な半導体素子の実装を得る
ことができた。
As described above, by hardening the leads of the film carrier with a protective resin in a state where there is no thermal deformation of the film carrier through primary termization, and then completely curing the protective resin through secondary curing, the leads of the film carrier and the semiconductor element can be bonded together. We were able to achieve reliable mounting of semiconductor elements without short circuits with the edges.

(発明の効果) 以上説明したように、本発明によれば、可とう仕給縁フ
ィルムの熱変形が保護樹脂の本硬化時に発生しても、フ
ィルムキャリヤのリードと半導体素子のエツジ部とは短
絡することなく、高歩留りを図ることができ、さらに容
易に製造することができる等の効果を有するものである
(Effects of the Invention) As explained above, according to the present invention, even if thermal deformation of the flexible supply edge film occurs during the main curing of the protective resin, the leads of the film carrier and the edge portion of the semiconductor element are This has the advantage of being able to achieve a high yield without causing short circuits, and also being able to be manufactured easily.

【図面の簡単な説明】[Brief explanation of drawings]

第1WIは、本発明の半導体素子表面とリードとに保護
樹脂が塗布された断面図、第2図は、第1図の熱処理後
の断面図、第3図は、本発明の実施例のフィルムキャリ
ヤの平面図、第4図は、フィルムキャリヤと半導体素子
の接続の断面図、第5図は、従来の半導体素子表面とリ
ードとに保護樹脂が塗布された断面図、第6図は、第5
図の熱処理後の断面図である。 1 ・・・可とう仕給縁フィルム、 2 ・・・ リー
ド、4・・・半導体素子、 5 アルミニウムパッド、
6・・・金バンプ、 7・・・熱硬体形保護樹脂。 特許出願人 松下電器産業株式会社 第1図 第2図 第3図
1WI is a cross-sectional view of a semiconductor element surface and leads coated with a protective resin according to the present invention, FIG. 2 is a cross-sectional view of the semiconductor element after heat treatment shown in FIG. FIG. 4 is a plan view of the carrier, FIG. 4 is a sectional view of the connection between the film carrier and the semiconductor element, FIG. 5 is a sectional view of the conventional semiconductor element surface and leads coated with protective resin, and FIG. 5
FIG. 3 is a cross-sectional view after the heat treatment shown in FIG. 1... Flexible supply edge film, 2... Lead, 4... Semiconductor element, 5 Aluminum pad,
6... Gold bump, 7... Thermosetting protective resin. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 1 Figure 2 Figure 3

Claims (3)

【特許請求の範囲】[Claims] (1)可とう性絶縁フィルム上の開孔部まで延設された
複数本のリードと半導体素子の電極とを接合した後、少
なくとも前記半導体素子表面及び半導体素子に接合され
た複数本のリードの全面に熱硬化形保護樹脂を塗布し、
前記熱硬化形保護樹脂の硬化後の硬度が鉛筆硬度2H以
上を示す一次硬化を行ない、次いで最終的な二次硬化を
行なうことを特徴とする半導体素子の実装方法。
(1) After bonding the plurality of leads extending to the opening on the flexible insulating film and the electrodes of the semiconductor element, at least the surface of the semiconductor element and the plurality of leads bonded to the semiconductor element are bonded. Apply thermosetting protective resin to the entire surface,
A method for mounting a semiconductor element, comprising performing primary curing in which the thermosetting protective resin has a hardness of 2H or more on a pencil hardness after curing, and then performing final secondary curing.
(2)可とう性絶縁フィルムが75〜250μmの厚み
を有するポリイミドフィルムからなり、一次硬化の温度
が80〜130℃であることを特徴とする特許請求の範
囲第(1)項記載の半導体素子の実装方法。
(2) The semiconductor element according to claim (1), wherein the flexible insulating film is made of a polyimide film having a thickness of 75 to 250 μm, and the primary curing temperature is 80 to 130°C. How to implement.
(3)熱硬化形保護樹脂は、二次硬化後の硬度が鉛筆硬
度3H以上を有することを特徴とする特許請求の範囲第
(1)項記載の半導体素子の実装方法。
(3) The method for mounting a semiconductor element according to claim (1), wherein the thermosetting protective resin has a pencil hardness of 3H or more after secondary curing.
JP2915585A 1985-02-16 1985-02-16 Method for mounting semiconductor element Granted JPS61188939A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2915585A JPS61188939A (en) 1985-02-16 1985-02-16 Method for mounting semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2915585A JPS61188939A (en) 1985-02-16 1985-02-16 Method for mounting semiconductor element

Publications (2)

Publication Number Publication Date
JPS61188939A true JPS61188939A (en) 1986-08-22
JPH0376781B2 JPH0376781B2 (en) 1991-12-06

Family

ID=12268372

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2915585A Granted JPS61188939A (en) 1985-02-16 1985-02-16 Method for mounting semiconductor element

Country Status (1)

Country Link
JP (1) JPS61188939A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58204547A (en) * 1982-05-25 1983-11-29 Citizen Watch Co Ltd Sealing method for ic

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58204547A (en) * 1982-05-25 1983-11-29 Citizen Watch Co Ltd Sealing method for ic

Also Published As

Publication number Publication date
JPH0376781B2 (en) 1991-12-06

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