JPS61182348A - Test system of margin - Google Patents
Test system of marginInfo
- Publication number
- JPS61182348A JPS61182348A JP2163585A JP2163585A JPS61182348A JP S61182348 A JPS61182348 A JP S61182348A JP 2163585 A JP2163585 A JP 2163585A JP 2163585 A JP2163585 A JP 2163585A JP S61182348 A JPS61182348 A JP S61182348A
- Authority
- JP
- Japan
- Prior art keywords
- margin
- repeater
- error
- transmission line
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/24—Testing correct operation
- H04L1/241—Testing correct operation using pseudo-errors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Dc Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明はディジタル伝送路において中継器の余裕度を試
験し、予め特性の劣化した中継器を検知する方式に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for testing the margin of repeaters in a digital transmission line and detecting repeaters whose characteristics have deteriorated in advance.
従来は添は文献の如くパルストリオなどによる余裕度試
験が行なわれていた。これはパルストリオの中継器が誤
動作するまで増加して行き、誤動作を生じたパルストリ
オの数により中継器の余裕度を判定するものである。し
かしながら、パルストリオは実際にはあり得ない信号パ
ルス列であり、−見回線を試験装置に切替えて行う関係
上、実用的稼動条件と異なるため必ずしも的確な試験結
果が得られなかった。すなわちパルストリオを用いて余
裕度が十分あると判定された場合でも実際の信号を通し
た場合には殆ど余裕度がなく、わずかな雑音により誤動
作をおこすこともあり得る。したがってなるべく使用状
態に近い条件で、またできれば稼動時における余裕度試
験を行うことが望まれていた。Conventionally, margin tests have been conducted using pulse trios, etc., as shown in the accompanying literature. This increases the number of pulse trio repeaters until they malfunction, and the margin of the repeater is determined based on the number of malfunctioning pulse trios. However, the pulse trio is a signal pulse train that cannot actually occur, and since it is performed by switching the observation line to the test equipment, which differs from practical operating conditions, accurate test results were not necessarily obtained. That is, even if it is determined that there is sufficient margin using a pulse trio, there is almost no margin when an actual signal is passed, and a slight noise may cause a malfunction. Therefore, it has been desired to conduct a margin test under conditions as close as possible to those in use, preferably during operation.
本発明の目的は、より稼動状態に近い条件下で余裕度試
験を可能とする方式を提供することにある。An object of the present invention is to provide a method that enables a margin test under conditions closer to operating conditions.
上記の目的を達成するために本発明では、各中継器のタ
イミング回路に周波数に応じて位相の変わる素子を設け
、送信側でクロック周波数を変化して各中継器における
符号誤り率を測定することにより余裕度の試験を行なう
。すなわち中継器が誤動作するまで送信のクロック周波
数をずらせて行き、誤りの生じたクロック周波数と基準
の（公称の）クロック周波数との差が大きい程、識別余
裕度が大であると判定する。In order to achieve the above object, the present invention provides an element whose phase changes depending on the frequency in the timing circuit of each repeater, and changes the clock frequency on the transmitting side to measure the bit error rate in each repeater. Perform a margin test using That is, the transmission clock frequency is shifted until the repeater malfunctions, and the larger the difference between the clock frequency at which the error occurs and the reference (nominal) clock frequency, the larger the identification margin is determined to be.
以下本発明の一実施例を第１図〜第３図を用いて説明す
る。An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.
第１図において可変周波数回路１はクロック周波数を変
えるための発振器である。送信器２より信号パルス列を
伝送路３に送信するが、そのクロックレートが公称値よ
り可変に出来る。中継器４はクロックレートが公称値よ
り所定値以上ずれた場合、以下（第２図）で説明するご
とく符号誤りを発生するので、これを誤り測定器５で検
出し。In FIG. 1, a variable frequency circuit 1 is an oscillator for changing the clock frequency. A signal pulse train is transmitted from the transmitter 2 to the transmission line 3, and its clock rate can be made variable from the nominal value. If the clock rate deviates from the nominal value by more than a predetermined value, the repeater 4 generates a code error as explained below (FIG. 2), and this is detected by the error measuring device 5.
その結果を変調器６でしかるべく変調し、介在対ケーブ
ル７を介して余裕度試験器８へ送信する。The result is appropriately modulated by a modulator 6 and transmitted via an intervening pair cable 7 to a margin tester 8 .
第２図は余裕度劣化の原理を説明するものである。中継
器内の増幅器１１により所定のレベル増幅された信号か
らタイミング回路１２によりタイミング波がとり出され
る。これは周波数に依存して位相の変わる周波数依存性
移相回路１３を通った後、クロック成形回路１４により
クロックパルスとして成形され、識別回路１５でパルス
再生に用いられる。FIG. 2 explains the principle of margin deterioration. A timing wave is extracted by a timing circuit 12 from a signal amplified to a predetermined level by an amplifier 11 in the repeater. After passing through a frequency-dependent phase shift circuit 13 whose phase changes depending on the frequency, this signal is shaped into a clock pulse by a clock shaping circuit 14, and used for pulse reproduction by an identification circuit 15.
クロックレートを公称値よりずらした場合に移相回路１
３により再生のタイミング位相がずれるため、正しく受
信パルスの中心をサンプリングすることが出来なくなり
、サンプリング点が中心からずれるほど波形ひずみの影
響をうけやすくなり識別の余裕度が劣化し１位相のずれ
が所定の量を越えると符号誤りを生ずる。Phase shift circuit 1 when the clock rate is shifted from the nominal value
3 causes the reproduction timing phase to shift, making it impossible to sample the center of the received pulse correctly, and the further the sampling point shifts from the center, the more susceptible it is to waveform distortion, which degrades the margin of identification and causes a one-phase shift. If it exceeds a predetermined amount, a code error will occur.
周波数依存性移相回路１３の典形的な例としてはＬＣ共
振回路があげられる。A typical example of the frequency dependent phase shift circuit 13 is an LC resonant circuit.
なお符号誤りは通常中継伝送に用いる伝送路符号の規則
性が符号誤りによって乱されるため生ずるバイオレーシ
ョンを用いて検出されるが、この場合各中継器における
符号誤りによるバイオレーションの累積が生ずる。これ
を避けるためには、第３図に示した如く、中継器４のあ
とに再符号器２１を挿入して、一旦原信号にもどした後
再び伝送路符号化することによりバイオレーションを解
消して送出してやれば、各中継区間の符号誤りのみを検
出することができる。Note that code errors are usually detected using violations that occur because the regularity of the transmission path code used for relay transmission is disturbed by code errors, but in this case, violations occur due to code errors in each repeater. In order to avoid this, as shown in Figure 3, a re-encoder 21 is inserted after the repeater 4 to restore the original signal and then re-encode the transmission line to eliminate the violation. If the signal is transmitted in the same manner, only code errors in each relay section can be detected.
以上本発明によれば第４図に示す如く、伝送路のクロッ
クレートを変えて各中継器の誤りを発生させ、この場合
の周波数ずれΔｆ！＋Δｆ２の大小により余裕度を判定
することが出来るため、伝送信号自体に特殊なものを用
いる必要がなく、稼動時に近い状態において試験を行う
ことが出来る。As described above, according to the present invention, as shown in FIG. 4, the clock rate of the transmission line is changed to cause errors in each repeater, and in this case, the frequency shift Δf! Since the degree of margin can be determined based on the magnitude of +Δf2, there is no need to use a special transmission signal itself, and the test can be performed in a state close to the operating state.
また稼動状態においてクロック周波数を変えてやり、使
用に耐える程度の符号誤り率を生ずる範囲内にクロック
の変動をとどめれば、稼動状態のまま余裕度を試験する
ことも出来る。Furthermore, by changing the clock frequency during operation and keeping the clock fluctuation within a range that produces a bit error rate that is acceptable for use, it is also possible to test the margin while in operation.
第１〜第３図は本発明の一実施例であり、第４図はこれ
を説明する図である。
１：可変周波数発振器、２：送信器、３：伝送線路、４
：中継器、５：符号誤り検出器、６：変調器、７：介在
対ケーブル、８：余裕度試験器、１１：増幅器、１，２
：タイミング抽出回路、１３：周波数依存形移相器、１
４：クロック成形回路、１５ ：ｉｌｌ再再生回路２１
：再符号化回路。
第７図
躬２図
１ヤ
／ｚ ／ｊ ７嘔躬
３図
躬 ４図
周 液艮1 to 3 show one embodiment of the present invention, and FIG. 4 is a diagram for explaining this. 1: Variable frequency oscillator, 2: Transmitter, 3: Transmission line, 4
: Repeater, 5: Code error detector, 6: Modulator, 7: Interposed pair cable, 8: Margin tester, 11: Amplifier, 1, 2
: Timing extraction circuit, 13: Frequency dependent phase shifter, 1
4: Clock shaping circuit, 15: ill regeneration circuit 21
: Re-encoding circuit. Fig. 7 Fig. 2 Fig. 1 Y/z /j 7 Fig. 3 Fig. 4 Fig. Zhou Liquid 艮
Claims (1)
号誤り率を測定することを特徴とする余裕度試験方式。 ２、特許請求の範囲第１項において、誤り検出可能な伝
送路符号を用い誤り率測定後の信号を符号誤りによるバ
イオレーションを除去すべく再符号化して送出すること
を特徴とする余裕度試験方式。[Claims] 1. A margin test method characterized by varying the clock rate of the transmission line and measuring the code error rate of each repeater. 2. A margin test according to claim 1, characterized in that the signal after error rate measurement using an error-detectable transmission line code is re-encoded to remove violations due to code errors and then sent. method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2163585A JPS61182348A (en) | 1985-02-08 | 1985-02-08 | Test system of margin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2163585A JPS61182348A (en) | 1985-02-08 | 1985-02-08 | Test system of margin |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61182348A true JPS61182348A (en) | 1986-08-15 |
Family
ID=12060527
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2163585A Pending JPS61182348A (en) | 1985-02-08 | 1985-02-08 | Test system of margin |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61182348A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003007578A1 (en) * | 2001-07-13 | 2003-01-23 | Anritsu Corporation | Jitter resistance measuring instrument and method for enabling efficient measurement of jitter resistance characteristic and adequate evaluation |
-
1985
- 1985-02-08 JP JP2163585A patent/JPS61182348A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2003007578A1 (en) * | 2001-07-13 | 2003-01-23 | Anritsu Corporation | Jitter resistance measuring instrument and method for enabling efficient measurement of jitter resistance characteristic and adequate evaluation |
| US7245657B2 (en) | 2001-07-13 | 2007-07-17 | Anritsu Coporation | Jitter resistance measuring instrument and method for enabling efficient measurement of jitter resistance characteristic and adequate evaluation |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CA1147402A (en) | Time jitter determining apparatus | |
| JPH0133064B2 (en) | ||
| US4100531A (en) | Bit error rate measurement above and below bit rate tracking threshold | |
| US6313934B1 (en) | Chromatic dispersion measurement scheme for optical systems having remote access points | |
| US5880837A (en) | Eye measurement of optical signals by optical sampling | |
| US6433899B1 (en) | Eye quality monitor for a 2R regenerator | |
| JP2007174176A (en) | Unit and method for testing communication terminal | |
| JPS61182348A (en) | Test system of margin | |
| US4274047A (en) | Analyzer for nonlinear networks | |
| CN100418064C (en) | Method to snapshot and playback raw data in an ultrasonic meter | |
| US4745603A (en) | Code sequence generator for a digital transmission line fault location system | |
| US2837636A (en) | Radio test signal generation | |
| US4053723A (en) | Method and apparatus for measuring the bit error frequency in a cable caused by crosstalk between line pairs during transmission of a 3-level coded pcm signal | |
| US3913011A (en) | Method and apparatus for measuring conversion of amplitude modulation to phase modulation | |
| US6986091B2 (en) | Method and apparatus for testing a high speed data receiver for jitter tolerance | |
| Lerner et al. | Measurement of bandwidth of microwave resonator by phase shift of signal modulation | |
| JPH01154660A (en) | Testing method for communication system | |
| US4553086A (en) | Carrier power to noise power ratio measuring system for TDMA signals | |
| US3537009A (en) | Frequency comparator | |
| JPS59501479A (en) | Signal processing method for received pulse train and receiver that performs this processing | |
| JPH03222553A (en) | Measuring method for timing jitter | |
| SU1469481A1 (en) | Method of determining natural frequency and attenuation of electrodynamic seismoreceivers | |
| SU1107171A1 (en) | Device for measuring variations of speed of record medium | |
| SU761940A1 (en) | Apparatus for automatic measuring of parameters of four-terminal network frequency characteristics | |
| JP2009171240A (en) | Jitter transfer characteristic measuring device |