JPS61181168A - Nonvolatile semiconductor memory device - Google Patents

Nonvolatile semiconductor memory device

Info

Publication number
JPS61181168A
JPS61181168A JP2242785A JP2242785A JPS61181168A JP S61181168 A JPS61181168 A JP S61181168A JP 2242785 A JP2242785 A JP 2242785A JP 2242785 A JP2242785 A JP 2242785A JP S61181168 A JPS61181168 A JP S61181168A
Authority
JP
Japan
Prior art keywords
insulating film
polycrystalline silicon
floating gate
silicon layer
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2242785A
Other languages
Japanese (ja)
Inventor
Susumu Hasunuma
蓮沼　晋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2242785A priority Critical patent/JPS61181168A/en
Publication of JPS61181168A publication Critical patent/JPS61181168A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling

Abstract

PURPOSE:To increase the area of overlapping by each laminating two layers of polycrystalline silicon layers onto a polycrystalline silicon layer as a floating gate through insulating films and arranging the floating gate so that several polycrystalline silicon layer as upper-most layers is mutually connected electrically. CONSTITUTION:A field insulating film 10 is formed to the surface of a substrate 1, and an insulating film 5 in a region 12, a region 13 and an insulating film 3 are shaped. Arsenic ions are implanted through the insulating film 3 to form a diffusion layer 2. A polycrystalline silicon layer as a floating gate 4 is shaped and the insulating film 5 is formed, a polycrystalline silicon layer as a control gate 6 is shaped, and an insulating film 7 is formed through oxidation. A gate 8 consisting of a polycrystalline silicon layer is shaped, conducted electrically with the floating gate 4 by a contact 9 through patterning, and unified as a floating gate. Source-drain regions and an inter-layer insulating film are formed, and a contact hole is bored and metallic wirings, etc. are shaped. Accordingly, a capacity ratio is removed, thus allowing writing and erasing at high speed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、浮遊ゲート構造を有し、薄いゲート絶縁膜を
介し九トンネル電流によって電気的に情報の書込み・消
去を行なう不揮発性半導体記憶装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a nonvolatile semiconductor memory device that has a floating gate structure and electrically writes and erases information using a tunnel current through a thin gate insulating film. Regarding.

〔従来の技術〕[Conventional technology]

絶縁膜を介して導電層に電子の注入、引出しを行なう手
段を有する。いわゆる浮遊ゲート構造からなる不揮発性
半導体記憶装置は、従来、第５図のような平面構造と、
第６図に示すような断面構造を有していた。なお第６図
は第５図のＡ−Ａ’断面図である。It has means for injecting and extracting electrons into and out of the conductive layer via the insulating film. A nonvolatile semiconductor memory device having a so-called floating gate structure has conventionally had a planar structure as shown in FIG.
It had a cross-sectional structure as shown in FIG. Note that FIG. 6 is a sectional view taken along the line AA' in FIG. 5.

このような構造の記憶装置は、例えば、Ｐ製半導体基板
ＩＫＬＯＣＯ８法を用いてフィールド絶縁ａｔＯ，薄い
ゲート絶縁膜３を設け、Ｎ重拡散層２を薄いゲート絶縁
膜３の下に設け、さらにゲート絶縁膜３の上に浮遊ゲー
ト４．ゲート絶縁膜５゜制御ゲート６を順次重ねて形成
することによりて得られる。なお、第５図において、１
１はドレイン領域、１２はチャンネル領域、１３はトン
ネル電流が流れるトンネル電流領域、１４はソース領域
である８ この記憶装置に情報の書込み・消去を行なう場合には、
Ｎ型拡散層２と制御ゲート６との間に電圧を印加し、Ｎ
型拡散層２−浮遊ゲート４−制御ゲート６の各電極間の
容量結合によって、薄いゲート絶縁膜３（例えば５ｉＱ
２膜）中に高電界を印加し、７アウラー・ノルトノ為イ
ム（ＦｏｗｌｅｒＮｏｒｄｈｅｉｍ）　トンネル電流を
発生することによって、浮遊ゲート４に電子を注入、ま
たは、浮遊ゲート４から電子を引出し、これＫよって制
御ゲート６から見たドレイン領域【１．チャンネル領域
Ｌ２．　　ソース領域１４からなるメモリトランジスタ
のチャンネル領域１２の閾値電圧を変化させる。A memory device having such a structure, for example, uses a P semiconductor substrate IKLOCO8 method to provide field insulation atO, a thin gate insulating film 3, an N heavy diffusion layer 2 under the thin gate insulating film 3, and then a gate insulating film 3. A floating gate 4 is formed on the insulating film 3. This is obtained by sequentially overlapping the gate insulating film 5° and the control gate 6. In addition, in Fig. 5, 1
1 is a drain region, 12 is a channel region, 13 is a tunnel current region where a tunnel current flows, and 14 is a source region.8 When writing and erasing information in this storage device,
A voltage is applied between the N type diffusion layer 2 and the control gate 6, and the N
The thin gate insulating film 3 (for example, 5iQ
By applying a high electric field in the Fowler-Nordheim film (2) and generating a tunnel current, electrons are injected into the floating gate 4 or electrons are extracted from the floating gate 4, which is controlled by K. Drain region seen from gate 6 [1. Channel area L2. The threshold voltage of the channel region 12 of the memory transistor consisting of the source region 14 is changed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

この場合、情報の書込み・消去の速度は、各電極間に印
加される電圧、薄いゲート絶縁膜３の厚さ、各電極間の
容量の比率等によって決定され、速度を速くするために
は、印加電圧を高くシ、薄いゲート絶縁膜３の厚さをよ
シ薄＜シ、浮遊ゲート４−制御ゲート６間の容量を他の
容量に比して相対的に大きくすること（以下、容量比の
改善という。）、がそれぞれ望ましい。しかし、印加電
圧を高めることはデバイスの耐圧等によシ制限され、ま
たゲート絶縁膜の薄膜化もピンホール密度の増加、絶縁
破壊等によって制限されている。容量比の改善を実現す
るためには浮遊ゲート−制御ゲート間のゲート絶縁膜厚
を薄くする方法と、オーバーラツプ面積を大きくする方
法とが考えられるが、絶縁膜厚を薄くするのは両ゲート
間のＩＪ−り（あるいは絶縁破壊）から制限され、オー
バーラツプ面積の増大はデバイスの面積の増大につなが
シ、高集積化の妨げとなる。In this case, the speed of writing and erasing information is determined by the voltage applied between each electrode, the thickness of the thin gate insulating film 3, the ratio of capacitance between each electrode, etc. In order to increase the speed, The applied voltage is increased, the thickness of the thin gate insulating film 3 is made thinner, and the capacitance between the floating gate 4 and the control gate 6 is made relatively larger than other capacitances (hereinafter referred to as capacitance ratio). ) are desirable. However, increasing the applied voltage is limited by the withstand voltage of the device, and making the gate insulating film thinner is also limited by increased pinhole density, dielectric breakdown, and the like. In order to improve the capacitance ratio, two methods are considered: reducing the thickness of the gate insulating film between the floating gate and the control gate, and increasing the overlap area. The increase in the overlap area leads to an increase in the area of the device, which hinders high integration.

従って、本発明の目的は、デバイス面積を増大させるこ
となく、浮遊ゲート−制御ゲート間のオーバーラツプ面
積を増大させることによって、高速の書込み・消去が可
能な高集積密度の不揮発性半導体記憶装置を提供するこ
とにおる。Therefore, an object of the present invention is to provide a high-density nonvolatile semiconductor memory device that can perform high-speed writing and erasing by increasing the overlap area between the floating gate and the control gate without increasing the device area. I am going to do something.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の不揮発性半導体記憶装置は、浮遊ゲート構造を
有し薄いゲート絶縁膜を介したトンネル電流によって電
気的に情報の書込み・消去を行なう不揮発性半導体記憶
装置において、浮遊ゲートとなる第１の多結晶シリコン
層と、第１の絶縁膜を介して前記第１の多結晶シリコン
層の一部を覆うように配置された第２の多結晶シリコン
層と、さらに第２の絶縁膜を介して前記第２の多結晶シ
リコン層の一部を榎うように配置され、前記第１の多結
晶シリコン層と電気的に接続された第３の多結晶シリコ
ン層とを有している。The nonvolatile semiconductor memory device of the present invention has a floating gate structure and electrically writes and erases information by tunneling current through a thin gate insulating film. a polycrystalline silicon layer, a second polycrystalline silicon layer disposed to cover a portion of the first polycrystalline silicon layer via a first insulating film, and further via a second insulating film. The third polycrystalline silicon layer is arranged so as to cover a part of the second polycrystalline silicon layer and is electrically connected to the first polycrystalline silicon layer.

〔実施例〕〔Example〕

以下、本発明の実施例について図面を参照して説明する
。Embodiments of the present invention will be described below with reference to the drawings.

ｓｇｉ図は本発明の一実施例を示す平面図、第２図、第
３図は第１図のＢ−Ｂ／、Ｃ−Ｃ’断面図である。sgi is a plan view showing an embodiment of the present invention, and FIGS. 2 and 3 are cross-sectional views taken along lines BB/ and CC' in FIG. 1.

本実施例は、浮遊ゲート構造を有し薄いゲート絶縁膜３
を介したトンネル電流によりて電気的に情報の書込み・
消去を行なう不揮発性半導体記憶装置において、浮°遊
ゲート４となる第１の多結晶シリコン層と、第１の絶縁
膜としてのゲート絶縁膜５を介して浮遊ゲート４の一部
を覆うように配置された第２の多結晶シリコン層からな
る制御ゲート６と、さらに第２の絶縁膜としてのゲート
絶縁膜７を介して制御ゲート６の上面の両端の一部を除
いて覆うように配置され、浮遊ゲート４とコンタクト９
により電気的に接続された第３の多結晶シリコン層から
なる補助浮遊ゲート８とを含んで構成される。This embodiment has a floating gate structure and a thin gate insulating film 3.
Information can be written electrically by tunneling current through
In a nonvolatile semiconductor memory device that performs erasing, a part of the floating gate 4 is covered with a first polycrystalline silicon layer serving as the floating gate 4 and a gate insulating film 5 serving as the first insulating film. A control gate 6 made of a second polycrystalline silicon layer is disposed, and a gate insulating film 7 as a second insulating film is disposed so as to cover the upper surface of the control gate 6 except for a part of both ends thereof. , floating gate 4 and contact 9
and an auxiliary floating gate 8 made of a third polycrystalline silicon layer electrically connected to the auxiliary floating gate 8.

すなわち、本実施例は第４図、第５図の従来例に対して
、補助浮遊ゲート８を設けた点が異なっている。これに
よシ従来、関与しなかった制御ゲート６の上面積を制御
ゲート−浮遊ゲート間容量に役立たせることができる。That is, this embodiment differs from the conventional examples shown in FIGS. 4 and 5 in that an auxiliary floating gate 8 is provided. This allows the upper area of the control gate 6, which has not been involved in the conventional art, to be used for the capacitance between the control gate and the floating gate.

次に１本実施例の製造方法について説明する。Next, the manufacturing method of this embodiment will be explained.

まず、Ｐ型半導体基板１０表面に通常のＬＯＣＯ８法を
用いてフィールド絶縁膜ｌＯを形成し、メモリトランジ
スタのチャンネル領域１２のゲート絶縁膜５と、トンネ
ル電流領域１３、薄いゲート絶縁膜３とを形成する。（
これらのゲート絶縁膜を酸化膜で形成する場合、それら
の膜厚は、前者は例えば５００人程程度後者は６０〜２
００λ程度である。） 次に、この薄いゲート絶縁膜３を通して、例えば、ヒ素
のイオン注入を行ない、Ｎ型拡散層２を形成する。ここ
で、Ｎ型拡散層２は後にメモリトランジスタのドレイン
領域１１と電気的に接続できるように、後の浮遊ゲート
４．制御ゲート６゜補助浮遊ゲート８の外側まで延在さ
せておく必要がある。さらに、浮遊ゲート４となる多結
晶シリコン層を形成、パターニングし、表面ｔ−ｍ化し
てゲート絶縁膜５ｔｌ−形成し、制御ゲート６となる多
結晶シリコン層を形成、パターニングした後、表面を酸
化してゲート絶縁膜７を形成する。このとさ、制御ゲー
ト６は浮遊ゲート４の上面と側面を覆うように形成され
るが、浮遊ゲート４の一部は制御ゲート６の外にまで突
出させておき、その部分にコンタクト９を開孔させ、絶
縁膜を除去して、その部分の浮遊ゲート４の表面を露出
させる。First, a field insulating film 1O is formed on the surface of the P-type semiconductor substrate 10 using the usual LOCO8 method, and a gate insulating film 5 of the channel region 12 of the memory transistor, a tunnel current region 13, and a thin gate insulating film 3 are formed. do. (
When these gate insulating films are formed of oxide films, their film thickness is, for example, about 500 for the former, and 60 to 2 for the latter.
It is about 00λ. ) Next, ions of, for example, arsenic are implanted through this thin gate insulating film 3 to form an N-type diffusion layer 2. Here, the N-type diffusion layer 2 is connected to the floating gate 4 so that it can be electrically connected to the drain region 11 of the memory transistor later. It is necessary to extend the control gate 6° to the outside of the auxiliary floating gate 8. Furthermore, after forming and patterning a polycrystalline silicon layer that will become the floating gate 4, forming a gate insulating film 5tl- by making the surface t-m, and forming and patterning a polycrystalline silicon layer that will become the control gate 6, the surface is oxidized. Then, a gate insulating film 7 is formed. At this point, the control gate 6 is formed so as to cover the top and side surfaces of the floating gate 4, but a part of the floating gate 4 is made to protrude to the outside of the control gate 6, and a contact 9 is opened in that part. A hole is made and the insulating film is removed to expose the surface of the floating gate 4 in that portion.

その後、３層めの多結晶シリコン層からなる補助浮遊ゲ
ート８を形成し、パターニングを行ない。Thereafter, an auxiliary floating gate 8 made of a third polycrystalline silicon layer is formed and patterned.

コンタクト９で浮遊ゲート４と電気的に導通させること
により、浮遊ゲートとして一体化する。かくして、浮遊
ゲート−制御ゲート間の容量は制御ゲート６の上下両面
を利用して形成することができる。By electrically conducting with the floating gate 4 through the contact 9, they are integrated as a floating gate. In this way, the capacitance between the floating gate and the control gate can be formed using both the upper and lower surfaces of the control gate 6.

この後は、従来のＭＯ８型半導体装置の製造方法と同様
に、ソース、ドレイン領域、眉間絶縁膜を形成し、コン
タクト孔の開孔、金属配線等を施す。After this, in the same manner as in the conventional manufacturing method of an MO8 type semiconductor device, a source, a drain region, an insulating film between the eyebrows are formed, and contact holes are formed, metal wiring, etc. are performed.

以上の説明から明らかな様に、本実施例によれは、浮遊
ゲート−制御ゲート間のゲート絶縁膜厚を一定にしたま
まで、かつ、メモリセル面積も一定のままで、浮遊ゲー
トと制御ゲート間の容量を約２倍近くにまで高めること
ができるため、デバイスの信頼性、集積度を何ら損なう
ことなく容量比の改善が実現され、情報の書込み・消去
の速度の高速化が可能となる。As is clear from the above explanation, according to this embodiment, the thickness of the gate insulating film between the floating gate and the control gate remains constant, and the area of the memory cell remains constant. By nearly doubling the capacity between the two, it is possible to improve the capacity ratio without any loss in device reliability or degree of integration, making it possible to increase the speed of writing and erasing information. .

このようなメモリ特性の改善例をｇ４図に示す。An example of such improvement in memory characteristics is shown in Figure g4.

これは浮遊ゲート−制御ゲート間の絶縁膜厚、メモリセ
ルの面積等を同一とし、構造のみを従来のものと比較し
たものであシ、同一の閾値電圧を得るための時間は１桁
近く改善されていることがわかる。This compares only the structure with the conventional one, keeping the insulating film thickness between the floating gate and control gate, the area of the memory cell, etc. the same, and the time to obtain the same threshold voltage is improved by nearly an order of magnitude. I can see that it is being done.

〔発明の効果〕〔Effect of the invention〕

以上、詳細述べてきたように、本発明によれば、上記手
段により、 イ、デバイスの信頼性上問題となる浮遊ゲート−制御ゲ
ート間の絶縁膜の薄膜化。As described in detail above, according to the present invention, by the above means, (a) thinning of the insulating film between the floating gate and the control gate, which poses a problem in terms of device reliability;

口、高密度集積化の妨げとなる浮遊ゲート−制御ゲート
のオーバーラツプ面積の拡大 というような問題点を伴わずに、容量比の改善を行なう
ことが可能となシ、高速の書込み・消去が可能な高集積
密度の不揮発性半導体記憶装置が得られる。First, it is possible to improve the capacitance ratio without the problems of increasing the floating gate-control gate overlap area, which hinders high-density integration, and enables high-speed writing and erasing. A nonvolatile semiconductor memory device with a high integration density can be obtained.

【図面の簡単な説明】 第１図は本発明の一実施例を示す平面・図、第２図、第
３図は第１図のＢ−８’、Ｃ−Ｃ／断面図、第４図は本
発明と従来の不揮発性半導体記憶装置の特性を比較して
示した特性図、第５図は一従来例を示す平面図、第す図
は第Ｓ図のＡ−Ａ’断面図である。 １・・・・・・Ｐ型半導体基板、２・・・・・・Ｎ型拡
散層、３・・・・・・薄いゲート絶縁膜、４・・・・・
・浮遊ゲート、５゜７・・・・・・ゲート絶縁膜、８・
・・・・・補助浮遊ゲート、６・・・・・・制御ゲート
、９・・・・・・コンタクト、ＩＯ・・・・・・フィー
ルド絶縁膜、１１・・・・・・ドレイン領域、」２・・
・・・・チャンネル領域、１３・・・・・・トンネル電
流領域、１４・・・・・・ソース領域。 ＼ニー５，５ ／ｌ　どｌ４−ｎｔ＊” 予（ゾ Ｌ！、（ｎ−シ［ン一 峯４回[Brief Description of the Drawings] Figure 1 is a plan view showing an embodiment of the present invention, Figures 2 and 3 are cross-sectional views taken along line B-8' and CC in Figure 1, and Figure 4 is a sectional view taken along line B-8' and CC in Figure 1. 5 is a characteristic diagram comparing the characteristics of the present invention and a conventional nonvolatile semiconductor memory device, FIG. 5 is a plan view showing a conventional example, and FIG. . 1... P-type semiconductor substrate, 2... N-type diffusion layer, 3... thin gate insulating film, 4...
・Floating gate, 5°7...Gate insulating film, 8・
... Auxiliary floating gate, 6 ... Control gate, 9 ... Contact, IO ... Field insulating film, 11 ... Drain region." 2...
... Channel region, 13 ... Tunnel current region, 14 ... Source region. \knee5,5 /l dol4-nt*” Yo(zoL!, (n-shi[nichimine 4 times

Claims (1)

【特許請求の範囲】[Claims] 　浮遊ゲート構造を有し薄いゲート絶縁膜を介したトン
ネル電流によって電気的に情報の書込み・消去を行なう
不揮発性半導体記憶装置において、浮遊ゲートとなる第
１の多結晶シリコン層と、第１の絶縁膜を介して前記第
１の多結晶シリコン層の一部を覆うように配置された第
２の多結晶シリコン層と、さらに第２の絶縁膜を介して
前記第２の多結晶シリコン層の一部を覆うように配置さ
れ、前記第１の多結晶シリコン層と電気的に接続された
第３の多結晶シリコン層とを含むことを特徴とする不揮
発性半導体記憶装置。In a nonvolatile semiconductor memory device that has a floating gate structure and electrically writes and erases information by tunneling current through a thin gate insulating film, a first polycrystalline silicon layer serving as a floating gate and a first insulating layer are used. A second polycrystalline silicon layer is disposed to cover a part of the first polycrystalline silicon layer through a film, and one of the second polycrystalline silicon layers is further disposed through a second insulating film. A nonvolatile semiconductor memory device, comprising: a third polycrystalline silicon layer disposed so as to cover the third polycrystalline silicon layer and electrically connected to the first polycrystalline silicon layer.
JP2242785A 1985-02-07 1985-02-07 Nonvolatile semiconductor memory device Pending JPS61181168A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2242785A JPS61181168A (en) 1985-02-07 1985-02-07 Nonvolatile semiconductor memory device

Applications Claiming Priority (1)

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JP2242785A JPS61181168A (en) 1985-02-07 1985-02-07 Nonvolatile semiconductor memory device

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Cited By (12)

* Cited by examiner, † Cited by third party
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JPS6384168A (en) * 1986-09-29 1988-04-14 Toshiba Corp Nonvolatile semiconductor memory device
JPH01160058A (en) * 1987-12-16 1989-06-22 Seiko Instr & Electron Ltd Semiconductor nonvolatile memory
JPH03285359A (en) * 1990-04-02 1991-12-16 Matsushita Electron Corp Semiconductor storage device and manufacture thereof
US5194925A (en) * 1990-02-22 1993-03-16 Mitsubishi Denki Kabushiki Kaisha Electrically programmable non-volatie semiconductor memory device
US5229631A (en) * 1990-08-15 1993-07-20 Intel Corporation Erase performance improvement via dual floating gate processing
US5313421A (en) * 1992-01-14 1994-05-17 Sundisk Corporation EEPROM with split gate source side injection
JPH07288291A (en) * 1994-04-19 1995-10-31 Nec Corp Non-volatile semiconductor memory device
US5712180A (en) * 1992-01-14 1998-01-27 Sundisk Corporation EEPROM with split gate source side injection
US6222762B1 (en) 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
US6664587B2 (en) 1996-02-28 2003-12-16 Sandisk Corporation EEPROM cell array structure with specific floating gate shape
KR100429083B1 (en) * 1998-11-16 2004-04-29 매트릭스 세미컨덕터 인코포레이티드 Vertically stacked field programmable nonvolatile memory and method of fabrication
US6914288B2 (en) 2002-10-09 2005-07-05 Denso Corporation EEPROM and EEPROM manufacturing method

Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0586075B2 (en) * 1986-09-29 1993-12-09 Toshiba Kk
JPS6384168A (en) * 1986-09-29 1988-04-14 Toshiba Corp Nonvolatile semiconductor memory device
JPH01160058A (en) * 1987-12-16 1989-06-22 Seiko Instr & Electron Ltd Semiconductor nonvolatile memory
US5378643A (en) * 1990-02-22 1995-01-03 Mitsubishi Denki Kabushiki Kaisha Electrically programmable non-volatile semiconductor memory device and manufacturing method thereof
US5194925A (en) * 1990-02-22 1993-03-16 Mitsubishi Denki Kabushiki Kaisha Electrically programmable non-volatie semiconductor memory device
JPH03285359A (en) * 1990-04-02 1991-12-16 Matsushita Electron Corp Semiconductor storage device and manufacture thereof
US5229631A (en) * 1990-08-15 1993-07-20 Intel Corporation Erase performance improvement via dual floating gate processing
US5910915A (en) * 1992-01-14 1999-06-08 Sandisk Corporation EEPROM with split gate source side injection
US6317364B1 (en) 1992-01-14 2001-11-13 Sandisk Corporation Multi-state memory
US5712180A (en) * 1992-01-14 1998-01-27 Sundisk Corporation EEPROM with split gate source side injection
US5776810A (en) * 1992-01-14 1998-07-07 Sandisk Corporation Method for forming EEPROM with split gate source side injection
US5847996A (en) * 1992-01-14 1998-12-08 Sandisk Corporation Eeprom with split gate source side injection
US5883409A (en) * 1992-01-14 1999-03-16 Sandisk Corporation EEPROM with split gate source side injection
US5910925A (en) * 1992-01-14 1999-06-08 Sandisk Corporation EEPROM with split gate source side injection
US5313421A (en) * 1992-01-14 1994-05-17 Sundisk Corporation EEPROM with split gate source side injection
US6002152A (en) * 1992-01-14 1999-12-14 Sandisk Corporation EEPROM with split gate source side injection with sidewall spacers
US6222762B1 (en) 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
US6275419B1 (en) 1992-01-14 2001-08-14 Sandisk Corporation Multi-state memory
US6954381B2 (en) 1992-01-14 2005-10-11 Sandisk Corporation EEPROM with split gate source side injection with sidewall spacers
US6317363B1 (en) 1992-01-14 2001-11-13 Sandisk Corporation Multi-state memory
US6856546B2 (en) 1992-01-14 2005-02-15 Sandisk Corporation Multi-state memory
JPH07288291A (en) * 1994-04-19 1995-10-31 Nec Corp Non-volatile semiconductor memory device
US6704222B2 (en) 1996-02-28 2004-03-09 Sandisk Corporation Multi-state operation of dual floating gate array
US6664587B2 (en) 1996-02-28 2003-12-16 Sandisk Corporation EEPROM cell array structure with specific floating gate shape
US6861700B2 (en) 1996-02-28 2005-03-01 Sandisk Corporation Eeprom with split gate source side injection
US6862218B2 (en) 1997-08-07 2005-03-01 Sandisk Corporation Multi-state memory
KR100429083B1 (en) * 1998-11-16 2004-04-29 매트릭스 세미컨덕터 인코포레이티드 Vertically stacked field programmable nonvolatile memory and method of fabrication
US6914288B2 (en) 2002-10-09 2005-07-05 Denso Corporation EEPROM and EEPROM manufacturing method

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