JPH0223672A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH0223672A JPH0223672A JP63174488A JP17448888A JPH0223672A JP H0223672 A JPH0223672 A JP H0223672A JP 63174488 A JP63174488 A JP 63174488A JP 17448888 A JP17448888 A JP 17448888A JP H0223672 A JPH0223672 A JP H0223672A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- floating gate
- control gate
- conductive layer
- floating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 24
- 238000007667 floating Methods 0.000 claims abstract description 67
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 230000008878 coupling Effects 0.000 abstract description 10
- 238000010168 coupling process Methods 0.000 abstract description 10
- 238000005859 coupling reaction Methods 0.000 abstract description 10
- 230000007261 regionalization Effects 0.000 abstract description 3
- 238000003475 lamination Methods 0.000 abstract 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 210000004709 eyebrow Anatomy 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 230000005689 Fowler Nordheim tunneling Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体記憶装置に係り、特に１ビツトが１
個のトランジスタで構成される電気的書き換え可能な読
み出し専用メモリＥＥＦＲＯＭの改良に関するものであ
る。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, and in particular, the present invention relates to a semiconductor memory device in which one bit is one bit.
This invention relates to an improvement of an electrically rewritable read-only memory EEFROM which is composed of transistors.
従来のＥＥＰＲＯＭは例えば特公昭６２−４１４３１号
公報に示されているように基本セルは２トランジスタで
構成されていたが、集積度の向上に従って、チップ面積
が増大する欠点があった。この点を改良するために１ト
ランジスタ構成で電気的に一括消去できるＥＥＦＲＯＭ
、即ちフラッシュＥＥＰＲＯＭが提案されている。A conventional EEPROM, as disclosed in Japanese Patent Publication No. 62-41431, has a basic cell consisting of two transistors, but has the disadvantage that the chip area increases as the degree of integration improves. To improve this point, EEFROM, which can be electrically erased all at once with a one-transistor configuration,
, that is, a flash EEPROM has been proposed.
第３図は例えばＩ ＥＥＦ、 ジャーナル オブソリ
ソドーステート ケーキツク。第ＳＣ−２２巻。Figure 3 shows, for example, IEEF, Journal of Solid State Cakes. Volume SC-22.
第５号、 １９８７年、 ６７６−６８３頁（Ｊ、
５ｏｌｉｄ−３ｔａｔｅ Ｃ１ｒｃｕｉｔｓ、 ｖｏｌ
、５ｃ−２２，Ｎｏ、５．１９８７． ｐｐ、６７６−
６８３）に示されている従来の１トランジスタ型フラッ
シュＥＥＰＲＯＭを示す平面図と断面図である。この図
において、３１は半導体基板、３２は浮遊ゲート、３３
は制御ゲート （ワード線）、３４はソ−ス拡散領域、
３５はドレイン拡散領域、３６はアルミ配線（ビット線
）、３７はアルミ配線３６とドレイン３５との接続用コ
ンタクトホール、３８は眉間絶縁膜、３９はフィールド
酸化膜（分離領域）、４０はフィールド酸化膜３９下の
チャネルストッパ、４１は浮遊ゲート３２と基板３１間
のゲート酸化膜、４２は制御ゲート３３と基板３１間の
ゲート酸化膜、４３は制御ゲート３３と浮遊ゲート３２
間の眉間絶縁膜である。第３図（ａ）が平面図であり、
第３図（ｂｌは（ａ）のＡ−Ａ線での断面図、第３図（
Ｃ１は（ａ）のＢ−Ｂ線での断面図である。No. 5, 1987, pp. 676-683 (J,
5olid-3tate C1rcuits, vol.
, 5c-22, No. 5.1987. pp, 676-
FIG. 683) is a plan view and a cross-sectional view showing a conventional one-transistor flash EEPROM shown in FIG. In this figure, 31 is a semiconductor substrate, 32 is a floating gate, and 33 is a semiconductor substrate.
is a control gate (word line), 34 is a source diffusion region,
35 is a drain diffusion region, 36 is an aluminum wiring (bit line), 37 is a contact hole for connecting the aluminum wiring 36 and the drain 35, 38 is an insulating film between the eyebrows, 39 is a field oxide film (separation region), 40 is a field oxide A channel stopper under the film 39; 41 a gate oxide film between the floating gate 32 and the substrate 31; 42 a gate oxide film between the control gate 33 and the substrate 31; 43 a gate oxide film between the control gate 33 and the floating gate 32;
This is the insulating membrane between the eyebrows. FIG. 3(a) is a plan view,
Figure 3 (bl is a sectional view taken along line A-A in (a), Figure 3 (
C1 is a sectional view taken along line BB in (a).
この図に示すように従来のフラッシュＥＥＰＲＯＭでは
、浮遊ゲート３２のドレイン側の端部は制御ゲート３３
とセルファラインになった積層構造をしており、浮遊ゲ
ート３２のその他の端部は制御ゲート３３で被覆されて
いた。このため、（ｂ）に示すようにメモリトランジス
タのチャネル部は浮遊ゲート３２と制御ゲート３３が直
列接続した構造をしていた。As shown in this figure, in the conventional flash EEPROM, the end of the floating gate 32 on the drain side is connected to the control gate 33.
The floating gate 32 had a laminated structure with a self-lined structure, and the other end of the floating gate 32 was covered with a control gate 33. For this reason, the channel portion of the memory transistor had a structure in which a floating gate 32 and a control gate 33 were connected in series, as shown in FIG.
従来のフラッシュＥＥＰＲＯＭは以上のように構成され
ているので、次のような問題点があった。Since the conventional flash EEPROM is configured as described above, it has the following problems.
制御ゲートと浮遊ゲートとのマスク合わせにずれが生ず
ると、□浮遊ゲートのチャネル長および制御ゲートと浮
遊ゲートとの積層部の面積が変化し、一定しない。この
ため、メモリセルの結合容量が一定せず、メモリセルの
書き込み深さや、読み出し電流がバラつく。また、メモ
リトランジスタのチャネル長が長いため、セル面積が比
較的大きくチャネル抵抗も高くなり、セル電流が小さく
なる。If a misalignment occurs in the mask alignment between the control gate and the floating gate, the channel length of the floating gate and the area of the laminated portion of the control gate and the floating gate change and are not constant. Therefore, the coupling capacitance of the memory cells is not constant, and the write depth and read current of the memory cells vary. Furthermore, since the channel length of the memory transistor is long, the cell area is relatively large, the channel resistance is high, and the cell current is small.
この発明は上記のような問題点を解消するためになされ
たもので、セル面積が小さく、セルファライン的にチャ
ネル長が決まり、制御ゲートと浮遊ゲートとの容量結合
比が一定にできる半導体記憶装置を得ることを目的とす
る。This invention was made to solve the above-mentioned problems, and provides a semiconductor memory device with a small cell area, a channel length determined by a cell line, and a constant capacitive coupling ratio between a control gate and a floating gate. The purpose is to obtain.
この発明に係る半導体記憶装置は、浮遊ゲートを形成し
た後、浮遊ゲート上と浮遊ゲートのソース側側壁に制御
ゲートを形成する際、側壁部の制御ゲートを自己整合で
形成するようにしたものである。In the semiconductor memory device according to the present invention, after forming the floating gate, when forming the control gate on the floating gate and on the sidewall on the source side of the floating gate, the control gate on the sidewall is formed in a self-aligned manner. be.
この発明においては、浮遊ゲートを形成した後、制御ゲ
ートを形成する際、浮遊ゲート側壁部の制御ゲートは自
己整合的に形成することにより、制御ゲートはソース側
側壁部のみで基板との間でチャネルを形成するため、メ
モリトランジスタのチャネル長は実質的に浮遊ゲート長
で決まることになり、セル面積が小さくなる。また、浮
遊ゲートと制御ゲート間の容量結合比は大部分が浮遊ゲ
ート上の制御ゲートと浮遊ゲート間の積層部分で決まる
ため、パターン形成時のアライメントずれによる容量結
合比の変動はほとんど生じない。In this invention, when forming the control gate after forming the floating gate, the control gate on the side wall of the floating gate is formed in a self-aligned manner, so that the control gate is connected to the substrate only on the side wall on the source side. Since a channel is formed, the channel length of the memory transistor is substantially determined by the floating gate length, reducing the cell area. Furthermore, since the capacitive coupling ratio between the floating gate and the control gate is mostly determined by the laminated portion between the control gate and the floating gate on the floating gate, there is almost no variation in the capacitive coupling ratio due to misalignment during pattern formation.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図（ａ）はこの発明の一実施例による半導体記憶装
置を示す平面図、第１図（′ｂ）は第１図（ａｌのＡＡ
線での断面図、第１図（Ｃ）は第１図（ａｌのＢ−Ｂ線
での断面図である。第１図において、１は半導体基板、
２は浮遊ゲート、３は制御ゲート（ワード線）、４はメ
モリトランジスタのソース領域、５はメモリトランジス
タのドレイン領域、６はアルミ配ｖＡ（ビット線）、７
はアルミ配線６とドレイン５との接続コンタクトホール
、８は眉間絶縁膜、９はフィールド酸化膜（分離領域）
、１０はフィールド酸化膜９下のチャネルストッパ、１
１は浮遊ゲート２と基板１間のゲート酸化膜、１２は制
御ゲート３と基板１間のゲート酸化膜、１３は制御ゲー
ト３と浮遊ゲート２間の眉間絶縁膜である。FIG. 1(a) is a plan view showing a semiconductor memory device according to an embodiment of the present invention, and FIG. 1('b) is a plan view showing a semiconductor memory device according to an embodiment of the invention.
1(C) is a sectional view taken along line B-B of FIG. 1 (al). In FIG. 1, 1 is a semiconductor substrate;
2 is a floating gate, 3 is a control gate (word line), 4 is a source region of a memory transistor, 5 is a drain region of a memory transistor, 6 is an aluminum wiring (bit line), 7
is a contact hole for connecting the aluminum wiring 6 and the drain 5, 8 is an insulating film between the eyebrows, and 9 is a field oxide film (separation region).
, 10 is a channel stopper under the field oxide film 9, 1
1 is a gate oxide film between the floating gate 2 and the substrate 1, 12 is a gate oxide film between the control gate 3 and the substrate 1, and 13 is an insulating film between the eyebrows between the control gate 3 and the floating gate 2.
この半導体記憶装置は、半導体基板１の主表面上に形成
される浮遊ゲートトランジスタと制御ゲートトランジス
タとを含む。浮遊ゲートトランジスタの浮遊ゲート２は
、半導体基板１の主表面上に形成されたドレイン５と絶
縁膜１１を介して一部が重なっている。制御ゲートトラ
ンジスタは制御ゲート３と半導体基板１の主表面上の絶
縁膜１２とを含む。制御ゲート３は、眉間絶縁膜１３を
介して浮遊ゲート２上に積層している。また浮遊ゲート
２のソース側側壁部には絶縁膜を介して制御ゲート３が
配置される。浮遊ゲート２の側壁部に配置された制御ゲ
ート３と浮遊ゲート２の上部に積層された制御ゲート３
とは、第１図ｆａ＋に示されているように同一ワード線
内の少なくとも一ケ所で接続している。浮遊ゲートトラ
ンジスタと制御ゲートトランジスタはソース４とドレイ
ン５に対して直列に配置され、浮遊ゲート２がドレイン
側に制御ゲート３がソース側に位置する。制御ゲートト
ランジスタのゲート絶縁膜１２と浮遊ゲートトランジス
タのゲート絶縁膜１１とはその膜厚が同一であっても、
異なっていてもどちらでもよい。ソース４とドレイン５
は半導体基板１と逆導電型を持ち、制御ゲート３および
浮遊ゲート２に対して自己整合で形成される。This semiconductor memory device includes a floating gate transistor and a control gate transistor formed on the main surface of semiconductor substrate 1. Floating gate 2 of the floating gate transistor partially overlaps drain 5 formed on the main surface of semiconductor substrate 1 with insulating film 11 in between. The control gate transistor includes a control gate 3 and an insulating film 12 on the main surface of the semiconductor substrate 1. The control gate 3 is stacked on the floating gate 2 via the glabella insulating film 13. Further, a control gate 3 is arranged on the side wall portion of the floating gate 2 on the source side with an insulating film interposed therebetween. Control gate 3 arranged on the side wall of floating gate 2 and control gate 3 stacked on top of floating gate 2
and are connected at least at one place within the same word line, as shown in FIG. 1 fa+. The floating gate transistor and the control gate transistor are arranged in series with the source 4 and drain 5, with the floating gate 2 located on the drain side and the control gate 3 located on the source side. Even if the gate insulating film 12 of the control gate transistor and the gate insulating film 11 of the floating gate transistor have the same film thickness,
It doesn't matter if they are different. source 4 and drain 5
has a conductivity type opposite to that of the semiconductor substrate 1 and is formed in self-alignment with the control gate 3 and floating gate 2.
また、第２図（ａ）はこの実施例による半導体記憶装置
の１ビツト等価回路図、第２図（ｂ）は４ビツトをアレ
イ配置したときの等価回路間である。FIG. 2(a) is a 1-bit equivalent circuit diagram of the semiconductor memory device according to this embodiment, and FIG. 2(b) is an equivalent circuit diagram when 4 bits are arranged in an array.
次に、第１図（ａ）ないし第１図（ｅ）、第２図（ａｌ
、 （ｂ）を参照して動作について述べる。浮遊ゲート
２に電子が注入されるときには、制御ゲート３には書き
込み電圧■ＣＰ ＋ ドレイン５には■ＤＰが印加さ
れ、ソース４と基板１は接地電位に保たれる。このとき
浮遊ゲート２の電位は制御ゲート３と浮遊ゲート２間の
容量結合によりＶｔｐａなる。その結果、・制御ゲート
トランジスタと浮遊ゲートトランジスタはオン状態とな
る。そして、ドレイン端近傍でいわゆるチャネルホット
エレクトロンの一部がゲート絶縁膜１１のポテンシャル
バリアを越えて浮遊ゲート２へ突入し、そこで保持され
る。この動作は通常のＥＰＲＯＭの書き込み動作と同じ
である。Next, Fig. 1(a) to Fig. 1(e), Fig. 2(al
, (b), the operation will be described. When electrons are injected into the floating gate 2, a write voltage CP+ is applied to the control gate 3, DP is applied to the drain 5, and the source 4 and substrate 1 are kept at ground potential. At this time, the potential of the floating gate 2 becomes Vtpa due to capacitive coupling between the control gate 3 and the floating gate 2. As a result, the control gate transistor and floating gate transistor are turned on. Then, near the drain end, a part of the so-called channel hot electrons crosses the potential barrier of the gate insulating film 11, enters the floating gate 2, and is held there. This operation is the same as a normal EPROM write operation.
浮遊ゲート２から電子を引き抜くときには、制御ゲート
３と基板１は接地電位として、ソース４は浮遊状態にす
る。このときドレイン５には消去電位ＶＤＥが印加され
、ドレイン５と浮遊ゲート２の重なり部分のゲート絶縁
膜１１を通してファウラー−ノルドハイム トンネリン
グ（Ｆｏｗｌｅｒ−Ｎｏｒｄｈｅｉｍ Ｔｕｎｎｅｌｉ
ｎｇ）によって浮遊ゲート２中の電子をドレイン５へ引
き抜く。When extracting electrons from the floating gate 2, the control gate 3 and the substrate 1 are set to a ground potential, and the source 4 is placed in a floating state. At this time, the erase potential VDE is applied to the drain 5, and Fowler-Nordheim tunneling is performed through the gate insulating film 11 in the overlapped portion of the drain 5 and the floating gate 2.
ng), the electrons in the floating gate 2 are extracted to the drain 5.
読み出し時には、制御ゲート３を読み出し電位ＶＣＲと
し制御ゲートトランジスタをオン状態にする。このとき
ソース４は接地電位とし、ドレイン５に電圧■、が印加
される。この状態で浮遊ゲートトランジスタがオンかオ
フかによってメモリトランジスタ全体のオン／オフが決
まり、浮遊ゲート２のバイナリ状態が判定される。なお
、書き込み時と読み出し時には、選択されたビット線と
ワード線のみに所定の電圧が印加される。消去時、即ち
浮遊ゲート２からドレイン５へ電子を引き抜くときには
、全てのビット線に消去電圧■□が印加され、全てのソ
ース線は浮遊状態にされる。この結果、消去は全ビット
−括で行われる。また、電圧Ｖｃｐ、 Ｖ□＋ Ｖ
ＣＲＩ ＶＤＲは同一であってもいいし、異なっていて
もかまわない。At the time of reading, the control gate 3 is set to the read potential VCR and the control gate transistor is turned on. At this time, the source 4 is set to the ground potential, and the drain 5 is applied with a voltage . In this state, whether the floating gate transistor is on or off determines whether the entire memory transistor is on or off, and the binary state of the floating gate 2 is determined. Note that during writing and reading, a predetermined voltage is applied only to selected bit lines and word lines. During erasing, that is, when electrons are extracted from the floating gate 2 to the drain 5, the erasing voltage ■□ is applied to all bit lines, and all source lines are placed in a floating state. As a result, erasing is performed for all bits at once. In addition, the voltage Vcp, V□+V
The CRI VDRs may be the same or different.
この実施例に係るフラッシュＥＥＰＲＯＭの製造プロセ
スを第４図（ａ）ないし第４図（ｆ）を参照して説明す
る。まず基板１が準備され、その上に素子分離用フィー
ルド酸化膜９とチャネルストッパ１０が形成される（第
４図（ａ））。次にゲート絶縁膜１１が形成され、第１
の導電層２がゲート絶縁層１１の上に形成される。この
第１の導電層２はｎ型にドープされている。第１導電層
２上に例えばシリコン酸化膜、シリコン窒化膜の２層構
造を持つ絶縁層１３が形成され、浮遊ゲート２のパター
ンがエツチングによ、て形成される（第４図（ｂ））。The manufacturing process of the flash EEPROM according to this embodiment will be explained with reference to FIGS. 4(a) to 4(f). First, a substrate 1 is prepared, and a field oxide film 9 for element isolation and a channel stopper 10 are formed thereon (FIG. 4(a)). Next, a gate insulating film 11 is formed, and the first gate insulating film 11 is formed.
A conductive layer 2 is formed on the gate insulating layer 11 . This first conductive layer 2 is n-type doped. An insulating layer 13 having a two-layer structure of, for example, a silicon oxide film and a silicon nitride film is formed on the first conductive layer 2, and a pattern of the floating gate 2 is formed by etching (FIG. 4(b)). .
浮遊ゲート２の存在しない領域の第１ゲート絶縁膜１１
がエツチングにより除去された後、第２ゲート絶縁膜１
２が熱酸化によって形成される。このとき、浮遊ゲート
２上の絶縁膜１３は表面がシリコン窒化膜のためほとん
ど酸化されないが、絶縁膜１３の存在しない浮遊ゲート
２の側壁部は比較的厚いシリコン酸化膜が形成される。First gate insulating film 11 in a region where floating gate 2 does not exist
is removed by etching, the second gate insulating film 1 is removed by etching.
2 is formed by thermal oxidation. At this time, the surface of the insulating film 13 on the floating gate 2 is a silicon nitride film and is hardly oxidized, but a relatively thick silicon oxide film is formed on the sidewalls of the floating gate 2 where the insulating film 13 does not exist.
次に第２の導電層３がデポされる（第４図（Ｃ））。こ
の後、ｎ型にドープされた第２の導電層３のパターンが
フォトリソグラフィーとエツチング技術によって形成さ
れる。このときのエツチングに非等方性エツチングを用
いることにより浮遊ゲート２の側壁部に第２の導電層３
ａを、いわゆるサイドウオールとして自己整合で残す（
第４図（ｄ））。次に第２導電層３上のフォトレジスト
２０を残したまま、新たにフォトレジストを塗布し、ソ
ース側に相当する側壁部の第２導電層３ａを被覆し、ド
レイン側に相当する側壁部の第２導電層３ｂを被覆しな
いようなフォトレジストパターンを形成した後、エツチ
ングにより第２導電層３ｂを除去し、その後金てのフォ
トレジストを除去する（第４図（ｅ））。Next, a second conductive layer 3 is deposited (FIG. 4(C)). After this, a pattern of the n-type doped second conductive layer 3 is formed by photolithography and etching techniques. By using anisotropic etching at this time, a second conductive layer 3 is formed on the side wall of the floating gate 2.
a is left in self-alignment as a so-called sidewall (
Figure 4(d)). Next, while leaving the photoresist 20 on the second conductive layer 3, a new photoresist is applied to cover the second conductive layer 3a on the side wall corresponding to the source side, and coat the second conductive layer 3a on the side wall corresponding to the drain side. After forming a photoresist pattern that does not cover the second conductive layer 3b, the second conductive layer 3b is removed by etching, and then the gold photoresist is removed (FIG. 4(e)).
以下通常のプロセスフローに従って、基板１と逆導電型
を有するソース領域４．ドレイン領域５が形成され、眉
間絶縁膜８が被着される。さらにコンタクトホール７と
アルミ配線６などが形成され（第４図（ｆ））、最後に
表面保護膜が形成されこの実施例に係るフラッシュＥＥ
ＰＲＯＭが完成される。Thereafter, according to the normal process flow, source regions 4. A drain region 5 is formed and a glabellar insulating film 8 is deposited. Further, a contact hole 7, an aluminum wiring 6, etc. are formed (FIG. 4(f)), and finally a surface protection film is formed to form a flash EE according to this embodiment.
PROM is completed.
このようなフラッシュＥＥＰＲＯＭでは、セルファライ
ン的に制御ゲートトランジスタのチャネル長が決まり、
メモリトランジスタのチャネル長は実質的に浮遊ゲート
長で決まることになるので、従来のフラッシュＥＥＰＲ
ＯＭに比べてセル面積が小さくなる。また、制御ゲート
と浮遊ゲートとの積層部の面積が一定となるので、制御
ゲートと浮遊ゲートとの容量結合比が一定となる。In such a flash EEPROM, the channel length of the control gate transistor is determined by the self-line,
Since the channel length of a memory transistor is essentially determined by the floating gate length, conventional flash EEPR
The cell area is smaller than that of OM. Further, since the area of the stacked portion of the control gate and the floating gate is constant, the capacitive coupling ratio between the control gate and the floating gate is constant.
以上のように、この発明によれば、浮遊ゲートのソース
側側壁に制御ゲートを自己整合で形成するようにしたの
で、パターン形成時のアライメントずれによる結合容量
の変動がほとんどなく、セル面積もほとんど増大させる
ことなしに、高集積化に適した半導体記憶装置を得られ
る効果がある。As described above, according to the present invention, since the control gate is formed on the source side wall of the floating gate in a self-aligned manner, there is almost no variation in coupling capacitance due to misalignment during pattern formation, and the cell area is also small. There is an effect that a semiconductor memory device suitable for high integration can be obtained without increasing the size.
第１図はこの発明の一実施例によるフラッシュＥＥＰＲ
ＯＭを示す図、第２図はその等価回路を示す図、第３図
は従来のフラッシュＥＥＰＲＯＭを示す図、第４図は第
１図のフラッシュＥＥＰＲＯＭの製造プロセスを説明す
るための図である。
図において、１は半導体基板、２は浮遊ゲート、３は制
御ゲート、４はソース領域、５はドにイン領域、６はア
ルミ配線、７はコンタクトホール、８は眉間絶縁膜、９
はフィールド酸化膜、１０はチャネルストッパ、１１は
浮遊ゲート絶縁膜、１２は制御ゲート絶縁膜、１３は浮
遊ゲートと制御ゲート間の眉間絶縁膜。
なお、図中、同一符号は同一または相当部分を示す。FIG. 1 shows a flash EEPR according to an embodiment of the present invention.
2 is a diagram showing its equivalent circuit, FIG. 3 is a diagram showing a conventional flash EEPROM, and FIG. 4 is a diagram for explaining the manufacturing process of the flash EEPROM shown in FIG. 1. In the figure, 1 is a semiconductor substrate, 2 is a floating gate, 3 is a control gate, 4 is a source region, 5 is a dome region, 6 is an aluminum wiring, 7 is a contact hole, 8 is an insulating film between the eyebrows, 9
10 is a field oxide film, 10 is a channel stopper, 11 is a floating gate insulating film, 12 is a control gate insulating film, and 13 is a glabellar insulating film between the floating gate and the control gate. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
の主表面上に第１の絶縁膜を介して形成された浮遊ゲー
ト電極としての第１の導電層と、該第１の導電層の側壁
部および上部に第２の絶縁膜を介して形成された制御ゲ
ート電極としての第２の導電層と、上記半導体基板の主
表面に形成された第２導電型を有するソースおよびドレ
インとしての第３の導電層とを有する半導体記憶装置で
あって、 上記第１の導電層の側壁部に形成された第２の導電層は
上記第１の導電層の上部に形成された第２の導電層と電
気的に接続されており、かつ上記第１の導電層に対して
自己整合的に形成されたものであることを特徴とする半
導体記憶装置。(1) A semiconductor substrate having a first conductivity type, a first conductive layer as a floating gate electrode formed on the main surface of the semiconductor substrate via a first insulating film, and the first conductive layer. a second conductive layer as a control gate electrode formed on the sidewalls and upper part of the semiconductor substrate via a second insulating film; and a second conductive layer as a source and drain having a second conductivity type formed on the main surface of the semiconductor substrate. a third conductive layer, wherein the second conductive layer formed on the side wall of the first conductive layer is a second conductive layer formed on the top of the first conductive layer; A semiconductor memory device characterized in that the semiconductor memory device is electrically connected to the first conductive layer and formed in a self-aligned manner with respect to the first conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63174488A JPH07101714B2 (en) | 1988-07-12 | 1988-07-12 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63174488A JPH07101714B2 (en) | 1988-07-12 | 1988-07-12 | Semiconductor memory device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0223672A true JPH0223672A (en) | 1990-01-25 |
| JPH07101714B2 JPH07101714B2 (en) | 1995-11-01 |
Family
ID=15979360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63174488A Expired - Lifetime JPH07101714B2 (en) | 1988-07-12 | 1988-07-12 | Semiconductor memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07101714B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03112166A (en) * | 1989-09-20 | 1991-05-13 | Samsung Electron Co Ltd | Non-volatile semiconductor memory and manufacture theheof |
| JPH04252072A (en) * | 1991-01-28 | 1992-09-08 | Toshiba Corp | Semiconductor device |
| JPH0897309A (en) * | 1994-09-29 | 1996-04-12 | Nec Corp | Non-volatile semiconductor memory and its manufacture |
| US6075267A (en) * | 1996-02-28 | 2000-06-13 | Ricoh Company, Ltd. | Split-gate non-volatile semiconductor memory device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS647569A (en) * | 1987-06-29 | 1989-01-11 | Nec Corp | Manufacture of semiconductor nonvolatile memory |
-
1988
- 1988-07-12 JP JP63174488A patent/JPH07101714B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS647569A (en) * | 1987-06-29 | 1989-01-11 | Nec Corp | Manufacture of semiconductor nonvolatile memory |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03112166A (en) * | 1989-09-20 | 1991-05-13 | Samsung Electron Co Ltd | Non-volatile semiconductor memory and manufacture theheof |
| JPH04252072A (en) * | 1991-01-28 | 1992-09-08 | Toshiba Corp | Semiconductor device |
| JPH0897309A (en) * | 1994-09-29 | 1996-04-12 | Nec Corp | Non-volatile semiconductor memory and its manufacture |
| US5891775A (en) * | 1994-09-29 | 1999-04-06 | Nec Corporation | Method of making nonvolatile semiconductor device having sidewall split gate for compensating for over-erasing operation |
| US6075267A (en) * | 1996-02-28 | 2000-06-13 | Ricoh Company, Ltd. | Split-gate non-volatile semiconductor memory device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07101714B2 (en) | 1995-11-01 |
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