JPS61163714A - Frequency multiplying circuit using delay line - Google Patents
Frequency multiplying circuit using delay lineInfo
- Publication number
- JPS61163714A JPS61163714A JP437485A JP437485A JPS61163714A JP S61163714 A JPS61163714 A JP S61163714A JP 437485 A JP437485 A JP 437485A JP 437485 A JP437485 A JP 437485A JP S61163714 A JPS61163714 A JP S61163714A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- delay line
- input signal
- signal line
- clock
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、周波数逓倍回路に関し、特に遅延線を用いた
周波数逓倍回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frequency multiplier circuit, and particularly to a frequency multiplier circuit using a delay line.
従来、この種の技術はＰＬＬを用いる回路方式％式％
〔解決すべき問題点〕
←述１．た従専の周波数逓倍回路〒行−複雑秀何路とな
り、多数の素子を必要とし、かつ、わかりに〈〈デユー
ティ（ｄｕｔｙ）比を変えたパルス列は得られないとい
う欠点がある。Conventionally, this type of technology has been based on a circuit system using a PLL.[Problems to be solved] ←Described in 1. However, a dedicated frequency multiplier circuit requires a complicated circuit, requires a large number of elements, and has the disadvantage that it is not possible to obtain a pulse train with a clearly changed duty ratio.
〔問題点の解決手段）
本発明は、入力された源クロックのパルス幅を細分化し
、それを再度組合せることにより、源クロックよりも高
い周波数でかつデユーティ（ｄｕｔｙ）比を変え九パル
ス列を得られるようにすることによシ、上記従来の問題
点を解決せんとするもので、そのために本発明は、入力
信号線に遅延線を接続し、該遅延線の出力信号線に入力
信号前縁微分回路をなすインバータ及びＡＮＤ回路を接
続すると共に、これらＡＮＤ回路を６Ｒ回路に集中結線
してなる遅延線を用いた周波数逓倍回路を提供するもの
である。[Means for solving the problem] The present invention subdivides the pulse width of the input source clock and combines them again to obtain a nine-pulse train at a higher frequency than the source clock and with a different duty ratio. It is an object of the present invention to solve the above-mentioned conventional problems by connecting a delay line to an input signal line, and to connect a leading edge of an input signal to an output signal line of the delay line. This invention provides a frequency multiplication circuit using a delay line in which an inverter and an AND circuit forming a differentiating circuit are connected, and these AND circuits are collectively connected to a 6R circuit.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１ｒｇＪは、本発明の一実施例の回路図である。遅延
線１と、その入力信号線１２と、遅延線１の出力信号線
１３〜２２と、インバータ２〜６と、ＡＮＤ回路７〜１
１と、接続線２３〜３２と６Ｒ回路３３と、出力信号線
３４より構成される。即ち、入力信号線１２に遅延線１
を接続し、該遅延線１の出力信号線１４，１６，１８，
２０，２２に各々インバータ２〜６が設けられ、更にこ
のインバータ２〜６の接続線２３〜２７と他の出力信号
線１３゜１５．１７，１９．２１ とが各々ＡＮＤ回
路７〜１１に接続され、そしてこのＡＮＤ回路７〜１１
が接続線２８〜３２を介してδＲ回路３３に集中的に接
続され、更にこの６Ｒ回路３３に出力信号線３４が設け
られている。そして、上記遅延線の２つの出力信号とイ
ンバー２１個とＡＮＤ回路１個による入力信号前縁微分
回路を５組持ち、各々の組で入力信号線１２に加えられ
るクロックよりもパルス幅の短かいクロックを作り、回
路全体として５相のクロックを作成し、さらにそれをＯ
Ｒ回路３３で１本の出力信号線３４にまとめることで５
逓倍のクロックを作成するようにしている。第２図は、
第１図の回路のタイミングチャートであり、遅延線ｌの
出力信号線１３〜２２の遅れが等間隔である場合の入力
信号線１２と、遅延線１の出力信号線１３〜２２と、Ａ
ＮＤ回路２８〜３２経過後の波形を示し、最後的には出
力信号＃！３４の波形が得られるようになっている。従
って、少ない素子数で周波数を逓倍できることとなる。The first rgJ is a circuit diagram of an embodiment of the present invention. Delay line 1, its input signal line 12, output signal lines 13-22 of delay line 1, inverters 2-6, AND circuits 7-1
1, connection lines 23 to 32, a 6R circuit 33, and an output signal line 34. That is, delay line 1 is connected to input signal line 12.
and the output signal lines 14, 16, 18,
20 and 22 are provided with inverters 2 to 6, respectively, and connection lines 23 to 27 of the inverters 2 to 6 and other output signal lines 13°15.17 and 19.21 are connected to AND circuits 7 to 11, respectively. and this AND circuits 7 to 11
are centrally connected to the δR circuit 33 via connection lines 28 to 32, and the 6R circuit 33 is further provided with an output signal line 34. It has five sets of input signal leading edge differentiating circuits made up of the two output signals of the delay line, 21 inverters, and one AND circuit, and each set has a pulse width shorter than the clock applied to the input signal line 12. Create a clock, create a 5-phase clock for the entire circuit, and then
By combining the R circuit 33 into one output signal line 34, 5
I am trying to create a multiplication clock. Figure 2 shows
1 is a timing chart of the circuit of FIG. 1, in which the delays of the output signal lines 13 to 22 of the delay line l are at equal intervals; the input signal line 12; the output signal lines 13 to 22 of the delay line 1;
The waveform after passing through the ND circuits 28 to 32 is shown, and finally the output signal #! 34 waveforms can be obtained. Therefore, the frequency can be multiplied with a small number of elements.
以上説明したように、本発明は、入力信号線に遅延線を
接続し、該遅延線の出力信号線に入力信号前縁微分回路
をなすインバータ及びＡＮＤ回路を接続すると共に、こ
れらＡＮＤ回路をＯＲ回路に集中結線してなる遅延線を
用いた構成としたため、少ない素子数で周波数を逓倍で
きるという効果がある。As explained above, the present invention connects a delay line to an input signal line, connects an inverter and an AND circuit forming an input signal leading edge differentiating circuit to an output signal line of the delay line, and ORs these AND circuits. Since the configuration uses a delay line that is connected in a concentrated manner to the circuit, it has the effect of being able to multiply the frequency with a small number of elements.
第１図は、本発明の一実施例を示す周波数逓倍回路図、
そして、第２図は、第１図に示す回路のタイミングチャ
ート図である。FIG. 1 is a frequency multiplication circuit diagram showing one embodiment of the present invention, and FIG. 2 is a timing chart diagram of the circuit shown in FIG. 1.
Claims (1)
入力信号前縁微分回路をなすインバータ及びＡＮＤ回路
を接続すると共に、これらＡＮＤ回路を＠Ｏ＠Ｒ回路に
集中結線してなる遅延線を用いた周波数逓倍回路。A delay line is connected to the input signal line, an inverter and an AND circuit forming the input signal leading edge differentiating circuit are connected to the output signal line of the delay line, and these AND circuits are centrally connected to the @O@R circuit. Frequency multiplier circuit using delay line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP437485A JPS61163714A (en) | 1985-01-14 | 1985-01-14 | Frequency multiplying circuit using delay line |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP437485A JPS61163714A (en) | 1985-01-14 | 1985-01-14 | Frequency multiplying circuit using delay line |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61163714A true JPS61163714A (en) | 1986-07-24 |
Family
ID=11582585
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP437485A Pending JPS61163714A (en) | 1985-01-14 | 1985-01-14 | Frequency multiplying circuit using delay line |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61163714A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07507436A (en) * | 1993-04-30 | 1995-08-10 | エスジーエス―トムソン、マイクロエレクトロニクス、リミテッド | frequency multiplier |
| JP2009120046A (en) * | 2007-11-15 | 2009-06-04 | Caterpillar Japan Ltd | Floor structure of vehicle |
| US9126643B2 (en) | 2012-02-23 | 2015-09-08 | Komatsu Ltd. | Cab for work vehicle and work vehicle |
| US9139979B2 (en) | 2012-02-23 | 2015-09-22 | Komatsu Ltd. | Work vehicle |
-
1985
- 1985-01-14 JP JP437485A patent/JPS61163714A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07507436A (en) * | 1993-04-30 | 1995-08-10 | エスジーエス―トムソン、マイクロエレクトロニクス、リミテッド | frequency multiplier |
| JP2009120046A (en) * | 2007-11-15 | 2009-06-04 | Caterpillar Japan Ltd | Floor structure of vehicle |
| US9126643B2 (en) | 2012-02-23 | 2015-09-08 | Komatsu Ltd. | Cab for work vehicle and work vehicle |
| US9139979B2 (en) | 2012-02-23 | 2015-09-22 | Komatsu Ltd. | Work vehicle |
| US9643662B2 (en) | 2012-02-23 | 2017-05-09 | Komatsu Ltd. | Cab for work vehicle and work vehicle |
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