JPS62131624A - Frequency multiplier circuit - Google Patents

Abstract

PURPOSE:To uniform the duty of an output pulse by connecting delay circuits having an inverting function in cascade connection of plural odd stages. CONSTITUTION:A delay circuit 11 consists of a buffer 8 controlling the charge/ discharge of an integration device 9 and a buffer 10 waveform-shaping the output of the integration device 9 and inverting the waveform. A delay circuit 15 consists of the same constitution as the circuit 11. An output signal 2B delayed by a time t1 from the leading of the input signal 2A and by a time t2 from the trailing is obtained from the delay circuit 11. The signal 2B passed through a delay circuit 15 and retarded by the time t2 from the trailing and by he time t1 from the leading and becomes an output signal 2C. The signal 2C is inputted to a multiplier 16 as a signal delayed by a time (t1+t2) both from the leading and the trailing of the input signal 2A and multiplied with the input signal 2A. Thus, even when the delay time of the delay circuits has variance, a pulse signal having a uniform duty is obtained.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は任意の周波数のパルス信号の周波数逓倍回路の
改良に係わシ、特に入力されたパルス信号の立上シから
と立下シからの遅延時間を同等にして、逓倍されたパル
ス信号のデユーティ−を均一にしようとするものである
。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to the improvement of a frequency multiplier circuit for a pulse signal of an arbitrary frequency, and particularly to the improvement of a frequency multiplier circuit for a pulse signal of an arbitrary frequency. The purpose is to equalize the delay times of the pulse signals and to equalize the duty of the multiplied pulse signals.

〔従来の技術〕[Conventional technology]

従来、マイクロコンピュータ等の制御装置のシステムク
ロック等を発生させるような場合において、発振周波数
の２倍の周波数を得る際、従来回路としては第３図に示
す回路があシ、バッファ１と積分器２とバッファ３で構
成される遅延回路２と乗算器５とからなっていた。Conventionally, when generating a system clock etc. for a control device such as a microcomputer, when obtaining a frequency twice the oscillation frequency, the circuit shown in Figure 3 has been used as a conventional circuit, using a buffer 1 and an integrator. The delay circuit 2 includes a delay circuit 2 and a buffer 3, and a multiplier 5.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

第４図は従来回路の動作を表わすタイミング図である。 FIG. 4 is a timing diagram showing the operation of the conventional circuit.

第３図による回路の動作を説明すると入力端子６に印加
された入力信号１人は充電をするバッファ１と積分器２
と波形成形をするバッファ３とで構成された遅延回路４
を通過して２つの入力を持つ乗算器５の一方に入力され
、他方は入力信号１人が直接乗算器５に入力される。こ
こで入力信号１人が遅延回路４を通過する時充放電時間
が同一になるように設計しても製造上のバラツキあるい
は温度の変化によって積分器２を充放電するバッファｌ
の充放電時間のバラツキや波形成形バッファ３のスレッ
シ、ルドのバラツキによって遅延回路４の出力信号ＩＢ
は入力信号ＩＡの立上りからの遅延時間ｔ１と立下シか
らの遅延時間ｔ２が異ってしまい乗算器５の出力信号Ｉ
Ｃのデ−ティが均一にならない。これは出力信号ＩＣが
周波数変調を受けてｂるため信号の立下シを分周した場
合５０チのデー−ティ出力が得られ々いといった欠点が
ある。本発明はかかる事情にかんがみてなされたもので
ある。To explain the operation of the circuit shown in FIG.
and a buffer 3 that shapes the waveform.
The input signal is passed through and input into one of the multipliers 5 having two inputs, and one input signal is directly input into the multiplier 5 on the other side. Here, even if the design is such that the charging and discharging times are the same when one input signal passes through the delay circuit 4, the buffer l that charges and discharges the integrator 2 due to manufacturing variations or temperature changes.
The output signal IB of the delay circuit 4 may be
Since the delay time t1 from the rising edge of the input signal IA and the delay time t2 from the falling edge of the input signal IA are different, the output signal I of the multiplier 5
C data is not uniform. This has the disadvantage that since the output signal IC is subjected to frequency modulation, it is difficult to obtain a data output of 50 when the falling edge of the signal is divided. The present invention has been made in view of such circumstances.

〔問題点を解決するための手段〕[Means for solving problems]

次に、本発明についてその一実施例である第１図によっ
て説明すると、遅延回路１１は積分器９の充放電を制御
するバッファ８と積分器９の出力を波形成形し反転させ
るバッファ１０で構成されている。遅延回路１５は遅延
回路１１と全く同等に構成される遅延回路。乗算器１６
は入力信号と入力信号が遅延回路１１．１５を通過した
信号を乗算する。Next, the present invention will be explained with reference to FIG. 1, which is an embodiment of the present invention. The delay circuit 11 is composed of a buffer 8 that controls charging and discharging of an integrator 9, and a buffer 10 that shapes and inverts the waveform of the output of the integrator 9. has been done. The delay circuit 15 is a delay circuit configured exactly the same as the delay circuit 11. Multiplier 16
multiplies the input signal by the signal obtained by passing the input signal through the delay circuit 11.15.

この様に構成された周波数逓倍回路を第１図及び第２図
を用いて説明する。まず、入力信号２人が立上ると、遅
延回路１１はパルスの立上りから時間ｔ１だけ、また、
パルスの立下りから時間ｔ２だけ入力信号２人が遅延さ
れた出力信号２Ｂを得る。A frequency multiplier circuit configured in this manner will be explained using FIGS. 1 and 2. First, when two input signals rise, the delay circuit 11 waits for a time t1 from the rise of the pulse, and
An output signal 2B is obtained by delaying the two input signals by a time t2 from the falling edge of the pulse.

次に出力信号２Ｂは遅延回路１１と全く同等に構成され
た遅延回路１５を通過するので信号２Ｂの立下シから時
間ｔ２だけ、また立上りから時間ｔ１だけ出力信号２Ｂ
を遅延された出力信号２Ｃを得る。このことは入力信号
２人が遅延回路１１及び１５を通過して得られる信号２
Ｃは入力信号２人の立上シからも立下シからも時間ｔｌ
　＋１２遅れた信号が乗算器１６に入力され、入力信号
２人と乗算されることになる。Next, the output signal 2B passes through the delay circuit 15, which is configured exactly the same as the delay circuit 11, so that the output signal 2B passes through the delay circuit 15, which is configured in exactly the same way as the delay circuit 11.
A delayed output signal 2C is obtained. This means that the signal 2 obtained when the two input signals pass through the delay circuits 11 and 15
C is the time tl from the rising edge and falling edge of the two input signals.
The +12 delayed signal is input to the multiplier 16 and will be multiplied by the two input signals.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば本周波数逓倍回路の
出力は、製造上あるいは温度変化によって１ケの遅延回
路の遅延時間にバラツキがあっても常に乗算器に入力さ
れる遅延時間はｔｌ　＋ｔ２になるため、均一なデユー
ティを持つパルス信号を提供することができる。As explained above, according to the present invention, the output of the frequency multiplier circuit is always input to the multiplier with a delay time of tl + t2 even if the delay time of one delay circuit varies due to manufacturing or temperature changes. Therefore, a pulse signal with uniform duty can be provided.

尚、第１図において遅延回路を２ケ縦続接続したが２ケ
以上かつ偶数個縦続接続しても同様の効果が得られるこ
とは明白である。Although two delay circuits are connected in cascade in FIG. 1, it is clear that the same effect can be obtained even if two or more delay circuits are connected in cascade.

以上説明した如く、本発明によればバラツキに対して改
良されているため集積回路化しやすく、また回路動作上
周波数逓倍回路の出力信号が周波数変調を受けていない
ため出力信号の立上シあるいは立下シのエッヂで分周し
ても５０チデユーテイの分周出力が得られる等の効果が
ある。As explained above, according to the present invention, it is easy to integrate the circuit because it is improved against variations, and since the output signal of the frequency multiplier circuit is not subjected to frequency modulation in terms of circuit operation, the rise or rise of the output signal is Even if the frequency is divided at the lower edge, a divided output of 50 times duty can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を示す周波数逓倍回路のブロ
ック図、第２図は第１図の動作を表わすタイミング図、
第３図は従来の周波数逓倍回路のブロック図、第４図は
第３図の動作を表わすタイミング図である。 ６．１７・・・・・・入力端子、７．１８・・・・・・
出力端子、１．３，８，１２・・・・・・バッファ、１
０，１４・・・・・・反転バッファ、２，９．１３・・
・・・・積分器、５．１６・・・・・・乗算器、４，１
１．１５・・・・・・遅延回路、ＩＡ。 １Ｂ、ＩＣ，２Ａ、２Ｂ、２Ｃ，２Ｄ・・・・・・各点
の動作波形。FIG. 1 is a block diagram of a frequency multiplier circuit showing an embodiment of the present invention, FIG. 2 is a timing diagram showing the operation of FIG. 1,
FIG. 3 is a block diagram of a conventional frequency multiplier circuit, and FIG. 4 is a timing diagram showing the operation of FIG. 3. 6.17... Input terminal, 7.18...
Output terminal, 1.3, 8, 12...Buffer, 1
0,14...Inverted buffer, 2,9.13...
...Integrator, 5.16... Multiplier, 4,1
1.15...Delay circuit, IA. 1B, IC, 2A, 2B, 2C, 2D...Operating waveforms at each point.

Claims (1)

【特許請求の範囲】[Claims] 任意の周波数のパルス信号が印加される遅延回路と該遅
延回路の出力及び前記パルス信号を入力する２入力の乗
算器によって構成させる周波数逓倍回路において、前記
遅延回路に反転機能を持たせ偶数段縦続接続することに
よって前記周波数逓倍回路の出力であるパルスのデュー
ティを均一にすることを特徴とする周波数逓倍回路。In a frequency multiplier circuit constituted by a delay circuit to which a pulse signal of an arbitrary frequency is applied, and a two-input multiplier to which the output of the delay circuit and the pulse signal are input, the delay circuit has an inversion function and an even number of stages are connected in cascade. A frequency multiplier circuit, characterized in that the duty of pulses output from the frequency multiplier circuit is made uniform by connecting the frequency multiplier circuit.