JPS6115831U - Channel display circuit device - Google Patents

Channel display circuit device

Info

Publication number
JPS6115831U
JPS6115831U JP1984100794U JP10079484U JPS6115831U JP S6115831 U JPS6115831 U JP S6115831U JP 1984100794 U JP1984100794 U JP 1984100794U JP 10079484 U JP10079484 U JP 10079484U JP S6115831 U JPS6115831 U JP S6115831U
Authority
JP
Japan
Prior art keywords
drive
muting signal
circuit
muting
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1984100794U
Other languages
Japanese (ja)
Other versions
JPH0230925Y2 (en
Inventor
卓男 池上
Original Assignee
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by シャープ株式会社 filed Critical シャープ株式会社
Priority to JP1984100794U priority Critical patent/JPS6115831U/en
Publication of JPS6115831U publication Critical patent/JPS6115831U/en
Application granted granted Critical
Publication of JPH0230925Y2 publication Critical patent/JPH0230925Y2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

図面は、本考案の一実施例の回路図である。 1・・・ミューテイング信号発生回路、2′・・・LE
D、3・・・駆動回路、5・・・切検回路。 {
The drawing is a circuit diagram of an embodiment of the present invention. 1... Muting signal generation circuit, 2'... LE
D, 3... Drive circuit, 5... Cut-off circuit. {

Claims (1)

【実用新案登録請求の範囲】 選局動作に応答して選局ノイズをミューテイングするミ
ューテイング信号を形成して形成して出力するミューテ
イング信号発生回路と、 印加された駆動電圧のレベルに応じた明かるさで選局チ
ャンネルを表示する表示素子と、− 前記表示素子に駆
動電圧を与えて該表示素子を表示駆動する駆動回路と、 駆動電圧供給源と前記駆動回路との間に接続されて、前
記ミューテイング信号発生回路からのミューテイング信
号の有無にそれぞれ対応じたレベルの前記駆動電圧を形
成して前記駆動回路に供給する切換回路とを含むことを
特徴とするチャンネル表示回路装置。
[Claims for Utility Model Registration] A muting signal generation circuit that forms and outputs a muting signal for muting tuning noise in response to a tuning operation, and a muting signal generation circuit that generates and outputs a muting signal that mutes tuning noise in response to a tuning operation, and a display element that displays a selected channel with brightness; - a drive circuit that applies a drive voltage to the display element to drive the display element; and a drive circuit that is connected between a drive voltage supply source and the drive circuit. and a switching circuit that forms the drive voltage at a level corresponding to the presence or absence of a muting signal from the muting signal generation circuit and supplies it to the drive circuit.
JP1984100794U 1984-07-03 1984-07-03 Channel display circuit device Granted JPS6115831U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984100794U JPS6115831U (en) 1984-07-03 1984-07-03 Channel display circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984100794U JPS6115831U (en) 1984-07-03 1984-07-03 Channel display circuit device

Publications (2)

Publication Number Publication Date
JPS6115831U true JPS6115831U (en) 1986-01-29
JPH0230925Y2 JPH0230925Y2 (en) 1990-08-21

Family

ID=30660237

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984100794U Granted JPS6115831U (en) 1984-07-03 1984-07-03 Channel display circuit device

Country Status (1)

Country Link
JP (1) JPS6115831U (en)

Also Published As

Publication number Publication date
JPH0230925Y2 (en) 1990-08-21

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