JPS60116501U - Control signal switching circuit - Google Patents
Control signal switching circuitInfo
- Publication number
- JPS60116501U JPS60116501U JP95984U JP95984U JPS60116501U JP S60116501 U JPS60116501 U JP S60116501U JP 95984 U JP95984 U JP 95984U JP 95984 U JP95984 U JP 95984U JP S60116501 U JPS60116501 U JP S60116501U
- Authority
- JP
- Japan
- Prior art keywords
- control signal
- output
- circuit
- switching circuit
- signal switching
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Feedback Control In General (AREA)
- Logic Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の制御信号切換回路の回路図、第２図は本
考案の一実施例の構成を示す回路図、第 −３図は本考
案の一実施例の作用の説明に供する波形図である。
Ａ、 Ｃ，ＥおよびＦ・・・・・・制御信号入力端子、
Ｇ・・・・・・出力端子、ＨおよびＪ・・・・・・ノア
ゲート、６・・・・・・アンドゲート、７・・・・・・
レベルホールド回路、８および９・・・・・・インバー
タ、１０・・・・・・抵抗、１１・・・・・・反転増幅
器、Ｔｒ１〜Ｔｒ３・・・・・・トランジスタ、Ｄ１〜
Ｄ３・・・・・・ダイオード。Fig. 1 is a circuit diagram of a conventional control signal switching circuit, Fig. 2 is a circuit diagram showing the configuration of an embodiment of the present invention, and Fig. 3 is a waveform diagram for explaining the operation of an embodiment of the present invention. It is. A, C, E and F...control signal input terminals,
G...Output terminal, H and J...Nor gate, 6...And gate, 7...
Level hold circuit, 8 and 9...Inverter, 10...Resistor, 11...Inverting amplifier, Tr1-Tr3...Transistor, D1-
D3...Diode.
Claims (1)
換回路において、第１の制御信号が供給゛ されたこと
を検知する第１の検知手段と、第１の検知手段からの検
知信号発生から少なくとも第１の制御信号の供給終了ま
で所定の信号を発生するホールド回路と、第１の検知手
段の出力とホールド回路の出力との論理積演算をする第
１の演算回路と、第２の制御信号とホールド回路の出力
とのノア演算する第２の演算回路と、第１の演算回路の
出力と第２の演算回路の出力とのノア演算する第３の演
算回路と、第２の演算回路の出力を反転出力する反転手
段とを備えてなることを特徴とする制御信号切換回路。In a control signal switching circuit that switches between two control signals consisting of a pulse train, a first detection means detects that the first control signal is supplied, and at least a first detection means detects that the first control signal is supplied. a hold circuit that generates a predetermined signal until the supply of the control signal ends; a first arithmetic circuit that performs an AND operation between the output of the first detection means and the output of the hold circuit; a second arithmetic circuit that performs a NOR operation on the output of the circuit; a third arithmetic circuit that performs a NOR operation on the output of the first arithmetic circuit and the output of the second arithmetic circuit; A control signal switching circuit comprising: inverting means for inverting output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP95984U JPS60116501U (en) | 1984-01-10 | 1984-01-10 | Control signal switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP95984U JPS60116501U (en) | 1984-01-10 | 1984-01-10 | Control signal switching circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60116501U true JPS60116501U (en) | 1985-08-07 |
Family
ID=30473267
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP95984U Pending JPS60116501U (en) | 1984-01-10 | 1984-01-10 | Control signal switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60116501U (en) |
-
1984
- 1984-01-10 JP JP95984U patent/JPS60116501U/en active Pending
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