JPS6115741U - 半導体集積回路 - Google Patents

半導体集積回路

Info

Publication number
JPS6115741U
JPS6115741U JP9377985U JP9377985U JPS6115741U JP S6115741 U JPS6115741 U JP S6115741U JP 9377985 U JP9377985 U JP 9377985U JP 9377985 U JP9377985 U JP 9377985U JP S6115741 U JPS6115741 U JP S6115741U
Authority
JP
Japan
Prior art keywords
diffusion layer
integrated circuit
semiconductor integrated
bonding pad
aluminum
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9377985U
Other languages
English (en)
Inventor
幸一 小口
Original Assignee
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコーエプソン株式会社 filed Critical セイコーエプソン株式会社
Priority to JP9377985U priority Critical patent/JPS6115741U/ja
Publication of JPS6115741U publication Critical patent/JPS6115741U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【図面の簡単な説明】
第１図は、従来の半導体集積回路のボンデイングパッド
構造を説明する概観図。 第２図は、半導体集積回路を導電性接着剤を用いてフエ
イスダウ− ンボンデイングあるいはフエ不スアップボ
ンデイングする場合の説明図。 第３図は、本考案による改良されたボンデイングパツド
構造の概観図。 １・・・シリコン基板、２・・・シリコン基板とは送符
号の導電型の拡散層、３・・・熱酸化膜、４・・・アル
ミニウム被膜、５・・・表面保護被膜、６・・・コンタ
クトホール、７・・・アルミニウム被膜露出部を示す線
、８・・・アルミニウムボンデイングパッド、９・・・
導電性接着材、１０・・・ボンデイング基板、１１・・
・リード線、１２・・・シリコン基板とは送符号の導電
型の拡散層、１３・・・シリコン基板とオーミック接触
する金属被膜、１４・・・表面が酸化されにくい金属被
膜、１５・・・内部配線の終端部、１６・・・巳ンタク
トホール。

Claims (1)

    【実用新案登録請求の範囲】
  1. 一部に拡散層を有する半導体基板、前記半導体基板上に
    形成された前記拡散層の一部と重なる位置に開孔部を有
    する酸化被膜及び、前記酸化被膜上の前記開孔部と重な
    る位置に形成され、前記開孔部を介して前記拡散層と接
    続するボンデイングバツド部を具備し、前記ボンデイン
    グパツド部は、アルミニウム以外の耐腐食性の多層金属
    にて形成され、前記ボンデイングパッド部と、アルミニ
    ウムよりなる内部配線の終端部とは、前記拡散層を介し
    て接続されたことを特徴とする．半導体集積回路。
JP9377985U 1985-06-20 1985-06-20 半導体集積回路 Pending JPS6115741U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9377985U JPS6115741U (ja) 1985-06-20 1985-06-20 半導体集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9377985U JPS6115741U (ja) 1985-06-20 1985-06-20 半導体集積回路

Publications (1)

Publication Number Publication Date
JPS6115741U true JPS6115741U (ja) 1986-01-29

Family

ID=30651762

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9377985U Pending JPS6115741U (ja) 1985-06-20 1985-06-20 半導体集積回路

Country Status (1)

Country Link
JP (1) JPS6115741U (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02135772A (ja) * 1988-11-16 1990-05-24 Mitsubishi Electric Corp 半導体装置

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4927361B1 (ja) * 1969-04-08 1974-07-17
JPS5028979A (ja) * 1973-07-16 1975-03-24
JPS5055261A (ja) * 1973-09-12 1975-05-15

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4927361B1 (ja) * 1969-04-08 1974-07-17
JPS5028979A (ja) * 1973-07-16 1975-03-24
JPS5055261A (ja) * 1973-09-12 1975-05-15

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02135772A (ja) * 1988-11-16 1990-05-24 Mitsubishi Electric Corp 半導体装置

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