JPS61150236A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61150236A JPS61150236A JP27088584A JP27088584A JPS61150236A JP S61150236 A JPS61150236 A JP S61150236A JP 27088584 A JP27088584 A JP 27088584A JP 27088584 A JP27088584 A JP 27088584A JP S61150236 A JPS61150236 A JP S61150236A
- Authority
- JP
- Japan
- Prior art keywords
- film
- melting point
- adhesion
- point metal
- high melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、半導体基板表面に絶縁膜を介して形成される
電極・配線に高融点金属膜を用いる半導体装置に関する
もので、特に、絶縁膜の変質防止と、絶縁膜と高融点金
属膜との接着性の改良とを図ったものである。Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a semiconductor device that uses a high melting point metal film for electrodes and wiring formed on the surface of a semiconductor substrate via an insulating film. This is aimed at preventing deterioration and improving the adhesion between the insulating film and the high melting point metal film.
従来、MO8素子の電極・配線には多結晶シリコンが用
いられてきた。しかし、素子の高集積化と高速化のため
には、多結晶シリコンより低抵抗の材料が必要である。Conventionally, polycrystalline silicon has been used for the electrodes and wiring of MO8 elements. However, in order to increase the integration and speed of devices, a material with lower resistance than polycrystalline silicon is required.
従って、電極・配線の材料として純金属が使えれば理想
的であるが゛、これには次のような問題がある。即ち、
製造工程中に金属が、絶縁膜であるS’−io、(二酸
化シリコン)膜からはがれてしまったり、高温熱処理中
−金属とSin、が反応して、絶縁耐圧不良等の素子特
性の劣化を引起こす心配がある、等の問題がある。Therefore, it would be ideal if pure metal could be used as the material for electrodes and wiring, but this has the following problems. That is,
During the manufacturing process, metal may peel off from the insulating S'-io (silicon dioxide) film, or during high-temperature heat treatment, metal and Sin may react, causing deterioration of device characteristics such as poor dielectric strength. There are problems such as concerns that it may cause
特に、高融点金属膜と5in2膜との接着性が不充分で
あるという問題はデバイスの信頼性に大きく影響するの
で解決が強く望まれていた。In particular, there has been a strong desire to solve the problem of insufficient adhesion between the high melting point metal film and the 5in2 film, since it greatly affects the reliability of the device.
〔発明の目的〕 □
本発明の目的は、繍縁膜特にSiO□膜上に□形成する
電極・配線として高融点金属膜を用いる半導体装置にお
いて、絶縁膜の変質を防止でき、かつ、高融点金属膜と
絶縁膜との接着性を良くすることのできる半導体装置を
提供することにある。[Object of the Invention] □ The object of the present invention is to prevent deterioration of the insulating film and to provide a high melting point metal film in a semiconductor device that uses a high melting point metal film as an electrode/wiring formed on a selvage film, particularly a SiO film. An object of the present invention is to provide a semiconductor device that can improve the adhesion between a metal film and an insulating film.
本発明の対象となる半導体素子では、製造工程中、絶縁
膜と電極・配線膜が接触した状態で、約1000℃の高
温で加熱される。電極・配線に高融点金属を使う場合、
金属の酸化物の生成自由エネルギーがSiO2のそれよ
り負で絶対値が大きい(即ち、生成自由エネルギーがS
i O2のそれより低い)ときには、金属と5in2
とは反応してしまう。一方、金属の酸化物の生成自由エ
ネルギーが5in2のそれより負で絶対値が小さい場合
には、金属とSi’02 とは反応しにくいはずである
。(生成自由エネルギーが正のときは、不安定 ・なの
で1問題外である。)ところが、約1000℃の高温で
は、5in2そのものの安定性も問題になる。即ち、金
属と5in2とが反応しにくくても、金属に含まれる酸
素が少なくなると、5in2の解離が認められる場合が
ある。従って、金属膜とS i O2膜間に酸化物層を
設けることが有効である。しかし、多くの場合、酸化物
は化学量論組成にはならないので、そのとき酸素が不足
していると、この酸化物としての生成自由エネルギーが
5iOzのそれより低いものを使うと、S i O2が
還元される場合があるので危険である。このような理由
から、本発明では、後述の実施例断面図(第1図)に示
すように、絶縁膜(S i O2膜3)と高融点金属膜
(ゲート電極1)との間に、生成自由エネルギーの絶対
値が5in2のそれより小さい酸化物に、生成自由エネ
ルギーの絶対値が5iOz のそれと同じか大きい酸化
物を1〜50%混合させた界面層2を謹ける構成とする
。In the semiconductor device to which the present invention is applied, during the manufacturing process, the insulating film and the electrode/wiring film are heated at a high temperature of about 1000° C. while in contact with each other. When using high melting point metals for electrodes and wiring,
The free energy of formation of metal oxides is negative and larger in absolute value than that of SiO2 (i.e., the free energy of formation is S
i lower than that of O2), when metal and 5in2
I end up reacting. On the other hand, if the free energy of formation of the metal oxide is more negative than that of 5in2 and its absolute value is smaller, it should be difficult for the metal to react with Si'02. (When the free energy of formation is positive, it is unstable, so it is out of the question.) However, at high temperatures of about 1000°C, the stability of 5in2 itself also becomes a problem. That is, even if the metal and 5in2 hardly react, dissociation of 5in2 may be observed when the amount of oxygen contained in the metal decreases. Therefore, it is effective to provide an oxide layer between the metal film and the SiO2 film. However, in many cases, oxides do not have a stoichiometric composition, so if oxygen is insufficient at that time, if an oxide with a free energy of formation lower than 5iOz is used, S i O2 It is dangerous because it may be returned. For this reason, in the present invention, as shown in the cross-sectional view of the embodiment (FIG. 1) described later, between the insulating film (SiO2 film 3) and the high melting point metal film (gate electrode 1), The interface layer 2 is constructed by mixing 1 to 50% of an oxide whose absolute value of free energy of formation is smaller than that of 5 in 2 with an oxide whose absolute value of free energy of formation is the same or larger than that of 5 iOz.
以下、図面により本発明の詳細な説明する。 Hereinafter, the present invention will be explained in detail with reference to the drawings.
第1図は実施例の断面図で、1は高融点金属膜のゲート
電極、2は界面層、3はSiO2膜、4はSi単鞘晶基
板を示す。タングステン(W)をゲート電極1としたM
O8半導体素子の試作を、2種類の被着法と2種類の界
面層について行なった。FIG. 1 is a cross-sectional view of the embodiment, in which 1 is a gate electrode made of a high-melting point metal film, 2 is an interface layer, 3 is a SiO2 film, and 4 is a Si monosheath crystal substrate. M with tungsten (W) as gate electrode 1
Prototyping of O8 semiconductor devices was carried out using two types of deposition methods and two types of interfacial layers.
被着には、CV D (Chemical Vapor
Deposition)法とスパン、り法を用いた。For adhesion, CV D (Chemical Vapor
We used the Deposition method and the Span method.
CV、D法ではふつ化タングステン(WF、 )を原料
ガスに用い、Si添加のためにはSiH4を混合した。In the CV and D methods, tungsten fluoride (WF, ) was used as a raw material gas, and SiH4 was mixed to add Si.
界面層の酸化物形成には、蒸着初期にCVD雰囲気中に
存在する0、2や水(H,O) を利用した。スパッ
タ法ではWとSiのターゲットを用い、初期に02を微
量導入して一時スバッタすることにより酸化物層を形成
した。上記の、2種類の被着法と、2種類の界面層との
組合せから成る4種類の試料I、TI。To form an oxide in the interfacial layer, 0,2 and water (H, O) present in the CVD atmosphere at the initial stage of vapor deposition were used. In the sputtering method, W and Si targets were used, and an oxide layer was formed by initially introducing a small amount of 02 and performing temporary sputtering. The above four types of samples I and TI consist of a combination of two types of deposition methods and two types of interfacial layers.
m、rvにつし)で、ゲート電極1と、SiO2膜3と
の接着性の1、良否、S i O2膜3の変質の有無を
調べた結果を第2図に示す。なお、界、面M(酸化物層
)2の厚さは、いずれも5nmである。 。FIG. 2 shows the results of examining the adhesion between the gate electrode 1 and the SiO2 film 3, the quality of the adhesion, and the presence or absence of deterioration of the SiO2 film 3. Note that the thickness of the boundary and the surface M (oxide layer) 2 are both 5 nm. .
第2図に見られるように、CVD法を用、いたとき、界
面層がWO3だけの場合、高一点金属膜(ゲート電極1
)とS i O,膜3との接着性が悪かったが、界面層
を、10%のS i O2を含むwo、 とした試料■
で、は、約、10007:、の加熱により良好な接着性
が、鏝ヤれん。スパッタ法によって得られた試料■、■
は、第2図に示す通り、WO3中のSin、の有無にか
かわらず接着性は良かったが、SiO□をWO3中に含
む試料■の方が、試料■より接着性が良かった。結局、
はがれが認められた試料Iを除いては、ドライエツチン
グ9.により電極を形成して、第1図に示すようなMO
,、S素子を形成することができ、た。測定したフラッ
トバンド電圧、Sin、膜3の絶縁耐圧等の特性に問題
はなかった。As shown in Fig. 2, when using the CVD method, when the interface layer is only WO3, the high point metal film (gate electrode 1
) and S i O, film 3 had poor adhesion, but the interface layer was made of wo containing 10% S i O2 Sample ■
So, when heated to about 10007, good adhesion is achieved. Samples obtained by sputtering method■,■
As shown in FIG. 2, the adhesiveness was good regardless of the presence or absence of Sin in WO3, but the adhesiveness of sample (2) containing SiO□ in WO3 was better than that of sample (2). in the end,
Dry etching 9. Except for sample I where peeling was observed. The electrodes are formed by MO as shown in FIG.
,, an S element can be formed. There were no problems with the measured characteristics such as flat band voltage, Sin, and dielectric strength voltage of the film 3.
界面層2へのSiO□添加の効果は、その量が1%以上
で認められた。しかし、50%以上にすはS i O2
を用いるとしたが、これは・Si’02でなくてもよく
、Si、O,として、−XΣ1であれば接着性向上の効
果が認められ、下層のS i O,膜3が劣化すること
はなかった。また、界面層2の厚さとしては、単分子層
以上、5 ’On’ m以下の厚さで接着性向上の効果
が認められた。さらに、界面層2のW酸化物の組成もW
Oaに限定されず、WOyのy、=4〜3の範囲で前記
効果が認められた。The effect of adding SiO□ to the interface layer 2 was observed when the amount was 1% or more. However, more than 50% S i O2
However, this does not have to be -Si'02; as Si, O, -XΣ1 will have the effect of improving adhesion, but the underlying SiO film 3 will deteriorate. There was no. Moreover, the effect of improving adhesion was observed when the thickness of the interface layer 2 was at least a monomolecular layer and at most 5'On' m. Furthermore, the composition of the W oxide in the interface layer 2 is also W
Not limited to Oa, the above effect was observed in the range of WOy=4 to 3.
以上は高融点金属としてWを用いた場合について説明し
たが、高融点金属としてMo(モリブデン)を用い、界
面層にM o O、+ S i O、を用いた場合にも
同様の効果が得られた。この場合、Sin、の代わりに
Tie、を用いても効果を生じ得るが、T i O,の
生成自由エネルギーがSiO2のそれより負で大きい値
をとることから、x>2にしないと、下層のSiO□膜
の変質が認められた。なお、C(炭素)を含む化合物を
Wo。The above explanation is about the case where W is used as the high melting point metal, but similar effects can be obtained when Mo (molybdenum) is used as the high melting point metal and M o O, + Si O, is used for the interface layer. It was done. In this case, using Tie instead of Sin may produce an effect, but since the free energy of formation of TiO takes a negative and larger value than that of SiO2, unless x>2, the lower layer Deterioration of the SiO□ film was observed. Note that the compound containing C (carbon) is Wo.
やMob、に添加しても、接着性向上の効果が認められ
た。The effect of improving adhesion was observed even when it was added to
本発明によれば、高融点金属で形成される電極・配線膜
と下層のSiC2膜との間に界面層を介在させることで
、下層の5in2膜の変質を防止しながら、電極・配線
膜とS i O,膜との接着性の良好なMO8型半導体
装置とすることができ、5in2膜が薄い、非常に多く
のMO3素子からなる、超高集積回路の歩留りの向上と
高信頼化に効果がある。また、将来、電極・配線の形成
に用いる蒸着装置が改良されて装置内雰囲気の酸化性不
純物が減少すると共に、電極・配線の金属は純粋になり
、下層のSj、O,膜が不安定になる可能性は大きくな
るので、本発明の有用性は増す。According to the present invention, by interposing an interface layer between the electrode/wiring film made of a high-melting point metal and the lower SiC2 film, the electrode/wiring film can be formed while preventing deterioration of the lower 5in2 film. It can be made into an MO8 type semiconductor device with good adhesion to SiO, film, and is effective in improving the yield and reliability of ultra-high integrated circuits, which are made up of a large number of MO3 elements with a thin 5in2 film. There is. In addition, in the future, the vapor deposition equipment used to form electrodes and wiring will be improved and oxidizing impurities in the atmosphere inside the equipment will be reduced, and the metal of the electrodes and wiring will become pure, making the underlying Sj, O, and films unstable. This increases the possibility that this will occur, and therefore the usefulness of the present invention increases.
第1図は本発明の詳細な説明用の断面図、第2図は実施
例の4種類の試料I〜■の仕様の特性比較を示す図であ
る。
1・・・ゲート電極(高融点金属膜)、2・・・界面層
、3・・・S i O,膜、4・・・Si単結晶基板。FIG. 1 is a sectional view for explaining the present invention in detail, and FIG. 2 is a diagram showing a comparison of characteristics of specifications of four types of samples I to (2) of the example. DESCRIPTION OF SYMBOLS 1... Gate electrode (high melting point metal film), 2... Interface layer, 3... SiO, film, 4... Si single crystal substrate.
Claims (1)
上に形成された高融点金属膜からなる電極・配線とを有
する半導体装置において、前記絶縁膜と前記電極・配線
との間に、生成自由エネルギーの絶対値が二酸化シリコ
ンのそれより小さい酸化物に生成自由エネルギーの絶対
値が二酸化シリコンのそれと同じか大きい酸化物を1〜
50%混合させた厚さ単分子層以上50nm以下の層が
介在されていることを特徴とする半導体装置。 2、前記絶縁膜が二酸化シリコン膜であることを特徴と
する特許請求の範囲第1項記載の半導体装置。[Claims] 1. In a semiconductor device having an insulating film formed on the surface of a semiconductor substrate, and an electrode/wiring made of a high melting point metal film formed on the insulating film, the insulating film and the electrode/wiring are formed on the insulating film. An oxide whose absolute value of free energy of formation is smaller than that of silicon dioxide and an oxide whose absolute value of free energy of formation is the same or larger than that of silicon dioxide are used between the wiring and the wiring.
A semiconductor device comprising a 50% mixed layer having a thickness of at least a monomolecular layer and at most 50 nm. 2. The semiconductor device according to claim 1, wherein the insulating film is a silicon dioxide film.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59270885A JPH0671076B2 (en) | 1984-12-24 | 1984-12-24 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP59270885A JPH0671076B2 (en) | 1984-12-24 | 1984-12-24 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS61150236A true JPS61150236A (en) | 1986-07-08 |
JPH0671076B2 JPH0671076B2 (en) | 1994-09-07 |
Family
ID=17492317
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP59270885A Expired - Lifetime JPH0671076B2 (en) | 1984-12-24 | 1984-12-24 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0671076B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6323115B1 (en) | 1998-05-20 | 2001-11-27 | Hitachi, Ltd. | Method of forming semiconductor integrated circuit device with dual gate CMOS structure |
US7049187B2 (en) | 2001-03-12 | 2006-05-23 | Renesas Technology Corp. | Manufacturing method of polymetal gate electrode |
US7053459B2 (en) | 2001-03-12 | 2006-05-30 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for producing the same |
US7221056B2 (en) | 2003-09-24 | 2007-05-22 | Renesas Technology Corp. | Semiconductor integrated circuit device and manufacturing method thereof |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57159042A (en) * | 1981-03-26 | 1982-10-01 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
-
1984
- 1984-12-24 JP JP59270885A patent/JPH0671076B2/en not_active Expired - Lifetime
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57159042A (en) * | 1981-03-26 | 1982-10-01 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and manufacture thereof |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6323115B1 (en) | 1998-05-20 | 2001-11-27 | Hitachi, Ltd. | Method of forming semiconductor integrated circuit device with dual gate CMOS structure |
US7049187B2 (en) | 2001-03-12 | 2006-05-23 | Renesas Technology Corp. | Manufacturing method of polymetal gate electrode |
US7053459B2 (en) | 2001-03-12 | 2006-05-30 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for producing the same |
US7144766B2 (en) | 2001-03-12 | 2006-12-05 | Renesas Technology Corp. | Method of manufacturing semiconductor integrated circuit device having polymetal gate electrode |
US7300833B2 (en) | 2001-03-12 | 2007-11-27 | Renesas Technology Corp. | Process for producing semiconductor integrated circuit device |
US7375013B2 (en) | 2001-03-12 | 2008-05-20 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for manufacturing the same |
US7632744B2 (en) | 2001-03-12 | 2009-12-15 | Renesas Technology Corp. | Semiconductor integrated circuit device and process for manufacturing the same |
US7221056B2 (en) | 2003-09-24 | 2007-05-22 | Renesas Technology Corp. | Semiconductor integrated circuit device and manufacturing method thereof |
Also Published As
Publication number | Publication date |
---|---|
JPH0671076B2 (en) | 1994-09-07 |
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