JPS61136236A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61136236A JPS61136236A JP25752784A JP25752784A JPS61136236A JP S61136236 A JPS61136236 A JP S61136236A JP 25752784 A JP25752784 A JP 25752784A JP 25752784 A JP25752784 A JP 25752784A JP S61136236 A JPS61136236 A JP S61136236A
- Authority
- JP
- Japan
- Prior art keywords
- plasma
- film
- evaporation
- source
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 238000000034 method Methods 0.000 claims abstract description 26
- 238000012545 processing Methods 0.000 claims abstract description 6
- 238000000151 deposition Methods 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 abstract description 21
- 238000007254 oxidation reaction Methods 0.000 abstract description 21
- 238000001704 evaporation Methods 0.000 abstract description 9
- 230000008020 evaporation Effects 0.000 abstract description 8
- 239000012535 impurity Substances 0.000 abstract description 6
- 238000010894 electron beam technology Methods 0.000 abstract description 4
- 238000010438 heat treatment Methods 0.000 abstract description 4
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 41
- 239000000758 substrate Substances 0.000 description 16
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000001257 hydrogen Substances 0.000 description 4
- 229910052739 hydrogen Inorganic materials 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000005121 nitriding Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- 230000003749 cleanliness Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000033001 locomotion Effects 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 238000009834 vaporization Methods 0.000 description 2
- 230000008016 vaporization Effects 0.000 description 2
- 238000010521 absorption reaction Methods 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- JTJMJGYZQZDUJJ-UHFFFAOYSA-N phencyclidine Chemical class C1CCCCN1C1(C=2C=CC=CC=2)CCCCC1 JTJMJGYZQZDUJJ-UHFFFAOYSA-N 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000010902 straw Substances 0.000 description 1
- 235000012976 tarts Nutrition 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野］
本発明は、半導体装置に用いる絶縁膜を低温で形成する
方法を提供するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention provides a method for forming an insulating film used in a semiconductor device at a low temperature.
従来、半導体製造プロセスにおいて、ＭＯＳＦＥＴのゲ
ート酸化膜などの能動領域に用いられる絶縁膜はＳｉ基
板の直接熱酸化法で形成し、層間絶縁パッシベーション
用など受動領域に使用される絶縁膜はＣＶＤ法等で形成
されることが多い。Conventionally, in semiconductor manufacturing processes, insulating films used in active regions such as gate oxide films of MOSFETs are formed by direct thermal oxidation of Si substrates, and insulating films used in passive regions, such as for interlayer insulation passivation, are formed by CVD, etc. is often formed.
ところが、上記の熱酸化プロセスは１００ＯＣ’程度の
高温となる次め、素子の微細化や三次元化に伴って必要
となるプロセス温度の低温化に対しては必ずしも好まし
い方法ではない。However, the above-mentioned thermal oxidation process involves a high temperature of about 100 OC', which is not necessarily a preferable method for lowering the process temperature, which is required with miniaturization and three-dimensionalization of elements.
そこで、プラズマを用いた低温プロセスが注目され、８
１基板のプラズマ［接酸化によるゲート絶縁膜形成やプ
ラズマＣＶＤ法によるバッシベー７ヨン膜形成が研究開
発されるようになった。Therefore, low-temperature processes using plasma have attracted attention, and 8
Research and development has begun on the formation of gate insulating films by plasma oxidation on one substrate and the formation of basibayon films by plasma CVD.
ところで、プラズマ利用プロセスには、荷電粒子による
照射損１という大きな問題があり、界面特性のよい絶縁
膜を形成するのは難しいのが現状である。例えば、酸素
プラズマを半導体基板に照射して、絶縁膜を成長させる
方法では、膜成長を促進するために、基板に電圧を印加
することが行われるが、（Ｔ、 ８ｎｇａｎｏ ： Ｔ
ｈ１ｎ Ｓｏｌ ｉｄ ｐｉ Ｉｍｓ 。Incidentally, plasma-based processes have a major problem of irradiation loss 1 due to charged particles, and it is currently difficult to form an insulating film with good interfacial properties. For example, in a method of growing an insulating film by irradiating a semiconductor substrate with oxygen plasma, a voltage is applied to the substrate to promote film growth.
h1n Solid pi Ims.
９２ （１９８２） ｌ ９ ）これは、膜成長の場加
とともに照射損傷も大きくしてしまう。しかしながら、
基板に電圧を印加させないと、速い成長速度は得られず
、厚い膜を形成するのは困−である。厚い絶縁膜を低温
で得る方法には、前述したようにプラズマＣＶＤがめる
。これは、プラズマを用いて、ガスの解離及び反応を促
進して基板上に堆積させるため、低い温度で厚い膜の形
成も可能である。92 (1982) l9) This increases the field stress for film growth as well as irradiation damage. however,
Unless a voltage is applied to the substrate, a high growth rate cannot be obtained and it is difficult to form a thick film. As mentioned above, plasma CVD is used to obtain a thick insulating film at low temperatures. Since this method uses plasma to promote gas dissociation and reaction and deposit it on a substrate, it is possible to form a thick film at a low temperature.
しかし、この方法では、処理前に基板表面に存在する不
純物等が、絶縁膜形成後も界面に残るために、界面特性
は前述のプラズマ酸化、窒化とは比べものにならないぐ
らい悪い、また、反応性ガス中には構成元素のひとつと
して水素が含まれているためにプラズマＣＶＤにおいて
はこれが膜中に取）込まれ、絶縁膜の特性に様々な悪影
ｌ＃を及ぼすことが知られている。However, with this method, impurities that exist on the substrate surface before processing remain at the interface even after the insulating film is formed, so the interface properties are incomparably worse than the plasma oxidation and nitridation described above, and the reactivity is Since hydrogen is contained in the gas as one of the constituent elements, it is known that in plasma CVD, hydrogen is incorporated into the film and exerts various negative effects on the properties of the insulating film.
以上述べてきたように、界面特性や膜質に優れ、半導体
の能動、受動領域の全てに亘って使用可能な絶縁ｐＩ＆
をプラズマ利用プ、σセスを用いて作るのは、従来の方
法では困難でめった。As mentioned above, insulating pI&
It is difficult and rare to make using plasma-based processes using conventional methods.
本発明の目的に、不純物の少ない、界面特性がすぐれた
、絶縁膜を所望の厚さく低温で形成する方法を提供する
ことにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming an insulating film with a desired thickness and low impurity and excellent interfacial properties at a low temperature.
上記目的を達成する為、本発明では、増速酸化の起こる
初期の酸化段階金＜９返すことにより所望の厚さの絶縁
膜を低温で得るものでるる。In order to achieve the above object, the present invention makes it possible to obtain an insulating film of a desired thickness at a low temperature by reducing the initial oxidation stage of gold <9 in which accelerated oxidation occurs.
すなわち、第１図は、基板にバイアスを印加せずにプラ
ズマ酸化を行った時の酸化膜の成長特性を示し友もので
ある。酸化速度は、時間がたつと飽和傾向を示すため、
１１００ｎ以上の酸化膜を形成するのは困難である。し
かし、初期の３０分程度においては、増速酸化が起こり
、１０Ａ／−程度の成長速度も実現できることがわかる
。That is, FIG. 1 shows the growth characteristics of an oxide film when plasma oxidation is performed without applying a bias to the substrate. The oxidation rate tends to saturate over time, so
It is difficult to form an oxide film with a thickness of 1100n or more. However, it can be seen that accelerated oxidation occurs during the initial period of about 30 minutes, and a growth rate of about 10 A/- can be achieved.
このように、基板にバイアスを印加しない方法で形成し
た酸化膜を用いて、ＭＯ８キャパシタを作り％ Ｓ １
Ｏｘ界面の界面準位密度を調べた結果を第２図に示し
た。熱酸化膜に匹敵する界面特性が得られており、これ
は、荷電粒子による照射損傷が低減されているためと考
えられる。In this way, an MO8 capacitor is made using an oxide film formed in a manner that does not apply a bias to the substrate, and the % S 1
Figure 2 shows the results of examining the interface state density at the Ox interface. Interface properties comparable to those of thermal oxide films were obtained, and this is thought to be due to reduced irradiation damage caused by charged particles.
上記の結果から、十分な膜厚を有し、かつ界面特性の良
好な酸化膜を形成する方法として、３ｊ蒸着膜のプラズ
マ酸化の〈シ返しが有効である。From the above results, plasma oxidation of the 3J vapor deposited film is effective as a method for forming an oxide film with sufficient thickness and good interface properties.
すなわち、初期の増速酸化が可能な２０〜３０ｎｍ程度
のＳｉ蒸着属を形成し、これをプラズマ酸化する工程を
数回くシ返せばよい。That is, it is sufficient to repeat the steps several times to form a Si vapor deposited layer of about 20 to 30 nm, which is capable of initial accelerated oxidation, and to oxidize it with plasma.
この方法で形成した５ｉＯａ膜の界面特性は、８ｉ、ｉ
ｊ、着時の基板表面の清浄度に大きく依存すると考えら
れるが、昨今の超高真空技術利用によるＭＢＤ装置を用
いれば、十分な清浄度が実現できる。さらに、この工程
においては、ＣＶＤ法と違って、膜形成に必要な元素以
外の元素を用いていないため、不純物のとり込みがなく
膜質にもすぐれている。The interfacial properties of the 5iOa film formed by this method are 8i,i
j. Although it is thought that this largely depends on the cleanliness of the substrate surface at the time of deposition, sufficient cleanliness can be achieved by using an MBD apparatus that utilizes recent ultra-high vacuum technology. Furthermore, unlike the CVD method, this process does not use any elements other than those necessary for film formation, so impurities are not introduced and the film quality is excellent.
以上により、蒸ｆ８ｉａのプラズマ酸化のく）返し法に
よって、素子の受動領域はか９でなく、能動領域にも使
用可能な絶縁膜の低温形成が可能である。As described above, by the repeated plasma oxidation method of evaporation f8ia, it is possible to form an insulating film at a low temperature that can be used not only in the passive region of the device but also in the active region.
〔実施ガニ〕
まずＳｉ基板上にＳ ｉ Ｏｘ Ｊｌｊｊ、を形成した
例について述べる。[Example] First, an example in which Si Ox Jljj is formed on a Si substrate will be described.
第３図には、本笑施例で用いた装置の概略図を示す。本
装置は、同−高真空チエンバー内ＫＳｉを蒸発させるた
めの電子線加熱方式の蒸発源と、蒸着したＳｉをプラズ
マ処理するためのプラズマ源とを備えている。プラズマ
源としては、１０−’ｔｏｒｒ以下の低圧力においても
安定性よく放電が行える有磁場マイクロ波放電を用いた
。この方法の原理は、磁場中での電子のサイクロ）ｃｙ
ン運動を利用し、電子の実効移動短躯を長くすることに
より、希薄竜ガス中での電子と分子との衝突頻度を高め
放電を行なうものである。電子線加熱方式の蒸発源の動
作限界圧力は、１０”ｌ’ｏｒｒ であるから、本装置
では、Ｓｉ蒸発とプラズマ処理を又互に行なうことはも
ちろん同時に行なうことも可能である。FIG. 3 shows a schematic diagram of the apparatus used in this example. This apparatus is equipped with an electron beam heating type evaporation source for evaporating the KSi in the high vacuum chamber, and a plasma source for plasma processing the deposited Si. As a plasma source, a magnetic field microwave discharge was used, which can perform stable discharge even at low pressures of 10-'torr or less. The principle of this method is that electron cyclones (cy) in a magnetic field
By utilizing the electron motion and lengthening the effective short length of electron movement, the frequency of collisions between electrons and molecules in dilute dragon gas is increased, resulting in discharge. Since the operating limit pressure of the electron beam heating type evaporation source is 10''l'orr, in this apparatus, Si evaporation and plasma treatment can be performed not only simultaneously, but also simultaneously.
第１図に示した酸化特性を考慮し、電子銃電力４０ＱＷ
で１０分間蒸着することによシ約２゜ｎｍの８ｉ膜を形
成し、これを、基板温度６０００１マイクロ波パワー１
４０Ｗで約３０分プラズマ酸化した。この操作を３回〈
り約し、約１．５時間で約１１００ｎの５ｊ（ｈ膜を形
成した。Considering the oxidation characteristics shown in Figure 1, the electron gun power was 40QW.
An 8i film with a thickness of approximately 2 nm was formed by vapor deposition for 10 minutes at a substrate temperature of 60,000 and a microwave power of 1.
Plasma oxidation was performed at 40W for about 30 minutes. Repeat this operation 3 times
A 5j(h film) of about 1100 nm was formed in about 1.5 hours.
赤外吸収特性及びエッチ速度測定から、水素などの不純
物を含まず、Ｓｉ基板をプラズマ酸化した膜に匹敵する
緻密度を有する８ｉ０＊ａが得られることがわかつ九。From infrared absorption characteristics and etch rate measurements, it was found that 8i0*a was obtained that did not contain impurities such as hydrogen and had a density comparable to that of a film obtained by plasma oxidation of a Si substrate.9.
同様に、プラズマ窒化を行ない水素を含まない８ｉｘＮ
４膜を形成できる。窒化は一般に酸化よりｌ１でおるが
、この方法によれば、拡散律速で窒化適度が飽和するｔ
丘どの厚い５ｉｌＩＩ＆を窒化する必要はなく、薄い膜
の窒化をくり返せばよく、十分な膜厚の８ｉｍＮＡ膜が
得られる。Similarly, 8ixN which does not contain hydrogen by plasma nitriding
4 films can be formed. Nitriding generally takes less than 11 compared to oxidation, but according to this method, the nitriding mode saturates due to diffusion control.
It is not necessary to nitride the thick 5ilII& film, and it is sufficient to repeat the nitridation of the thin film, and an 8imNA film with a sufficient thickness can be obtained.
〔実施例２］
次に超高真空Ｓｉ蒸Ｍ装置（ＭＢＤ）を用いて、ガラス
基板上に、薄膜トランジスタ（ＴＦ’ＴＩ作成した例に
ついて述べる。[Example 2] Next, an example in which a thin film transistor (TF'TI) was formed on a glass substrate using an ultra-high vacuum Si vaporization device (MBD) will be described.
第４図に、今回作成したＴＰＴの断面構造を示した。２
Ｘ １０” ｔａｒｔまで排気されたＭＢＤ装置内で
、ガラス基板９上に１μｍのｐｏｌｙ Ｓ ｉ ＭＪｌ
ｌｔ−形成する。基板温度は５ｏｏＣ％蒸着速度は１人
／戴である。装置外に出して、ＣＶＤ ５ｉｆｔマス
クを用いてイオン打込みし、ソース、ビレ４フ層２．３
ｔ−形成した後、再びＭＢＤ装置内に戻す。イオンスパ
ッタで表面クリーニングの後、再Ｕ８ｉ’ｉＡＭし、約
２Ｑｎｍのａ−８ｉｍｆｔ形成し、その後約３０分のプ
ラズマ酸化を行った。プラズマ酸化条件は実施例１と同
じでおる。これを２回くり返し、約７Ｑｎｍのゲート５
ｊ０２膜４を形成した。次に、ゲート′＃Ｌ極６、Ａｔ
’ｌｉ℃を設け −た。Figure 4 shows the cross-sectional structure of the TPT created this time. 2
In the MBD device that was evacuated to X 10” tart, a 1 μm poly Si
lt-form. The substrate temperature was 5ooC% and the deposition rate was 1 person/person. After taking it out of the device, ion implantation was performed using a CVD 5ift mask to form the source, fillet 4, and fillet layers 2.3.
After t-forming, it is returned to the MBD device. After surface cleaning by ion sputtering, U8i'iAM was performed again to form an a-8imft of about 2Q nm, and then plasma oxidation was performed for about 30 minutes. The plasma oxidation conditions were the same as in Example 1. Repeat this twice and use the gate 5 of about 7Qnm.
A j02 film 4 was formed. Next, gate '#L pole 6, At
'li℃ was set.
上記ＴＰＴの出力特性（Ｉｎｔｏ％性）ｔ−測定し、し
きい値屯圧Ｖｔｔ求めたところ、従来のＣＶＤ−８ｉ（
ｈｔ”ゲート絶縁膜としたものに比べ、Ｖでか小さくな
ることがわかった。これは、Ｓ ｒ Ｏｘ−ｐｏｌｙ
Ｓ ！ 界面のトラップ準位が減少した効果と考えられ
る。When we measured the output characteristic (into% characteristic) t of the above TPT and determined the threshold pressure Vtt, we found that the conventional CVD-8i (
ht” gate insulating film, it was found that the V was smaller than that of the S r Ox-poly
S! This is thought to be an effect of a decrease in the trap levels at the interface.
〔発明の効果］
本発明の方法によれば、不純物を含まず、界面特性も良
好な、高品質絶縁膜を所望の厚さで低温形成することが
可能である。[Effects of the Invention] According to the method of the present invention, it is possible to form a high-quality insulating film to a desired thickness at a low temperature, which does not contain impurities and has good interface properties.
第１図は、プラズマ酸化による膜成長特性を示す図、第
２図は、プラズマ酸化膜の界面準位密度を示す図、第３
図は、プラズマ酸化、窒化及びＳｉ蒸着を同一チェンバ
ー内で行なえる装置の構ＴＰＴデバイスの断面構造を示
を図である。
１・・・ポリシリコン襄、２・・・ソース領域、３・・
・ドレイン領域、４・・・酸化膜、５・・・アルミニウ
ム電極、６・・・ゲート電極、９・・・ガラス基板、３
０・・・高真空容器、３１・・・有磁場マイクロ波プラ
ズマ源、３２・・・プラズマ流、３３・・・５ｉｉＡ発
源、３４・・・Ｓｉ蒸■ １ 図
０１ρ １２ρ ｌθＩ肋髪化帳間
Ｃ分〕
藁 ２ 図
界面ホ゛テンン♀ル Ｃｅン〕
ｆ４ 図Figure 1 is a diagram showing the film growth characteristics by plasma oxidation, Figure 2 is a diagram showing the interface state density of a plasma oxide film, and Figure 3 is a diagram showing the interface state density of a plasma oxide film.
The figure shows a cross-sectional structure of a TPT device, which is an apparatus in which plasma oxidation, nitridation, and Si deposition can be performed in the same chamber. 1...Polysilicon layer, 2...Source region, 3...
- Drain region, 4... Oxide film, 5... Aluminum electrode, 6... Gate electrode, 9... Glass substrate, 3
0...High vacuum container, 31...Magnetic field microwave plasma source, 32...Plasma flow, 33...5iiA source, 34...Si vaporization 1 while
C minute] straw 2 figure surface text
Claims (1)
造方法において、高速にプラズマ処理される膜厚以下の
Ｓｉ膜を堆積する工程と、該Ｓｉ膜をプラズマ処理する
工程とを交互に数回くり返すことにより絶縁膜を形成す
ることを特徴とする半導体装置の製造方法。In a method for manufacturing a semiconductor device in which an insulating film is formed in a plasma atmosphere, a step of depositing a Si film having a thickness equal to or less than that of a film that is subjected to high-speed plasma processing and a step of plasma processing the Si film are alternately repeated several times. 1. A method of manufacturing a semiconductor device, comprising forming an insulating film by forming an insulating film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25752784A JPS61136236A (en) | 1984-12-07 | 1984-12-07 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25752784A JPS61136236A (en) | 1984-12-07 | 1984-12-07 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61136236A true JPS61136236A (en) | 1986-06-24 |
Family
ID=17307530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25752784A Pending JPS61136236A (en) | 1984-12-07 | 1984-12-07 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61136236A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005229129A (en) * | 2000-06-08 | 2005-08-25 | Genitech Inc | Method of forming thin film |
-
1984
- 1984-12-07 JP JP25752784A patent/JPS61136236A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005229129A (en) * | 2000-06-08 | 2005-08-25 | Genitech Inc | Method of forming thin film |
| JP4684706B2 (en) * | 2000-06-08 | 2011-05-18 | ジニテック インク． | Thin film formation method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5412246A (en) | Low temperature plasma oxidation process | |
| US4804640A (en) | Method of forming silicon and aluminum containing dielectric film and semiconductor device including said film | |
| US7033958B2 (en) | Semiconductor device and process for producing the same | |
| US7488655B2 (en) | Method for fabricating semiconductor device | |
| JP3746478B2 (en) | Manufacturing method of semiconductor device | |
| US6825538B2 (en) | Semiconductor device using an insulating layer having a seed layer | |
| US5336361A (en) | Method of manufacturing an MIS-type semiconductor device | |
| US7326988B2 (en) | Semiconductor device and method for fabricating the same | |
| JP2004266263A (en) | Method for manufacturing semiconductor device | |
| CN115295407B (en) | Preparation method of gate oxide structure of SiC power device and gate oxide structure | |
| CN111430228A (en) | Preparation method of dielectric film with ultrahigh dielectric constant | |
| JPS61136236A (en) | Manufacture of semiconductor device | |
| KR940005290B1 (en) | Method of forming a dielectric film and semiconductor device including said film | |
| JPH10270434A (en) | Semiconductor wafer cleaning method for oxide film forming method | |
| JP2840802B2 (en) | Method and apparatus for manufacturing semiconductor material | |
| JP2001308319A (en) | Insulated gate compound semiconductor device | |
| JPH04199828A (en) | Manufacture of oxide thin film of high dielectric constant | |
| KR100379533B1 (en) | method for fabricating gate insulating film of semiconductor device | |
| JP2003086588A (en) | Manufacturing method of mis-type semiconductor device | |
| JP2006216774A (en) | Method of forming insulating film | |
| KR100395912B1 (en) | Method for forming the gate electrode in semiconductor device | |
| JPH02142187A (en) | Insulated gate type field effect transistor | |
| KR20010045963A (en) | Method of manufacturing a capacitor in a semiconductor device | |
| JP2003188374A (en) | Semiconductor device and method of manufacturing the same | |
| JPH03156919A (en) | Formation of metal-semiconductor junction |