JPS6112107A - Input circuit of hall element - Google Patents

Input circuit of hall element

Info

Publication number
JPS6112107A
JPS6112107A JP13356384A JP13356384A JPS6112107A JP S6112107 A JPS6112107 A JP S6112107A JP 13356384 A JP13356384 A JP 13356384A JP 13356384 A JP13356384 A JP 13356384A JP S6112107 A JPS6112107 A JP S6112107A
Authority
JP
Japan
Prior art keywords
voltage
hall element
current
circuit
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13356384A
Other languages
Japanese (ja)
Other versions
JPH0325046B2 (en
Inventor
Kenzou Shiyou
鍾　健三
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP13356384A priority Critical patent/JPS6112107A/en
Publication of JPS6112107A publication Critical patent/JPS6112107A/en
Publication of JPH0325046B2 publication Critical patent/JPH0325046B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/30—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters
    • H03F1/302—Modifications of amplifiers to reduce influence of variations of temperature or supply voltage or other physical parameters in bipolar transistor amplifiers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Amplifiers (AREA)

Abstract

PURPOSE:To obtain an input circuit operated even with a low power supply voltage by shifting the level of an output of a Hall element with a simple circuit. CONSTITUTION:The voltage VH fed to the Hall element 1 is divided into a voltage VA by resistors R1, R2. The voltage VA is converted into a current I0 by a current converting circuit comprising TRs 2-8 and a resistor R3. The current I0 is converted into a voltage by an output voltage converting circuit comprising TRs 9-12 and a resistor R4. A voltage VC generated across the resistor R4 depends on the resistors R1-R4. On the other hand, an input voltage VIN of the 1st stage TR13 of the amplifier section is expressed as VIN=VH/2-VC. Thus, the power supply voltage VCC required for the amplifier section is VCC>=VF+VIN and the power supply voltage required for operating the input circuit is set to, e.g., 1V between VF-2VF by deciding properly the value of the resistors R1- R4.

Description

【発明の詳細な説明】 （ａ）技術分野 この発明はホール素子出力を増幅する入力回路に関する
。DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field The present invention relates to an input circuit that amplifies the output of a Hall element.

（ｂｌ従来技術とその欠点 ホール素子１は一般に第２図に示すように電源端子ａ−
ｂ間に加わる電圧を■８とすると、出力端子Ｃに発生す
る電圧がＶＨ／２となる。またホール素子出力を増幅す
る場合には、その出力端子と入力回路の初段トランジス
タとの結合状態は通常、直結状態にされる。したがって
、仮に第２図においてホール素子１に印加される電圧Ｖ
Ｈを電源電圧ＶＣＣに等しく設定すると、入力初段トラ
ンジスタＴＲＩでホール素子出力を正確に増幅するには
Ｖｌｌ／２＝ｖＣＣ／２〉■Ｆにしなければならず、低
電圧の電源電圧ＶＣＣを使用できない不都合があった。(bl Prior art and its drawbacks) The Hall element 1 generally has a power terminal a-- as shown in FIG.
If the voltage applied between b is 8, the voltage generated at the output terminal C will be VH/2. Further, when amplifying the output of the Hall element, the output terminal thereof and the first stage transistor of the input circuit are usually connected directly. Therefore, if the voltage V applied to the Hall element 1 in FIG.
If H is set equal to the power supply voltage VCC, in order to accurately amplify the Hall element output with the input first stage transistor TRI, it is necessary to set Vll/2 = vCC/2〉■F, and the low voltage power supply voltage VCC cannot be used. There was an inconvenience.

即ち、入力回路の電源電圧ＶＣＣとしては、少なくとも
２ＶＦ以上の電圧が必要であり、Ｖ　Ｆ−０，７Ｖ程度
であるから１ｖ程度の抵い電圧の電源電圧を使用できな
い欠点があった（Ｃ）発明の目的 ゛この発明゛の目的は上記の欠点を解消し、ホール素子
出力を簡単な回路でレベルシフトすることにより電源電
圧が低くても動作する入力回路を提供することにある。That is, the power supply voltage VCC of the input circuit requires a voltage of at least 2VF or more, and since it is about VF-0.7V, there is a drawback that a power supply voltage with a resistance voltage of about 1V cannot be used (C). OBJECTS OF THE INVENTION An object of the present invention is to eliminate the above-mentioned drawbacks and to provide an input circuit that operates even at a low power supply voltage by level-shifting the Hall element output using a simple circuit.

：（ｄ）発明の構成 この発明は要約すれば、電源電圧を抵抗分割する回路と
、その分割した電圧を電流変換する回路と、さらにその
変換した電流を抵抗によって電圧変換し、その変換電圧
をホール素子出力に加えてレヘルシフトするＩ：ｇＪ路
とを設けたことを特徴とし抵抗比によってホール素子出
力をＶ）Ｉ／２以下にレヘルシフトシ、電源電圧が２Ｖ
Ｆ以下でも入力回路が動作するようにしたものである。:(d) Structure of the Invention To summarize, the present invention includes a circuit that divides a power supply voltage with a resistance, a circuit that converts the divided voltage into a current, and further converts the converted current into a voltage using a resistor, and converts the converted voltage into a voltage. It is characterized by providing a level-shifting I:gJ path in addition to the Hall element output, and depending on the resistance ratio, the Hall element output is level-shifted to below I/2, and the power supply voltage is 2V.
The input circuit is designed to operate even when the temperature is below F.

（ｅ）実施例 第１図はこの発明の実施例である入力回路の回路図であ
る。(e) Embodiment FIG. 1 is a circuit diagram of an input circuit which is an embodiment of the present invention.

図において、ホール素子１の電源端子ａ、ｂには、電圧
■、が印加され、また電圧Ｖ□は抵抗Ｒ１、Ｒ２からな
る抵抗分割回路によって電圧ＶＡに分割される。分割さ
れた電圧■４はトランジスタＴＲ２に入力する。トラン
ジスタＴＲ２〜ＴＲ８および抵抗Ｒ３は電圧ＶＡを電流
■。に変換する電流変換回路を構成する。この電流変換
回路において１〜ランジスタＴＲ２は電圧Ｖ、をエミッ
タホロアで受け、トランジスタＴＲ３〜ＴＲ８はトラン
ジスタＴＲ７のヘース電圧■３が上記電圧■４乙こ一致
するよう動作する差動アンプを構成している。電流Ｉ。In the figure, voltage ■ is applied to power supply terminals a and b of Hall element 1, and voltage V□ is divided into voltage VA by a resistance divider circuit consisting of resistors R1 and R2. The divided voltage (4) is input to the transistor TR2. Transistors TR2 to TR8 and resistor R3 convert voltage VA into current ■. A current conversion circuit is configured to convert the current into . In this current conversion circuit, transistors 1 to TR2 receive voltage V at their emitter followers, and transistors TR3 to TR8 constitute a differential amplifier that operates so that the heath voltage (3) of transistor TR7 matches the voltage (4) above. . Current I.

はこの電圧■８を抵抗Ｒ３の両端に発生させることによ
り形成している。この電流変換回路によって電流■。は トランジスタＴＲ８〜ＴＲＩＩは共通−１−入接続され
、各トランジスタのエミッタ領域も同面積に設定されて
いる。−のため、Ｉ・ランジスタＴＲ８に電流Ｊ。が流
れると、トランジスタＴＲ９に同し大きさの電流Ｉ。′
か流れ、さらにダイオードに接続されたトランジスタＴ
Ｒｌ０．トランジスタＴＲ１２によって反転された電流
Ｉ。″がトランジスタＴＲＩＩを流れる。電流１ｏ　　
”は抵抗Ｒ４を流れ、この両端に電圧■。を形成する。is formed by generating this voltage (18) across the resistor R3. ■ Current by this current conversion circuit. The transistors TR8 to TRII are commonly connected to each other, and the emitter regions of each transistor are also set to have the same area. -, current J flows through I transistor TR8. flows, a current I of the same magnitude flows through the transistor TR9. ′
, and the transistor T connected to the diode
Rl0. Current I inverted by transistor TR12. '' flows through transistor TRII. Current 1o
” flows through the resistor R4, forming a voltage .

抵抗Ｒ４とトランジスタＴＲ１）の接続点ｄにはホール
素子１の出力端子Ｃか接続されている。トランジスタＴ
Ｒ９・〜ＴＲ１２および抵抗Ｒ４は出力電圧変換回路を
構成する。The output terminal C of the Hall element 1 is connected to the connection point d between the resistor R4 and the transistor TR1. transistor T
R9.about.TR12 and resistor R4 constitute an output voltage conversion circuit.

以上の構成によって抵抗Ｒ４の両端に発生する電圧Ｖ０
は Ｖ　（”　Ｔ　ｏ　　”　Ｘ　Ｒ４ ＝ＴｏＸＲ４ となる。また増幅部の初段トランジスタＴＲ］３の入力
電圧ＶＩＮは ＶＩＮ＝ＶＨ／２−ＶＣ−（３） となる。With the above configuration, the voltage V0 generated across the resistor R4
is V ("T o "

上記（２）、　（３１式から明らかなように電圧■。は
抵抗比率によって一義的に定まり、この値をホール素子
電圧から引いた電圧が初段トランジスタの入力電圧とな
る。したがって、増幅部に必要な電源電圧ＶＣＣば ＶＣＣ≧ＶＦ＋ＶＩＮ となり、上記（２）式の抵抗比率を適当に定めることに
より、入力回路を動作させるのに必要な電源電圧ｖｃｃ
をＶＦ〜２ＶＦの間、例えば１ｖに設定することができ
る。(2) above, (As is clear from Equation 31, the voltage ■) is uniquely determined by the resistance ratio, and the voltage obtained by subtracting this value from the Hall element voltage becomes the input voltage of the first stage transistor. If the power supply voltage VCC is VCC, then VCC≧VF+VIN, and by appropriately determining the resistance ratio in equation (2) above, the power supply voltage VCC required to operate the input circuit can be determined.
can be set between VF and 2VF, for example, 1v.

（ｆ１発明の効果 以」二のようにこの発明によれば、入力回路を作動させ
るための電源電圧ＶＣＣを２ＶＦ以下に設定することが
できるため、電源電圧が低電圧の電子機器にも組み込む
ことができる。また抵抗分割回路、電流変換回路、電圧
変換回路等は簡単な回路の組合せによって構成できるた
め、回路構成も複雑化しない利点がある。(f1 Effects of the Invention) According to this invention, the power supply voltage VCC for operating the input circuit can be set to 2VF or less, so it can be incorporated into electronic equipment with a low power supply voltage. Furthermore, since the resistance divider circuit, current conversion circuit, voltage conversion circuit, etc. can be configured by a combination of simple circuits, there is an advantage that the circuit configuration does not become complicated.

【図面の簡単な説明】[Brief explanation of drawings]

第１図はこの発明の実施例である入力回路の回路図を示
し、第２図は従来の入力回路の初段トう・ンジスクとホ
ール素子の結合部を示す図である。 １−ポール素子。FIG. 1 shows a circuit diagram of an input circuit according to an embodiment of the present invention, and FIG. 2 is a diagram showing a coupling portion between a first-stage connector and a Hall element of a conventional input circuit. 1-pole element.

Claims (1)

【特許請求の範囲】[Claims] （１）電源電圧を抵抗分割する抵抗分割回路と、その分
割した電圧を電流変換する電流変換回路と、その変換し
た電流を抵抗によって電圧変換しその変換電圧をホール
素子出力に加えてホール素子出力をレベルシフトする出
力電圧変換回路とを備えてなるホール素子の入力回路。(1) A resistance divider circuit that divides the power supply voltage with resistance, a current conversion circuit that converts the divided voltage into a current, and a resistor that converts the converted current into a voltage and adds the converted voltage to the Hall element output and outputs the Hall element. A Hall element input circuit comprising an output voltage conversion circuit that level-shifts the output voltage.
JP13356384A 1984-06-27 1984-06-27 Input circuit of hall element Granted JPS6112107A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13356384A JPS6112107A (en) 1984-06-27 1984-06-27 Input circuit of hall element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13356384A JPS6112107A (en) 1984-06-27 1984-06-27 Input circuit of hall element

Publications (2)

Publication Number Publication Date
JPS6112107A true JPS6112107A (en) 1986-01-20
JPH0325046B2 JPH0325046B2 (en) 1991-04-04

Family

ID=15107725

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13356384A Granted JPS6112107A (en) 1984-06-27 1984-06-27 Input circuit of hall element

Country Status (1)

Country Link
JP (1) JPS6112107A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03274021A (en) * 1990-03-23 1991-12-05 Mitsubishi Electric Corp Production of liquid crystal display device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03274021A (en) * 1990-03-23 1991-12-05 Mitsubishi Electric Corp Production of liquid crystal display device
JP2822558B2 (en) * 1990-03-23 1998-11-11 三菱電機株式会社 Liquid crystal display device and method of manufacturing the same

Also Published As

Publication number Publication date
JPH0325046B2 (en) 1991-04-04

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