JPS6112082A - Manufacture of compound semiconductor device - Google Patents
Manufacture of compound semiconductor deviceInfo
- Publication number
- JPS6112082A JPS6112082A JP13236484A JP13236484A JPS6112082A JP S6112082 A JPS6112082 A JP S6112082A JP 13236484 A JP13236484 A JP 13236484A JP 13236484 A JP13236484 A JP 13236484A JP S6112082 A JPS6112082 A JP S6112082A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- photoresist
- film
- insulating film
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 150000001875 compounds Chemical class 0.000 title claims description 5
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000002184 metal Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 14
- 150000002500 ions Chemical class 0.000 claims description 8
- 239000000758 substrate Substances 0.000 claims description 8
- 239000012535 impurity Substances 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 2
- 238000005468 ion implantation Methods 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- 238000000151 deposition Methods 0.000 claims 2
- 230000003213 activating effect Effects 0.000 claims 1
- 238000001947 vapour-phase growth Methods 0.000 claims 1
- 238000010438 heat treatment Methods 0.000 abstract description 7
- 238000006243 chemical reaction Methods 0.000 abstract description 5
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 abstract description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 3
- 229910045601 alloy Inorganic materials 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 3
- 230000004888 barrier function Effects 0.000 abstract description 3
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 238000001704 evaporation Methods 0.000 abstract description 2
- 230000008020 evaporation Effects 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract 3
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 229910009052 W5Si3 Inorganic materials 0.000 abstract 1
- 238000004140 cleaning Methods 0.000 abstract 1
- 238000002161 passivation Methods 0.000 abstract 1
- 230000000717 retained effect Effects 0.000 abstract 1
- 238000005406 washing Methods 0.000 abstract 1
- 238000005530 etching Methods 0.000 description 10
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 5
- 150000002739 metals Chemical class 0.000 description 4
- 108091006146 Channels Proteins 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000001354 calcination Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002353 field-effect transistor method Methods 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000005979 thermal decomposition reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は化合物半導体装置、特にＧａＡｓメタルシ目ッ
トキットキー接合電界効果トランジスタ方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a compound semiconductor device, and more particularly to a GaAs metal junction field effect transistor method.
（従来の技術）
（３ａＡｓメタルシヨツトキ一接合電界効果トランジス
タでは、従来ゲート金属としてＴｉ／ｋｌ又はＡｔが用
いられいる。これらの金属はゲート長を短くして高周波
特性を改善する上で加工性が悪いため歩留が低い。又シ
ョットキー接合を形成するため°に施される合金化処理
は４２０〜４５０’Ｃの極めて短い時間の処理工程であ
るので、ショットキーダイオード特性のバラツキが大き
い。このバラツキは基板ウェハーのサイズが大きくなる
に従って更に大きくなる。素子の信頼度点に関しては特
に高電力素子においでショットキ接合の金属とＧ ａ
Ａ ｓとの界面での反応が進行しシｍｙトキーダイオー
ド特性の経時的劣化を生じるという問題がある。本発明
はこれらの問題点に着目したものである。(Prior art) (In 3aAs metal shot one-junction field effect transistors, Ti/kl or At is conventionally used as the gate metal.These metals have poor processability in order to shorten the gate length and improve high frequency characteristics. In addition, since the alloying treatment performed to form the Schottky junction is an extremely short process at 420 to 450'C, the Schottky diode characteristics vary widely.This variation becomes larger as the size of the substrate wafer increases.In terms of device reliability, especially in high-power devices, the Schottky junction metal and Ga
There is a problem in that the reaction at the interface with As progresses, resulting in deterioration of the characteristics of the Schmytokey diode over time. The present invention focuses on these problems.
Ｗ、ＴｉＷ、Ｔａとこ２れらのミリサイドは高温の熱処
理で安定でＧ ａ Ａ ｓとの反応も極めて少ないこと
が知られている。又、異方性を持つリアクティブイオン
エッチでもサブミクロンのパターンの形成が再現性よく
行なえる等の特徴を有する。しかし、このような金属又
はシリサイドをゲートメタルとして用いたときの欠点と
いえば、通常用いられるＡｔに比べて、電気抵抗が１０
〜１００倍位大きいため、ゲート抵抗が大きく、高周波
での動作特性が悪いことである。特にゲート幅が大きく
なると問題となる。そこでゲート抵抗を低減するために
はどうしても電気抵抗の低い金属を積層する必要性が生
じる。例えばＡｕを積層する場合、イオン注入によ５Ｇ
ａＡｓ基板にｎ型導伝性の不純物であるＳｉイオンを用
いたチャンネル層を形成した後に、Ａｕを積層したゲー
トを形成し、そのチャンネル層を熱処理する事によって
電気的に活性化する。この熱処理工程中に、Ａｕとその
下層の金属との反応が生じ、ショットキ特性を劣化させ
てしまう。そこで、Ａｕを拡散させないように、二層間
にＡｕの拡散を防ぐバリア層を用いることが重要となる
。It is known that W, TiW, Ta, and these two milicides are stable when subjected to high-temperature heat treatment, and their reaction with GaAs is extremely low. Furthermore, reactive ion etching with anisotropy also has the feature that submicron patterns can be formed with good reproducibility. However, the disadvantage of using such metals or silicides as gate metals is that the electrical resistance is 10% lower than the commonly used At.
Since it is about 100 times larger, the gate resistance is large and the operating characteristics at high frequencies are poor. This becomes a problem especially when the gate width becomes large. Therefore, in order to reduce the gate resistance, it is necessary to stack metals with low electrical resistance. For example, when stacking Au, 5G
After forming a channel layer using Si ions, which are n-type conductive impurities, on an aAs substrate, a gate is formed by stacking Au, and the channel layer is electrically activated by heat treatment. During this heat treatment step, a reaction occurs between Au and the underlying metal, resulting in deterioration of the Schottky characteristics. Therefore, it is important to use a barrier layer between the two layers to prevent Au from diffusing.
（発明が解決しようとする問題点）
本発明の目的は、ソースドレイン領域のオーミックメタ
ルとのコンタクト抵抗とＦＢＴ特性を改善する上で重要
なソース抵抗を低減した化合物半導体装置の製造方法を
得ることにある。(Problems to be Solved by the Invention) An object of the present invention is to obtain a method for manufacturing a compound semiconductor device in which the source resistance, which is important for improving the contact resistance with the ohmic metal in the source/drain region and the FBT characteristics, is reduced. It is in.
（問題を解決するための手段）
本発明はチャンネル層よシ濃度の高いソースおよびドレ
イン電極接続用高濃度領域全ゲート電極の脇に近接して
形成した上にオーミックメタルを被着することにより、
よシ安定な再現性のよいオーミ、りを得る工程を採用し
たことが特徴である。(Means for Solving the Problems) The present invention forms high concentration regions for connecting source and drain electrodes with a high concentration in the channel layer, all of which are formed close to the side of the gate electrode, and then coats an ohmic metal on the high concentration regions for connecting the source and drain electrodes.
It is characterized by the adoption of a process to obtain ohms and ri with good stability and reproducibility.
（実施例）
次に１本発明の製造方法による一実施例を第１図体）〜
（ｈ）の断面図を用いてよシ詳細に説明する。(Example) Next, an example according to the manufacturing method of the present invention is shown in Figure 1) ~
This will be explained in detail using the cross-sectional view in (h).
まず、半絶縁性Ｇａ Ａ ｓ基板１に将来チャンネル層
となるｎ型不純物層２ ’ｔ” ７０ ＫｅＶのエネル
ギードース量４ＸＬＯ１２ｃＩｒＬ−２で８ｉイオンの
注入を行なう（第１図（ａ））。次に、ＲＦスパ、クリ
ング法でシロ、トキ金属としてＷ５ Ｓ ｉ ３ ’３
を３０００〜５０００Ｘの厚さに被着し、さらに熱分解
によるＣＶＤ法で８ｉ０２膜４を２０００Ｘ被着したの
ち、ホトレジストによるリングラフイーによりゲート長
１μｍのホトレジストパターン５を形成する（第１図（
ｂ））。First, 8i ions are implanted into a semi-insulating GaAs substrate 1 at an energy dose of 4XLO12cIrL-2 at an energy dose of 70 KeV (Fig. 1(a)). In, RF spa, Shiloh by Kring method, W5 Si 3 '3 as Toki Metal
was deposited to a thickness of 3,000 to 5,000×, and further an 8i02 film 4 was deposited at 2,000× using a thermal decomposition CVD method, and then a photoresist pattern 5 with a gate length of 1 μm was formed by photoresist ring graphing (see Fig. 1).
b)).
平行平板型のりアクティブイオンエツチャーを用い、
ＣＦ４＋ Ｈ２（２７チ）のガスで圧力、ＲＦパワート
バイアスヲそれぞれ４．５Ｐａ、２００Ｗ。Using a parallel plate glue active ion etcher,
CF4 + H2 (27 cm) gas pressure and RF power bias were 4.5 Pa and 200 W, respectively.
３５０±２０Ｖの条件に設定し、先ずＷ５８ ｔ ３膜
３上の５ｉ０２膜４をエツチングによって除去する。The condition is set to 350±20V, and first, the 5i02 film 4 on the W58 t3 film 3 is removed by etching.
このとき、８ｉ０２膜４とホトレジストパターン５のエ
ツチング比は約２で８ｉ０２膜４のエツチング速度は３
６０Ａ／ｍｉｎであり、エツチング時間はオーバーエツ
チング時間約１５秒を含めて５分５０秒である。この工
程の後、異方性の強いエツチングに有利なＥＣＲ型ドラ
ドライエツチャーＦ６ガスヲ用い、ＥＣＲ電圧、ガス圧
、マイクロ波パワーとイオン電流のそれぞれを２ Ｑｖ
ｌ １．２ Ｘ Ｉ Ｏｏ−３Ｔｏｒｒｔｏｏ、 ０
．ｔ ５ｍＡ／ｃｍ２に設定し、Ｗｓ Ｓ を膜３をエ
ツチングする。このエツチング条件ではＷ５８ ｉ ３
３．８ｉ０□膜４とホトレジストパターン５のエツチン
グ速度はそれぞれ２２０久／ｍ ｉｎ 、 ３２＾／ｍ
ｉｎ。At this time, the etching ratio between the 8i02 film 4 and the photoresist pattern 5 is approximately 2, and the etching rate of the 8i02 film 4 is 3.
The etching time was 5 minutes and 50 seconds, including an overetching time of about 15 seconds. After this step, ECR voltage, gas pressure, microwave power, and ion current were each adjusted to 2 Qv using an ECR type doradry etcher F6 gas, which is advantageous for highly anisotropic etching.
l 1.2 X I Oo-3Torrtoo, 0
．． t is set at 5 mA/cm2, and the film 3 is etched with Ws S . Under this etching condition, W58 i 3
The etching rates of the 3.8i0□ film 4 and the photoresist pattern 5 are 220 min/min and 32^/m, respectively.
in.
Ｂ□Ｘ／ｍｉｎとなシホトレジストパターン５及び８、
ｉ０２膜４が残った状態でＷ５８ ｉ ３膜３のエツチ
ングが可能で、しかもＧａＡｓの表面はｔｌとんどエツ
チングされない。ホトレジストパターン５０寸法はＷ５
Ｓｉ３３へ精度よく転写され、ホトレジストパター：１
５Ｃ１１／ＪｍはＷ５Ｓｉ３３−１’ ０．９／Ｊｍと
なる（第１図（Ｃ））。B□X/min photoresist patterns 5 and 8,
The W58 i3 film 3 can be etched with the i02 film 4 remaining, and the GaAs surface is hardly etched. Photoresist pattern 50 dimension is W5
Accurately transferred to Si33, photoresist pattern: 1
5C11/Jm becomes W5Si33-1' 0.9/Jm (FIG. 1(C)).
次の工程では、イオン注入によるｎ 導伝層をゲートメ
タル３に自動的に形成するため％ ＣＶＤＩｃ Ｌ ｂ
Ｓ ｓ ０２膜４’ｔ−１０００〜２０００ Ｘ被着
し８ｉイオンを注入エネルギー２００ＫｅＶ 、ドース
１ｘｌＯｃＩＩＬ の注入を膜を通して行なう。このと
きゲートメタル３の下部とゲートメタル３の側壁下部の
ＧａＡｓにはイオン注入はされず、ゲートメタル３から
Ｏｏ」〜０．２μｍ外側にｎ＋注入層が形成されること
になる。この状態でｓ Ｈ２雰囲気中で８５０℃、２０
分の熱処理を施し、ｎ型チャンネル層２とｎ＋型層６の
イオン注入層の電気的活性化を行なう（第１図（ｄ））
。In the next step, % CVDIc L b is used to automatically form an n conductive layer on the gate metal 3 by ion implantation.
A S s 02 film 4't-1000-2000X is deposited and 8i ions are implanted through the film at an energy of 200 KeV and a dose of 1xlOcIIL. At this time, ions are not implanted into the GaAs under the gate metal 3 and the lower sidewalls of the gate metal 3, and an n+ implanted layer is formed outside the gate metal 3 by 0.2 μm. In this state, 850℃, 20℃ in s H2 atmosphere.
The ion-implanted layers of the n-type channel layer 2 and the n+-type layer 6 are electrically activated by heat treatment for several minutes (Fig. 1(d)).
.
次に、ホトレジスト７を２μｍ厚で塗布し、８０℃、２
０分の仮焼篩めとそれに続く１８０℃６０分の焼きなま
しによってゲート凸起部のレジスト膜厚を減少させる（
第１図（ｅ））。Next, photoresist 7 was applied to a thickness of 2 μm and heated at 80°C for 2
The resist film thickness at the gate protrusion is reduced by 0 minutes of calcining and subsequent annealing at 180°C for 60 minutes (
Figure 1(e)).
続いて、平行平板型のりアクティブイオンエ。Next, the parallel plate type glue active ion.
チャーを用い、ＣＦ４＋０２（５チ）のガスで圧力。Using char, pressurize with CF4+02 (5 chi) gas.
ＲＦパワーとバイアスをそれぞれ４．５Ｐａ、２００Ｗ
、３５０±２０Ｖの条件で１８分エツチングを行なうと
、ゲート３の頭部のＳ ｉ０２膜４′が露出する。RF power and bias are 4.5Pa and 200W respectively.
, 350±20V for 18 minutes, the Si02 film 4' at the top of the gate 3 is exposed.
次に、ドライエツチングガスのみをＣＦ４＋Ｈ２（２７
チ）に切換え、他の条件は同一のまま１１分間エツチン
グすると、ｗ５Ｓｉ３３の頭部が露出する（第１図（ｆ
））。Next, use only dry etching gas as CF4+H2 (27
When etching was performed for 11 minutes under the same conditions, the head of w5Si33 was exposed (Fig.
)).
初めのドライエ、テンプではレジストアと８ ｉ０２膜
４′のエツチング速度比はｌ：ｏ、７３であり、レジス
ト７のエツチングが主に行なわれるが、二度目のドライ
エツチングでのそれは１：２で８ｉ０２のエツチングが
主に行なわれる。In the first dry etching, the etching speed ratio between the resist and the 8i02 film 4' was 1:0, 73, and the resist 7 was mainly etched, but in the second dry etching, it was 1:2. 8i02 etching is mainly performed.
第１図（ｇｌは、ゲート抵抗を低減させるための工程で
、同図（ｆ）のままで逆スバ、タリングをＡｒガスで行
ない、Ｗ５８ｉ３３の表面を若干側ることでＷ５８ｉ３
３の頭部の表面を清浄にし、同一スバ。Figure 1 (gl is a process for reducing gate resistance. Reverse stripping and taring are performed using Ar gas while maintaining the same shape as shown in figure (f), and the surface of W58i33 is slightly lateralized to reduce the gate resistance.
Clean the surface of the head in step 3 and use the same scrubber.
夕装置でＡｎの拡散及び反応のバリアとしてＴｉＮ膜ｓ
を５ｏｏＸ厚スバ、タリングにより被着し、さらに続け
てＡｕ９を同様に３０００Ｘ厚被着せしめられ、この基
板をアセトン液中に浸し、超音波洗浄するとゲート頭部
以外のＴｉＮｇ及びＡｕ９がり７トオフ法により除去さ
れ、ゲート頭部のみのＴｉＮ３とＡｕ ９が残る工程で
ある。A TiN film is used as a barrier for diffusion and reaction of An in the evening equipment.
The substrate was deposited with a thickness of 500X and talling, and then Au9 was similarly deposited with a thickness of 3000X. When this substrate was immersed in an acetone solution and ultrasonically cleaned, the TiNg and Au9 other than the gate head were removed by the 7-off method. In this process, TiN3 and Au 9 are removed only at the top of the gate.
この工程以外は従来の工程と同様にオーミックメタルで
あるＡｕＧｅ／Ｎｉ層を通常のリングラフィでＮ十層６
上に抵抗加熱蒸着しＨ２雰囲気中で′４２０℃１分間の
熱処理でオーミックアロイ層ｌＯを形成し、ソースとド
レインの電極形成を行なうと共にパ、シペーシ目ン膜と
してＣＶＤ５ｉ０２膜４”で表面を覆う（第１図（ｈ）
）。Other than this step, the AuGe/Ni layer, which is an ohmic metal, is formed in a N0 layer by normal phosphorography in the same way as in the conventional process.
An ohmic alloy layer 1O is formed by resistive heating evaporation and heat treatment at 420°C for 1 minute in an H2 atmosphere, and the source and drain electrodes are formed, and the surface is covered with a CVD 5i02 film 4'' as a spacer film. (Figure 1 (h)
).
（発明の効果）
このような製造方法で得られるＦＥＴは従来のＡｔ又は
Ｔ ｉＡｔゲートで作られるＦＥＴよりゲート長の均一
性もよく素子の歩留も向上させることができ、ソース抵
抗も減少し、高周波特性のよいＦＥＴを提供できる。又
ＩＣに適用したときも同様に歩留の向上が期待できる。(Effects of the invention) The FET obtained by this manufacturing method has better gate length uniformity than FETs made with conventional At or TiAt gates, can improve device yield, and has reduced source resistance. , it is possible to provide an FET with good high frequency characteristics. Furthermore, when applied to ICs, a similar improvement in yield can be expected.
第１図（ａ）〜（ｈ）は本発明の一実施例をその整造工
程順に示す素子断面図である。
ｌ・・・・・・Ｇ ａ 、Ａ ｓ基板、２・・・・・・
ｎ導伝型不純物層、３・・・・・・Ｗ５８ ｉ ３膜、
４，４’＃４“・・・・・・８ｉ０２膜、５・・・・・
・・・・ホトレジスト膜％ ６・・・・・・ｎ 導伝型
不純物層、７・・・・・・ホトレジスト膜、８・・・・
・・Ｔ ｉ Ｎ 膜％ ９・・・・・・Ａｕ１１１．Ｉ
Ｏ・・・・・・オーミックアロイ層。
（α）
（ｂ）
（Ｃ）
（’＝’）
第 ｌ 図
＜ｈ
（＆）FIGS. 1(a) to 1(h) are sectional views showing an embodiment of the present invention in the order of its preparation steps. l...G a , A s substrate, 2...
n conduction type impurity layer, 3...W58 i 3 film,
4,4'#4"...8i02 membrane, 5...
...Photoresist film% 6...n Conductive impurity layer, 7... Photoresist film, 8...
...T i N film% 9...Au111. I
O...Ohmic alloy layer. (α) (b) (C) ('=') Figure l <h (&)
Claims (1)
ーゲートを持つ電界効果トランジスタの製造において、
該基板の一表面側にトランジスタのチャンネルとなるｎ
型導伝層を形成する工程と、該表面側にゲート電極パタ
ーンの耐熱性金属を形成し、その上に気相成長法による
絶縁膜を被着する工程と、それに続くイオン注入により
ゲート幅より広い間隔で自動的に、将来高濃度ｎ型導伝
層となる領域に不純物イオンを前記絶縁膜を通して注入
する工程、高温で注入不純物を電気的に活性化したのち
、ホトレジスト膜を該絶縁膜上に塗布し、該ホトレジス
トの焼締めと同時にゲート部の突出部のホトレジスト厚
を減少させる工程と、リアクティブイオンエッチングを
施すことにより前記ゲート部の前記ホトレジスト及び前
記絶縁膜を除去したのち低抵抗金属を被着し、リフトオ
フ法によってゲート部以外の前記低抵抗金属を除去する
工程とを含むことを特徴とする化合物半導体装置の製造
方法。In the production of field effect transistors with metal Schottky gates using semi-insulating compound semiconductor substrates,
On one surface side of the substrate, there is an n
A process of forming a type conductive layer, a process of forming a heat-resistant metal for a gate electrode pattern on the surface side, and a process of depositing an insulating film on it by vapor phase growth, followed by ion implantation to increase the gate width. A process of automatically implanting impurity ions at wide intervals through the insulating film into regions that will become high-concentration n-type conductive layers in the future. After electrically activating the implanted impurities at high temperature, a photoresist film is placed on the insulating film. A step of reducing the thickness of the photoresist on the protruding portion of the gate portion at the same time as baking and tightening the photoresist, and removing the photoresist and the insulating film on the gate portion by performing reactive ion etching. 1. A method of manufacturing a compound semiconductor device, comprising the steps of: depositing a low-resistance metal on a portion other than a gate portion using a lift-off method;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13236484A JPS6112082A (en) | 1984-06-27 | 1984-06-27 | Manufacture of compound semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13236484A JPS6112082A (en) | 1984-06-27 | 1984-06-27 | Manufacture of compound semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6112082A true JPS6112082A (en) | 1986-01-20 |
Family
ID=15079637
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13236484A Pending JPS6112082A (en) | 1984-06-27 | 1984-06-27 | Manufacture of compound semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6112082A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS632803U (en) * | 1986-06-24 | 1988-01-09 | ||
| US10662785B2 (en) | 2012-09-21 | 2020-05-26 | Mitsubishi Hitachi Power Systems, Ltd. | Method of welding erosion resistance metallic material and turbine blade |
-
1984
- 1984-06-27 JP JP13236484A patent/JPS6112082A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS632803U (en) * | 1986-06-24 | 1988-01-09 | ||
| US10662785B2 (en) | 2012-09-21 | 2020-05-26 | Mitsubishi Hitachi Power Systems, Ltd. | Method of welding erosion resistance metallic material and turbine blade |
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