CN114171584A - Based on Ga2O3Heterojunction field effect transistor and preparation method thereof - Google Patents

Based on Ga2O3Heterojunction field effect transistor and preparation method thereof Download PDF

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CN114171584A
CN114171584A CN202111498547.5A CN202111498547A CN114171584A CN 114171584 A CN114171584 A CN 114171584A CN 202111498547 A CN202111498547 A CN 202111498547A CN 114171584 A CN114171584 A CN 114171584A
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epitaxial wafer
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beta
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周弘
王晨璐
燕庆龙
张进成
郝跃
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Xidian University
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
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Abstract

The invention discloses a Ga-based alloy2O3The heterojunction field effect transistor mainly solves the problems of low actual power figure of merit and large power loss of the existing gallium oxide-based device. It includes from bottom to top: a source electrode S, a substrate layer, a drift layer, a drain electrode and a gate electrode, wherein the substrate layer is 500 um-700 um thick and 1 x 1018～5×1018cm‑3N-type highly doped beta-Ga of2O3A material; the drift layer is 5-7 um thick and 1.5 × 1016～1×1017cm‑3N-type low doped beta-Ga of2O3A material; the N-type low-doped beta-Ga2O3The two ends of the drift layer are respectively provided with a P-type NiO layer which is low-doped with the N-type beta-Ga2O3The drift layer constitutes a hetero-PN junction. The invention improves the breakdown voltage of the device, increases the power figure of merit of the device, reduces the power loss of the device, and can be used for preparing a high-power enhanced gallium oxide device.

Description

Based on Ga2O3Heterojunction field effect transistor and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to Ga2O3The heterojunction field effect transistor can be used for preparing a vertical enhancement mode gallium oxide device.
Technical Field
Ga2O3Is an ultra-wide band gap semiconductor material with 4.6-4.9eV, has a theoretical breakdown electric field strength of about 8MV/cm and is close to 250cm2Electron mobility of/Vs and Baliga figure of merit of more than 3000, and high breakdown voltage and high conversion efficiency can be obtained at the same time. While Ga2O3The material can also be obtained by mature and low cost melting method to obtain high quality bulk substrate, thus Ga2O3The base device is regarded as a powerful competitor in the power device market and becomes a hot spot of research in recent years.
Since Ga is2O3The material has a size of as small as 0.28-0.33meAnd an electron affinity of up to 4.0eV, Ga2O3The material can realize N-type doping with ideal conductivity and electron mobility, and Ga is used at present2O310 can be achieved by doping atoms of Si, Ge, Sn, F, Cl, etc15-1019Effective N-type semiconductor of power, but Ga2O3P-type doping of materials is difficult to achieve and remains a focus of research. Ga2O3Ga of the material is due to its very large effective hole mass and the valence band at deep levels2O3It is very difficult to realize P-type doping with high mobility, and the absence of P-type doping limits Ga to a great extent2O3Development of devices. To alleviate this deficiency, research has found that P-type NiO material and N-type Ga can be used2O3The material forms a heterogeneous PN junction to improve the power merit value of the device, but the current heterogeneous PN junction Ga2O3The base device is basically a horizontal structure which reduces the reliability of the device due to the existence of interface states and does not have the characteristics of low cost, high reliability and low costCan fully exert Ga2O3The advantage of a power figure of merit of greater than 3000 increases the useless power loss of the device. While Ga is absent due to the absence of P-type material2O3The basic device mainly works in a depletion mode, the subsequent circuit design is complex, and the device cannot be ensured to be in a safe working mode.
Disclosure of Invention
The present invention aims to overcome the defects of the prior art and provide a Ga-based material2O3The heterojunction field effect transistor and the preparation method thereof are used for increasing the power figure of merit of the device and reducing the power loss of the device.
In order to achieve the purpose, the technical scheme of the invention is as follows:
1. based on Ga2O3The heterojunction field effect transistor and the preparation method thereof comprise the following steps from bottom to top: source electrode S, substrate layer, drift layer and drain, gate electrode, its characterized in that:
the substrate layer is 500-700 um thick and 1 × 1018～5×1018cm-3N-type highly doped beta-Ga of2O3A material;
the drift layer adopts a thickness of 5 um-7 um and a concentration of 1.5 multiplied by 1016～1×1017cm-3N-type low doped beta-Ga of2O3A material;
the N-type low-doped beta-Ga2O3The two ends of the drift layer are respectively provided with a P-type NiO layer which is low-doped with the N-type beta-Ga2O3The drift layer forms a heterogeneous PN junction so as to increase the power figure of merit of the device and reduce the power loss of the device.
Further, the thickness of the NiO layer is 1-1.5 um, and the concentration is 2 x 1017～5×1018cm-3。
Further, the gate electrode G is positioned at the upper part of the P-type NiO layer, and the drain electrode D is positioned between the gate electrodes G and is N-type low-doped beta-Ga2O3The upper part of (a).
2. Based on Ga2O3The method for manufacturing a Heterojunction Field Effect Transistor (HFET) comprises:
1) the thickness of the substrate is 500 um-700 um, the doping is 1 x 1018～5×1018cm-3The thickness of the drift layer is 5 um-7 um, and the concentration is 1.5 multiplied by 1016～1×1017cm-3Ga of (2)2O3Sequentially placing the epitaxial wafer into an acetone solution, an isopropanol solution and deionized water, respectively ultrasonically cleaning for 5min, and then blowing by using a nitrogen gun;
2) ga after washing2O3The back of the epitaxial wafer faces upwards, titanium with the thickness of 40 nm-70 nm and gold with the thickness of 80 nm-150 nm are sequentially deposited in an electron beam evaporation E-beam system, then the epitaxial wafer after electron beam evaporation is placed in an annealing furnace, and rapid annealing is carried out for 1min under the condition that the nitrogen flow rate is 3-5L/min and the temperature is 460-480 ℃, so that ohmic contact of a source electrode is formed;
3) annealing the Ga2O3Sequentially placing the epitaxial wafer into an acetone solution, an isopropanol solution and deionized water, respectively ultrasonically cleaning for 5min, and then blowing by using a nitrogen gun; then Ga is added2O3Photoetching the surface of the epitaxial wafer to form a drain electrode pattern;
4) post-lithographic Ga in E-beam evaporation2O3Depositing titanium with the thickness of 40 nm-70 nm and gold with the thickness of 80 nm-150 nm on the surface of the epitaxial wafer in sequence, performing ultrasonic cleaning in an acetone solution, an isopropanol solution and deionized water for 5min respectively to strip the drain metal, placing the drain metal into an annealing furnace, and performing rapid annealing for 1min under the conditions that the nitrogen flow rate is 3-5L/min and the temperature is 460-480 ℃ to form the ohmic contact of the drain.
5) In forming drain ohmic contact Ga2O3The surface of the epitaxial wafer is subjected to secondary photoetching to form a pattern to be etched, and the pattern is placed into an Inductively Coupled Plasma (ICP) system and BCl is utilized3Etching with Ar gas to a depth of 1-1.5 μm;
6) placing the etched epitaxial wafer into a magnetron sputtering sputter system, and carrying out Ar and O treatment at the radio frequency power of 150W2Bombarding the NiO target to form a P-type NiO coating on the etched surface of the NiO target in the atmosphere;
7) putting the epitaxial wafer with the P-type NiO coating film into an electron beam evaporation E-beam system to sequentially deposit nickel with the thickness of 40-80 nm and gold with the thickness of 80-150 nm so as to form a grid electrode;
8) depositing NiO and Ga after the grid metal2O3And respectively putting the epitaxial wafer into an acetone solution, an isopropanol solution and deionized water, and respectively carrying out ultrasonic cleaning for 15min for stripping to finish the manufacture of the device.
Compared with the prior art, the invention has the following advantages:
1. the invention adopts N-type Ga2O3The materials are used as a substrate and a drift layer, and the N-type Ga can be doped by introducing a P-type NiO material2O3A heterogeneous PN junction is formed, reverse electric leakage can be effectively restrained through the depletion effect of the PN junction, and therefore the breakdown voltage of the device is improved, the power excellent value of the device is greatly increased, and the power loss of the device is reduced.
2. The invention constructs a Ga-based2O3The enhancement mode is realized by the enhancement type field effect transistor made of the material and by turning off the device without bias voltage through a heterogeneous PN junction, and the subsequent circuit design is simplified.
3. In the invention, Ga is added in the preparation process2O3The three process steps of etching, NiO coating and grid metal deposition are placed after one-time photoetching, compared with the experimental process of the traditional one-time photoetching process, the experimental efficiency is greatly improved, meanwhile, the photoetching times are reduced, the exposure time of the device is shortened, the quantity of introduced impurities is reduced, and the reliability of the device is effectively improved.
Drawings
FIG. 1 is a schematic diagram of a heterojunction field effect transistor structure according to the present invention.
FIG. 2 is a schematic diagram of an implementation process for fabricating a heterojunction field effect transistor according to the present invention.
Detailed Description
The heterojunction field effect transistor structure and the preparation process of the present invention are further described in detail below with reference to the accompanying drawings.
Referring to fig. 1, the heterojunction field effect transistor of the present invention comprises: a P-type NiO layer, a substrate layer, a drift layer,A source electrode S, a drain electrode D, and a gate electrode G. Wherein, the substrate layer is 500 um-700 um thick and 1 × 1018～5×1018cm-3N-type highly doped beta-Ga of2O3A material; the drift layer is 5-7 um thick and 1.5 × 1016～1×1017cm-3N-type low doped beta-Ga of2O3Material of N-type highly doped beta-Ga2O3A layer above; the thickness of the P-type NiO layer is 1 um-1.5 um, and the concentration is 2 multiplied by 1017～5×1018cm-3Which is located in N-type low doped beta-Ga2O3Both ends of the upper part of the drift layer, and beta-Ga2O3The drift layer forms a heterogeneous PN junction so as to improve the breakdown voltage and increase the power optimal value; the gate electrode G is positioned on the upper part of the P-type NiO layer; n-type low-doped beta-Ga with drain electrode D positioned between gate electrodes G2O3An upper portion of the drift layer; the source electrode S is positioned in N type highly doped beta-Ga2O3A lower portion of the substrate layer.
Referring to fig. 2, the method of fabricating a heterojunction field effect transistor of the present invention gives the following three examples:
example 1 preparation of N-type beta-Ga2O3The substrate layer has a thickness of 500um and a doping of 5 × 1018cm-3N type beta-Ga2O3The drift layer has a thickness of 5 μm and a doping of 1.5X 1016cm-3And P-type NiO with the thickness of 1 μm and the doping of 2 × 1017cm-3A heterojunction field effect transistor of (1).
Step 1: cleaning of beta-Ga2O3And (c) an epitaxial wafer, as shown in fig. 2 (a).
The thickness of the substrate layer is 500um and the doping is 5 multiplied by 1018cm-3And a drift layer thickness of 5 μm and a doping concentration of 1.5X 1016cm-3Of beta-Ga2O3And (3) carrying out ultrasonic cleaning on the homoepitaxial wafer in an acetone solution, absolute ethyl alcohol and deionized water for 5min respectively in sequence, and then carrying out blow-drying by using nitrogen.
Step 2: and manufacturing a source ohmic electrode.
2.1) Ga after washing2O3Putting electron beams into the epitaxial wafer with the back side facing upwardsIn the evaporation E-beam system, the electron gun voltage is 7.5kV and the pressure is 1X 10-6Sequentially depositing Ti with the thickness of 60nm and Au with the thickness of 120nm under the condition of Pa;
2.2) putting the epitaxial wafer evaporated by the electron beam into an annealing furnace, and carrying out rapid annealing for 1min under the condition that the nitrogen flow rate is 3L/min and the temperature is 470 ℃ to form ohmic contact of a source electrode.
And step 3: cleaning of beta-Ga2O3And (c) an epitaxial wafer, as shown in fig. 2 (b).
Annealing the Ga2O3And ultrasonic cleaning the epitaxial wafer in an acetone solution, an isopropanol solution and deionized water for 5min respectively, and blow-drying by using a nitrogen gun.
And 4, step 4: and manufacturing a drain electrode ohmic electrode.
4.1) in Ga2O3Performing primary photoetching on the surface of the epitaxial wafer to form a drain electrode pattern, as shown in FIG. 2 (c);
4.2) etching the post-Ga2O3The epitaxial wafer was placed in an electron beam evaporation E-beam system at an electron gun voltage of 7.5kV and a pressure of 1X 10-6Sequentially depositing Ti with the thickness of 60nm and Au with the thickness of 120nm under the condition of Pa, wherein the growth rates of the Ti and the Au are respectively 0.3nm/s and 0.3nm/s, as shown in a figure 2 (d);
4.3) Ga grown with Ti and Au2O3Sequentially placing the epitaxial wafer in an acetone solution, an isopropanol solution and deionized water, and carrying out ultrasonic cleaning for 5min respectively to strip the drain metal;
4.4) placing the epitaxial wafer with the stripped drain metal into an annealing furnace, and carrying out rapid annealing for 1min under the condition that the nitrogen flow rate is 3L/min and the temperature is 470 ℃ to form a drain ohmic contact, as shown in figure 2 (e).
And 5: etching of beta-Ga2O3And (7) an epitaxial wafer.
5.1) Ga in forming ohmic contact of drain2O3Performing secondary photoetching on the surface of the epitaxial wafer to form a gate pattern, as shown in FIG. 2 (f);
5.2) Ga to be patterned into a gate electrode2O3Placing the epitaxial wafer into an Inductively Coupled Plasma (ICP) system, and setting the pressure of a reaction chamber to be 8mTorr and BCl3With Ar gasThe proportion is 2:1, the RF power is 150W, and the gate pattern is etched to a depth of 1 μm, as shown in FIG. 2 (g).
Step 6: NiO grows by sputtering.
Putting the etched sample wafer into a magnetron sputtering sputter system, and arranging Ar and O2The flow rate ratio is 5: 1. the pressure of the reaction chamber is 0.5Pa, the radio frequency power is 150W, and the NiO target is bombarded to carry out NiO coating, namely the NiO coating is carried out on the etched surface with the thickness of 1 mu m and the doping concentration of 2 multiplied by 1017cm-3FIG. 2(h) shows the P-type NiO plating film.
And 7: and manufacturing a grid electrode.
7.1) putting the coated sample wafer into an electron beam evaporation E-beam system, wherein the voltage of an electron gun is 7.5kV, and the pressure is 1 multiplied by 10-6Setting the growth rates of Ni and Au to be 0.3 and 0.3nm/s respectively under the condition of Pa, and sequentially depositing Ni with the thickness of 60nm and Au with the thickness of 120nm on the surface of the sample wafer after film plating, as shown in figure 2 (i);
7.2) placing the sample wafer deposited with Ni and Au in an acetone solution, an isopropanol solution and deionized water in sequence, and carrying out ultrasonic cleaning for 5min respectively to strip the gate metal, as shown in figure 2(j), thereby completing the preparation of the device.
Example 2 preparation of N-type beta-Ga2O3The substrate layer thickness is 600um and the doping is 2X 1018cm-3The drift layer thickness is 7 μm and the doping is 1.5X 1016cm-3And P-type NiO with a thickness of 1.5 μm and a doping of 5 × 1017cm-3A heterojunction field effect transistor of (1).
The method comprises the following steps: n-type beta-Ga2O3Homoepitaxial wafer cleaning
The substrate layer thickness was chosen to be 600um and the doping 2 x 1018cm-3And a drift layer thickness of 7 μm and a doping concentration of 1.5X 1016cm-3Of the N-type beta-Ga2O3The homoepitaxial wafer, as shown in fig. 2(a), was sequentially subjected to ultrasonic cleaning in acetone solution, absolute ethanol, and deionized water for 5min, and then blown dry with nitrogen.
Step two: and manufacturing a source ohmic electrode.
Ga after washing2O3The epitaxial wafer is placed into an electron beam evaporation E-beam system with the back side facing upwards, and the voltage of an electron gun is 7.5kV, and the pressure is 2 multiplied by 10-6Sequentially depositing Ti with the thickness of 40nm and Au with the thickness of 150nm under the condition of Pa; and then the silicon substrate is placed into an annealing furnace, and rapid annealing is carried out for 1min under the condition that the nitrogen flow rate is 4L/min and the temperature is 475 ℃, so that ohmic contact of a source electrode is formed.
Step three: cleaning of beta-Ga2O3And (c) an epitaxial wafer, as shown in fig. 2 (b).
This step is the same as step 3 of example 1.
Step four: and manufacturing a drain electrode ohmic electrode.
In Ga2O3Performing primary photoetching on the surface of the epitaxial wafer to form a drain electrode pattern, as shown in FIG. 2 (c);
then the photoetched epitaxial wafer is put into an electron beam evaporation E-beam system, and the voltage of an electron gun is set to be 7.5kV, and the pressure is set to be 2 multiplied by 10-6Pa, Ti and Au growth rate of 0.2 and 0.2nm/s, depositing Ti with thickness of 40nm and Au with thickness of 150nm on the drain electrode pattern in sequence, as shown in figure 2(d), and placing the drain electrode pattern in acetone solution, isopropanol solution and deionized water in sequence to perform ultrasonic cleaning for 5min respectively for stripping the drain electrode metal;
then the stripped epitaxial wafer is put into an annealing furnace, and rapid annealing is carried out for 1min under the condition that the nitrogen flow rate is 4L/min and the temperature is 475 ℃, so as to form the drain electrode ohmic contact, as shown in figure 2(e)
Step five: etching of beta-Ga2O3And (7) an epitaxial wafer.
In Ga2O3Performing secondary photoetching on the surface of the epitaxial wafer to form a gate pattern, as shown in FIG. 2 (f);
then putting the sample with the drain electrode pattern into an Inductively Coupled Plasma (ICP) system, wherein the pressure of the reaction chamber is 10mTorr, BCl3And Ar gas ratio 3: 1, etching the gate pattern with a depth of 1.5 μm under the condition of 150W of RF power, as shown in FIG. 2 (g).
Step six: NiO grows by sputtering.
Placing the etched epitaxial wafer into a magnetron sputtering sputter system, and arranging Ar and O2Is 5: 2. the technological conditions that the pressure of the reaction chamber is 0.6Pa and the radio frequency power is 150W are adopted, the NiO target material is bombarded, the thickness of the NiO target material is 1.5 mu m, the doping concentration is 5 multiplied by 1017cm-3FIG. 2(h) shows the P-type NiO plating film.
Step seven: and manufacturing a grid electrode.
7.1) putting the coated sample wafer into an electron beam evaporation E-beam system, wherein the voltage of an electron gun is 7.5kV, and the pressure is 2 multiplied by 10-6Sequentially depositing Ni with the thickness of 40nm and Au with the thickness of 150nm on the NiO layer under the condition of Pa, wherein the growth rates of the Ni and the Au are respectively 0.2 and 0.2nm/s, and shown in a figure 2 (i);
7.2) carrying out ultrasonic cleaning on the sample wafer subjected to metal evaporation in acetone solution, isopropanol solution and deionized water for 5min respectively to carry out grid metal stripping, as shown in figure 2(j), and finishing the preparation of the device.
Example 3 production of N-type beta-Ga2O3The substrate layer has a thickness of 700 μm and a doping of 1X 1018cm-3N type beta-Ga2O3The drift layer thickness is 5 μm and the doping is 1 × 1017cm-3And P-type NiO with a thickness of 1 μm and a doping of 5 × 1018cm-3A heterojunction field effect transistor of (1).
Step A: cleaning of beta-Ga2O3And (c) an epitaxial wafer, as shown in fig. 2 (a).
The substrate layer thickness was chosen to be 700 μm and the doping 1X 1018cm-3And a drift layer thickness of 5 μm and a doping concentration of 1 × 1017cm-3Of the N-type beta-Ga2O3And (3) carrying out ultrasonic cleaning on the homoepitaxial wafer in an acetone solution, absolute ethyl alcohol and deionized water for 5min respectively in sequence, and then carrying out blow-drying by using nitrogen.
And B: and manufacturing a source ohmic electrode.
B1) Ga after washing2O3The back of the epitaxial wafer faces upwards, and the epitaxial wafer is placed into an electron beam evaporation E-beam system, and the voltage of an electron gun is set to be 7.5kV, and the pressure is set to be 5 multiplied by 10-6Pa, sequentially depositing Ti with the thickness of 70nm and Au with the thickness of 80nm on the back of the epitaxial wafer;
B2) and (3) putting the sample wafer subjected to electron beam evaporation into an annealing furnace, and performing rapid annealing for 1min at the temperature of 480 ℃ under the condition of the nitrogen flow rate of 5L/min to form ohmic contact of the source electrode.
And C: cleaning of beta-Ga2O3Swatch, as in fig. 2 (b).
This step is the same as step 3 of example 1.
Step D: and manufacturing a drain electrode ohmic electrode.
D1) In Ga2O3Performing one-time photoetching on the surface of the sample wafer to form a drain electrode pattern, as shown in FIG. 2 (c);
D2) placing the sample wafer with the drain electrode pattern into an electron beam evaporation E-beam system, and controlling the electron gun voltage to be 7.5kV and the pressure to be 5 × 10-6Controlling the growth rates of Ti and Au to be 0.1 and 0.1nm/s respectively under the process condition of Pa, and sequentially depositing Ti with the thickness of 70nm and Au with the thickness of 80nm on the drain electrode pattern, as shown in figure 2 (d);
D3) sequentially placing the sample wafer subjected to electron beam evaporation into an acetone solution, an isopropanol solution and deionized water, and carrying out ultrasonic cleaning for 5min respectively to strip the drain metal;
D4) placing the stripped sample wafer into an annealing furnace, performing rapid annealing at 480 deg.C under nitrogen flow rate of 5L/min to form drain ohmic contact, as shown in FIG. 2(e)
Step E: etching of beta-Ga2O3And (7) an epitaxial wafer.
E1) Ga in forming drain ohmic contact2O3Carrying out secondary photoetching on the surface of the sample wafer to form a grid pattern, as shown in figure 2 (f);
E2) ga to be patterned into gate electrode2O3Placing the sample into inductively coupled plasma ICP system, and using BCl3Etching with Ar gas under 12mTorr, BCl pressure in the reaction chamber3And Ar gas ratio of 4:1, etching the gate pattern with a depth of 1 μm under the condition of 150W of RF power, as shown in FIG. 2 (g).
Step F: NiO grows by sputtering.
Putting the etched sample wafer into a magnetron sputtering sputter system, and arranging Ar and O2The flow rate ratio is 5: 4. the pressure of the reaction chamber is 0.8Pa, and the radio frequency power is 150WThe process conditions are that the thickness of the etched surface is 1 mu m, the doping concentration is 5 multiplied by 1018cm-3FIG. 2(h) shows the P-type NiO plating film.
Step G: and manufacturing a grid electrode.
G1) Putting the NiO-coated sample wafer into an electron beam evaporation E-beam system, wherein the voltage of an electron gun is 7.5kV, and the pressure is 5 multiplied by 10-6Controlling the growth rates of Ni and Au to be 0.1 and 0.1nm/s respectively under the condition of Pa, and sequentially depositing Ni with the thickness of 80nm and Au with the thickness of 80nm on the surface of the NiO plating film, as shown in figure 2 (i);
G2) and (5) sequentially placing the sample wafer subjected to metal evaporation into an acetone solution, an isopropanol solution and deionized water, and carrying out ultrasonic cleaning for 5min respectively to strip the gate metal, as shown in figure 2(j), thereby completing the preparation of the device.
The above are only three embodiments of the present invention, and do not limit the present invention in any way. It will be apparent to persons skilled in the relevant art that various modifications and changes in form and detail can be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (7)

1. Based on Ga2O3The heterojunction field effect transistor of (1) comprises from bottom to top: source electrode S, substrate layer, drift layer and drain, gate electrode, its characterized in that:
the substrate layer is 500-700 um thick and 1 × 1018～5×1018cm-3N-type highly doped beta-Ga of2O3A material;
the drift layer adopts a thickness of 5 um-7 um and a concentration of 1.5 multiplied by 1016～1×1017cm-3N-type low doped beta-Ga of2O3A material;
the N-type low-doped beta-Ga2O3The two ends of the drift layer are respectively provided with a P-type NiO layer which is low-doped with the N-type beta-Ga2O3The drift layer forms a heterogeneous PN junction to increase the power figure of merit of the device and reduce the power loss of the device。
2. The field effect transistor of claim 1, wherein: the thickness of the NiO layer is 1-1.5 um, and the concentration is 2 multiplied by 1017～5×1018cm-3。
3. The field effect transistor of claim 1, wherein: the gate electrode G is positioned at the upper part of the P-type NiO layer, and the drain electrode D is positioned between the gate electrodes G2O3The upper part of (a).
4. Based on Ga2O3The method for manufacturing a Heterojunction Field Effect Transistor (HFET) comprises the following steps:
1) the thickness of the substrate is 500 um-700 um, the doping is 1 x 1018～5×1018cm-3The thickness of the drift layer is 5 um-7 um, and the concentration is 1.5 multiplied by 1016～1×1017cm-3Ga of (2)2O3Sequentially placing the epitaxial wafer into an acetone solution, an isopropanol solution and deionized water, respectively ultrasonically cleaning for 5min, and then blowing by using a nitrogen gun;
2) ga after washing2O3The back of the epitaxial wafer faces upwards, titanium with the thickness of 40 nm-70 nm and gold with the thickness of 80 nm-150 nm are sequentially deposited in an electron beam evaporation E-beam system, then the epitaxial wafer after electron beam evaporation is placed in an annealing furnace, and rapid annealing is carried out for 1min under the condition that the nitrogen flow rate is 3-5L/min and the temperature is 470-480 ℃, so that ohmic contact of a source electrode is formed;
3) annealing the Ga2O3Sequentially placing the epitaxial wafer into an acetone solution, an isopropanol solution and deionized water, respectively ultrasonically cleaning for 5min, and then blowing by using a nitrogen gun; then Ga is added2O3Photoetching the surface of the epitaxial wafer to form a drain electrode pattern;
4) post-lithographic Ga in E-beam evaporation2O3Depositing titanium with the thickness of 40 nm-70 nm and gold with the thickness of 80 nm-150 nm on the surface of the epitaxial wafer in sequence, and then respectively placing the titanium and the gold in acetone solution, isopropanol solution and deionized waterAnd (3) carrying out ultrasonic cleaning for 5min to strip the drain metal, then placing the drain metal into an annealing furnace, and carrying out rapid annealing for 1min under the conditions that the nitrogen flow rate is 3-5L/min and the temperature is 470-480 ℃ to form the ohmic contact of the drain.
5) In forming drain ohmic contact Ga2O3The surface of the epitaxial wafer is subjected to secondary photoetching to form a pattern to be etched, and the pattern is placed into an Inductively Coupled Plasma (ICP) system and BCl is utilized3Etching with Ar gas to a depth of 1-1.5 μm;
6) placing the etched epitaxial wafer into a magnetron sputtering sputter system, and carrying out Ar and O treatment at the radio frequency power of 150W2Bombarding the NiO target to form a P-type NiO coating on the etched surface of the NiO target in the atmosphere;
7) putting the epitaxial wafer with the P-type NiO coating film into an electron beam evaporation E-beam system to sequentially deposit nickel with the thickness of 40-80 nm and gold with the thickness of 80-150 nm so as to form a grid electrode;
8) depositing NiO and Ga after the grid metal2O3And respectively putting the epitaxial wafer into an acetone solution, an isopropanol solution and deionized water, and respectively carrying out ultrasonic cleaning for 15min for stripping to finish the manufacture of the device.
5. The method according to claim 4, wherein the Ga is carried out in (5) by using an Inductively Coupled Plasma (ICP) system2O3Etching, wherein the process conditions are as follows:
the pressure intensity of the reaction chamber is 8 mTorr-12 mTorr;
the gas in the reaction chamber is BCl3And Ar;
BCl3the flow rate ratio of Ar to Ar is 2: 1-4: 1;
the RF source power was 150W.
6. The method of claim 4, wherein the NiO coating is performed in a magnetron sputtering sputter system in (6) under the following process conditions:
the pressure intensity of the reaction chamber is 0.5Pa to 0.8 Pa;
the gas in the reaction chamber is Ar or O2、CDA；
Ar and O2The gas flow rate ratio is 5: 1-5: 4;
the RF source power was 150W.
7. The method according to claim 4, wherein the metal evaporation is performed in the E-beam system of electron beam evaporation in (2), (4) and (7) under the following process conditions:
the voltage of the electron gun is 7.5 kV;
the pressure in the reaction cavity is 1 x 10-6～5×10-6Pa。
CN202111498547.5A 2021-12-09 2021-12-09 Based on Ga2O3Heterojunction field effect transistor and preparation method thereof Pending CN114171584A (en)

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