JPS61115236U - - Google Patents
Info
- Publication number
- JPS61115236U JPS61115236U JP20080984U JP20080984U JPS61115236U JP S61115236 U JPS61115236 U JP S61115236U JP 20080984 U JP20080984 U JP 20080984U JP 20080984 U JP20080984 U JP 20080984U JP S61115236 U JPS61115236 U JP S61115236U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- power source
- main power
- numerical data
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
Landscapes
- Power Sources (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図は本考案の電子機器の構成を示すブロツ
ク図、第２図ａ，ｂ，ｃはＲＡＭの構成を示す図
、第３図は第１図の動作を説明するフローチヤー
ト図である。
１…中央処理回路、２…ＲＯＭ、３…キーボー
ド、４…ＲＡＭ、５…表示器、６…送受信回路、
７…主電源、８…補助電源。
FIG. 1 is a block diagram showing the configuration of the electronic device of the present invention, FIGS. 2a, b, and c are diagrams showing the configuration of the RAM, and FIG. 3 is a flowchart explaining the operation of FIG. 1. 1...Central processing circuit, 2...ROM, 3...keyboard, 4...RAM, 5...display, 6...transmission/reception circuit,
7...Main power supply, 8...Auxiliary power supply.
Claims (1)
する補助電源と、該補助電源によりバツヤアツプ
され所定領域に不特定の数値データが書き込まれ
る揮発性メモリと、該メモリに０〜９の数値デー
タを入力する入力手段と、主電源が入ると、前記
メモリの数値データを記憶している領域のデータ
を読出し、読出したデータが０〜９の何れかに該
当するか否かを判定する判定手段を具備し、この
判定結果により前記メモリの内容が壊われている
か否かを確認するメモリチエツク機能を持つこと
を特徴とする電子機器。 A main power source, an auxiliary power source that backs up when the main power is off, a volatile memory that is backed up by the auxiliary power source and unspecified numerical data is written in a predetermined area, and numerical data from 0 to 9 is input into the memory. and determining means for reading out data in the area storing numerical data in the memory and determining whether or not the read data corresponds to any one of 0 to 9 when the main power is turned on. An electronic device characterized in that it has a memory check function for checking whether or not the contents of the memory are corrupted based on the determination result.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20080984U JPS61115236U (en) | 1984-12-28 | 1984-12-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP20080984U JPS61115236U (en) | 1984-12-28 | 1984-12-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61115236U true JPS61115236U (en) | 1986-07-21 |
Family
ID=30762002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP20080984U Pending JPS61115236U (en) | 1984-12-28 | 1984-12-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61115236U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0187451U (en) * | 1987-11-30 | 1989-06-09 |
-
1984
- 1984-12-28 JP JP20080984U patent/JPS61115236U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0187451U (en) * | 1987-11-30 | 1989-06-09 |
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