JPH026341U - - Google Patents
Info
- Publication number
- JPH026341U JPH026341U JP8318988U JP8318988U JPH026341U JP H026341 U JPH026341 U JP H026341U JP 8318988 U JP8318988 U JP 8318988U JP 8318988 U JP8318988 U JP 8318988U JP H026341 U JPH026341 U JP H026341U
- Authority
- JP
- Japan
- Prior art keywords
- instruction
- microprocessor
- main memory
- signal
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
Description
第1図は本考案の基本的な構成を示すブロツク
図、第2図は本考案の一実施例を示すブロツク図
、第3図は動作の一例を示すタイムチヤートであ
る。
1……マイクロプロセツサ、2……主メモリ、
3……未定義命令判定手段、4……命令格納領域
アクセス判定手段、5……停止信号発生手段。
FIG. 1 is a block diagram showing the basic configuration of the present invention, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a time chart showing an example of the operation. 1...Microprocessor, 2...Main memory,
3... Undefined instruction determining means, 4... Instruction storage area access determining means, 5... Stop signal generating means.
Claims (1)
サが実行する命令を記憶しておく主メモリとから
なるマイクロプロセツサ装置において、 前記主メモリから読み出された命令コードを入
力し当該命令があらかじめ定義された命令である
かどうか判定する末定義命令判定手段と、 前記主メモリへのアドレスが命令を格納した領
域をアクセスするものであるかどうか判定する命
令格納領域アクセス判定手段と、 前記未定義命令判定手段からの信号と、前記命
令格納領域アクセス判定手段からの信号とを入力
し、マイクロプロセツサからのアドレスが命令を
格納した領域をアクセスするものであつて、主メ
モリから読み出された命令があらかじめ定義され
た命令でない場合前記マイクロプロセツサの動作
を停止させる信号を出力する停止信号出力手段と
を設けたことを特徴とするマイクロプロセツサ装
置。[Claims for Utility Model Registration] In a microprocessor device consisting of a microprocessor and a main memory for storing instructions to be executed by the microprocessor, an instruction code read from the main memory is input. undefined instruction determining means for determining whether the instruction is a predefined instruction; and instruction storage area access determining means for determining whether the address to the main memory accesses an area in which an instruction is stored. , a signal from the undefined instruction determination means and a signal from the instruction storage area access determination means are input, and the address from the microprocessor accesses an area storing an instruction, and the address from the main memory is A microprocessor device comprising stop signal output means for outputting a signal to stop the operation of the microprocessor if the read instruction is not a predefined instruction.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8318988U JPH026341U (en) | 1988-06-23 | 1988-06-23 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8318988U JPH026341U (en) | 1988-06-23 | 1988-06-23 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH026341U true JPH026341U (en) | 1990-01-17 |
Family
ID=31307915
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8318988U Pending JPH026341U (en) | 1988-06-23 | 1988-06-23 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH026341U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102181715B1 (en) * | 2019-08-01 | 2020-11-23 | 한상교 | Handling method of undefined instruction exception for microprocessor, and microprocessor comprising the handling method of undefined instruction exception for microprocessor |
-
1988
- 1988-06-23 JP JP8318988U patent/JPH026341U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR102181715B1 (en) * | 2019-08-01 | 2020-11-23 | 한상교 | Handling method of undefined instruction exception for microprocessor, and microprocessor comprising the handling method of undefined instruction exception for microprocessor |