JPS61112362A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS61112362A JPS61112362A JP59233105A JP23310584A JPS61112362A JP S61112362 A JPS61112362 A JP S61112362A JP 59233105 A JP59233105 A JP 59233105A JP 23310584 A JP23310584 A JP 23310584A JP S61112362 A JPS61112362 A JP S61112362A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- semiconductor
- gallium arsenide
- insulating film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、半導体チップの実装技術に係り、特に、シリ
コン（Ｓｉ）集積回路チップとガリウムヒ素（ＱａＡｓ
）集積回路チップを混在して実装する場合に適用して有
効な技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to semiconductor chip packaging technology, and in particular to silicon (Si) integrated circuit chips and gallium arsenide (QAAs) packaging technology.
) This relates to a technique that is effective when applied to the case where integrated circuit chips are mixed and mounted.
シリコンチップのマルチチップ実装は１例えば、第３図
に示すように、パッケージ基板１の上にシリコンからな
る半導体チップ塔載基板（以下、マザーチップという）
２を接着し、その上に複数のシリコンチップ７をフリッ
プチップ方式の突起な極６を介して実装し、各シリコン
チップ間を配線３により接続し、ボンディングワイヤ５
により外部リード４に接続している。８はシリコン酸化
膜である。For example, as shown in FIG. 3, multi-chip mounting of silicon chips is performed by mounting a silicon semiconductor chip on a package substrate 1 (hereinafter referred to as a mother chip).
2 is bonded, a plurality of silicon chips 7 are mounted thereon via protruding poles 6 using a flip-chip method, each silicon chip is connected by a wiring 3, and a bonding wire 5 is bonded.
It is connected to the external lead 4 by. 8 is a silicon oxide film.
また、ガリウムヒ素チップを実装する場合は。Also, if you want to implement a gallium arsenide chip.
前記シリコンチップ実装方式のマザーチップをガリウム
ヒ素チップで形成し、その他の手法は全く同じ手段で実
装される。The mother chip of the silicon chip mounting method is formed of a gallium arsenide chip, and the other methods are the same.
しかしながら、シリコンチップとガリウムヒ素チップを
混在して実装する場合には、シリコン基板とガリウムヒ
素チップの熱膨張率が異なるため周囲温度が変化した場
合、突起電極６にクラックが生しる等の問題があること
を１本発明者は見い出した。However, when mounting silicon chips and gallium arsenide chips together, problems such as cracks occurring in the protruding electrodes 6 occur when the ambient temperature changes because the thermal expansion coefficients of the silicon substrate and gallium arsenide chips are different. The inventor has found that there is.
なお、階層構造を利用したシリコン・オン・シリコン方
式でシリコン基板の上にシリコンチップを実装する技術
は、例えば１日経マグロウヒル社発行、「日経エレクト
ロニクスＪ、１９８４年６月１１日号、ｎｏ、２．Ｐ１
３６に記載されている。The technology for mounting silicon chips on a silicon substrate using a silicon-on-silicon method using a hierarchical structure is described, for example, in Nikkei Electronics J, June 11, 1984, no. 2, published by Nikkei McGraw-Hill. .P1
It is described in 36.
本発明の目的は、シリコンチップとガリウムヒ素チップ
と混在して塔載したマルチチップ型半導体装置の信頼性
を向上させることが可能な技術を提供することにある。An object of the present invention is to provide a technique that can improve the reliability of a multi-chip semiconductor device in which silicon chips and gallium arsenide chips are mixedly mounted.
本発明の前記ならびにその他の目的と新規な特徴は、本
明！Ｉ書の記述及び添付図面によって明らかになるであ
ろう。The above and other objects and novel features of the present invention are the present invention! This will become clear from the description in Book I and the attached drawings.
本願において開示される発明のうち、代表的なものの概
要を説明すれば、下記のとおりである。Outline of typical inventions disclosed in this application is as follows.
すなわち、配線を設けた半導体チップ塔載基板に複数個
の半導体チップを塔載したマルチチップ型半導体装置に
おいて、前記複数個の半導体チップのうち少なくとも一
個は異なる材質の半導体チップとし、前記半導体チップ
塔載基板上に異なる材質の半導体チップの熱膨張率と略
同一又はそれに近い熱膨張率を有する絶縁膜を選択的に
設け。That is, in a multi-chip semiconductor device in which a plurality of semiconductor chips are mounted on a semiconductor chip mounting substrate provided with wiring, at least one of the plurality of semiconductor chips is a semiconductor chip made of a different material, and the semiconductor chip tower is An insulating film having a thermal expansion coefficient substantially the same as or close to that of a semiconductor chip made of a different material is selectively provided on a mounting substrate.
該絶縁膜の上に異な材質の半導体チップを塔載すること
により、該半導体装置の信頼性を向上させたものである
。 １゛（以
下、本発明の構成について、実施例とともに説明する。By mounting semiconductor chips made of different materials on the insulating film, the reliability of the semiconductor device is improved. 1 (Hereinafter, the structure of the present invention will be explained along with examples.
なお、全回において、同一の機能を有するものは同一の
符号を付け、その繰り返しの説明は省略する。In addition, in all the episodes, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.
第１図及び第２図は、本発明をマルチチップ型半導体装
置に適用した一実施例の構成を説明するための図であり
、第１図は、そのマルチチップ半導体装置の平面図、第
２図は、第１図のｎ−ｎ切断線における断面図である。1 and 2 are diagrams for explaining the configuration of an embodiment in which the present invention is applied to a multi-chip semiconductor device, and FIG. 1 is a plan view of the multi-chip semiconductor device, and FIG. The figure is a sectional view taken along the line nn in FIG. 1.
第１図及び第２図において、９はガリウムヒ素チップで
あり、例えば、１〜６キロビツトｃＫｂｉしコのメモリ
として用いる。シリコンチップ７は、例えば、 ５ｏｏ
ｏ〜１００００ゲートの大規模論理回路として用いる。In FIGS. 1 and 2, reference numeral 9 denotes a gallium arsenide chip, which is used as, for example, a 1 to 6 kilobit cKbi memory. The silicon chip 7 is, for example, 5oo
It is used as a large-scale logic circuit with 0 to 10,000 gates.
１０はガリウムヒ素チップ９の熱膨張率と略同一又はそ
れに近い熱膨張率を有す絶縁膜であり１例えば、ガリウ
ムヒ素のエピタキシャル層又は窒化アルミニウム（Ａ
Ｑ Ｎ）を用いる。Reference numeral 10 denotes an insulating film having a coefficient of thermal expansion that is substantially the same as or close to that of the gallium arsenide chip 9;
QN) is used.
この絶縁膜１０の膜厚は突起電極６に直接ストレスを加
えない程度の厚さであり、この厚さはシリコンマザチッ
プの厚さによって変ってくる。The thickness of this insulating film 10 is such that it does not directly apply stress to the protruding electrodes 6, and this thickness varies depending on the thickness of the silicon mother chip.
ここで、シリコンチップ７及びガリウムヒ素チップ９の
一般的な特性を以下に述べる。Here, general characteristics of the silicon chip 7 and the gallium arsenide chip 9 will be described below.
（１）シリコンチップ （イ）バイポーラ型 利点 （ａ）歩留が良い。(1) Silicon chip (b) Bipolar type Advantages (a) Good yield.
（ｂ）高速度である。(b) High speed.
（ｃ）外部装置への駆動能力が大きい。(c) Large driving capacity for external devices.
（ｄ）集積度が中程度ある。(d) The degree of integration is moderate.
（ロ）ＭＯＳ型 利点 （ａ）集積度が最大である。(b) MOS type Advantages (a) Maximum degree of integration.
（ｂ）歩留が最大である。(b) Yield is maximum.
問題点 （ａ）外部装置への駆動能力が小さい。Problems (a) The driving capacity for external devices is small.
（ｂ）低速度である。(b) It is slow.
（２）ガリウムヒ素チップ （イ）バイポーラ型及びＭＥＳ型 利点 （ａ）超高速度である 問題点 （ａ）歩留が悪い。(2) Gallium arsenide chip (a) Bipolar type and MES type Advantages (a) Ultra-high speed Problems (a) Yield is poor.
本実施例のマルチチップ型半導体装置は、前記ガリウム
ヒ素チップ及びシリコンチップの特性の利点を生かして
、マルチチップ型半導体装置の高速度の動作をさせたい
部分にはガリウムヒ素チップを用い、大集積度を必要と
する部分にはシリコンチップを用いたものであり、シリ
コンマザーチップ２上に、前記ガリウムヒ素チップ９の
熱膨張率と略同−の熱膨張率を有する材質の絶縁膜１０
を選択的に設け、該絶縁膜１０の上にガリウムヒ素チッ
プ９を塔載することにより、信頼度を向上させたもので
ある。The multi-chip semiconductor device of this embodiment takes advantage of the characteristics of the gallium arsenide chip and silicon chip, uses gallium arsenide chips in the parts of the multi-chip semiconductor device where high-speed operation is desired, and is highly integrated. A silicon chip is used for the portion that requires high temperature, and an insulating film 10 made of a material having a coefficient of thermal expansion approximately the same as that of the gallium arsenide chip 9 is disposed on the silicon mother chip 2.
By selectively providing the insulating film 10 and mounting the gallium arsenide chip 9 on the insulating film 10, reliability is improved.
すなわち、本実施例のマルチチップ型半導体装置の半導
体チップの実装は、第１図及び第２図に示すように、シ
リコンマザーチップ２の上にシリコン酸化膜８を形成し
た後、ガリウムヒ素エピタキシャル層又は窒化アルミニ
ウム膜のようなガリウムヒ素チップ９の熱膨張率と略同
一又はそれに近い熱膨張率を有す絶縁膜１０を形成する
。その後、ガリウムヒ素チップ９を実装すべき領域に、
ホトエツチング技術により、絶縁膜１０を選択的に残留
させる。その後、チップ間の配線３をホトエツチング技
術により形成する。That is, as shown in FIGS. 1 and 2, the semiconductor chips of the multi-chip semiconductor device of this embodiment are mounted, after forming a silicon oxide film 8 on a silicon mother chip 2, a gallium arsenide epitaxial layer is formed. Alternatively, an insulating film 10 such as an aluminum nitride film having a coefficient of thermal expansion that is substantially the same as or close to that of the gallium arsenide chip 9 is formed. After that, in the area where the gallium arsenide chip 9 is to be mounted,
The insulating film 10 is left selectively by photoetching. Thereafter, interconnections 3 between the chips are formed using photoetching technology.
以上までの工程をウェハレベルで加工し、ダイシング等
でマザーチップレベルに分割し、パッケージ基板１上に
接着する。The above steps are carried out at the wafer level, the chips are divided into mother chip levels by dicing, etc., and the chips are bonded onto the package substrate 1.
その後、絶縁膜１０上にガリウムヒ素チップ９を、その
他の領域には、シリコンチップ７をブリップチップ方式
の突起電極６により実装し、パッケージ基板１に設けら
れた外部リード（リードピン）４と配線３をワイヤボン
ディング５により電気的に接続する。Thereafter, a gallium arsenide chip 9 is mounted on the insulating film 10, and a silicon chip 7 is mounted on the other areas using a blip-chip type projecting electrode 6, and external leads (lead pins) 4 and wiring 3 provided on the package substrate 1 are mounted. are electrically connected by wire bonding 5.
以上の説明かられかるように、本実施例によれば、高速
度の動作をさせたい部分にはガリウムヒ素チップ９を用
い、大集積度を必要とする部分にはシリコンチップ７を
用い、ガリウムヒ素チップ９の熱膨張率と略同一又はそ
れに近い熱膨張率を有する材質の絶縁膜１０を選択的に
設け、該絶縁膜１０の上にガリウムヒ素チップ９を塔載
することにより、高集積度のシリコンチップ７と高速化
のガリウムヒ素チップ９を混在さたマルチチップ型半導
体装置の高密度化及び高速化がはかれるとともに、高信
頼な実装を可能にすることができる。As can be seen from the above description, according to this embodiment, the gallium arsenide chip 9 is used for the part where high-speed operation is desired, the silicon chip 7 is used for the part that requires a large degree of integration, and the gallium arsenide chip 9 is used for the part where high-speed operation is required. By selectively providing an insulating film 10 made of a material having a coefficient of thermal expansion that is substantially the same as or close to that of the arsenic chip 9, and mounting the gallium arsenide chip 9 on the insulating film 10, high integration is achieved. It is possible to increase the density and speed of a multi-chip type semiconductor device in which silicon chips 7 and high-speed gallium arsenide chips 9 are mixed together, and also enable highly reliable mounting.
また、既在の技術が使用できるので、装置の歩留を向上
させることができる。Furthermore, since existing technology can be used, the yield of the device can be improved.
以上説明したように、本願で開示した新規な技術によれ
ば、次に述べるような効果を得ることができる。As explained above, according to the new technology disclosed in this application, the following effects can be obtained.
（１）配線を設けた半導体チップ塔載基板に複数個の半
導体チップを塔載したマルチチップ型半導体装置におい
て、前記複数個の半導体チップのうち少なくとも一個は
異なる材質の半導体チップとし、前記半導体チップ塔載
基板上に異なる材質の半導体チップの熱膨張率と略同一
又はそれに近い膨張率を有する絶縁膜を選択的に設け、
該絶縁膜の上に異な材質の半導体チップを塔載すること
により、周囲温度が変化した場合、該半４体チップとマ
ザーチップとの熱膨張率の差を絶Ｂ膜で吸収して、突起
電極にクラック等を生ずるのを防止することができるの
で、装置の信頼性を向上させたことができる。(1) In a multi-chip semiconductor device in which a plurality of semiconductor chips are mounted on a semiconductor chip mounting substrate provided with wiring, at least one of the plurality of semiconductor chips is a semiconductor chip made of a different material, and the semiconductor chip selectively providing on the mounting substrate an insulating film having a coefficient of thermal expansion that is substantially the same as or close to the coefficient of thermal expansion of a semiconductor chip made of a different material;
By mounting semiconductor chips made of different materials on the insulating film, when the ambient temperature changes, the difference in thermal expansion coefficient between the half-quad chip and the mother chip is absorbed by the absolute B film, and the protrusion Since it is possible to prevent cracks from occurring in the electrodes, the reliability of the device can be improved.
（２）前記（１）により、高速度の動作をさせたい部分
にはガリウムヒ素チップを用い、大集積度を必要とする
部分にはシリコンチップを用いることができるので、マ
ルチチップ型半導体装置の高密度化及び高速化をはかる
ことができる。(2) According to (1) above, gallium arsenide chips can be used for parts that require high-speed operation, and silicon chips can be used for parts that require large integration, so multi-chip semiconductor devices can be High density and high speed can be achieved.
（３）マザーチップをシリコンで構成することにより、
既在の技術が使用できるので、装置の歩留を向上させる
ことができる。(3) By configuring the mother chip with silicon,
Since existing technology can be used, the yield of the device can be improved.
以上、本発明を実施例にもとすき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
はいうまでもない。The present invention has been specifically explained above using examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the gist thereof.
例えば、マルチチップ型半導体装置のシスチル構成は、
前記実施例に限定されることなく必要に応じて種々変形
できる。For example, the cystyl configuration of a multi-chip semiconductor device is
The embodiments are not limited to the embodiments described above, and can be modified in various ways as necessary.
また、前記絶縁膜は、その機能を果すものであればどの
ようなものでもよい。Furthermore, the insulating film may be of any type as long as it fulfills its function.
第１図及び第２図は、本発明をマルチチップ型半導体装
置に適用し、た一実施例の構成を説明するための図であ
り。
第１図は、そのマルチチップ半導体装置の平面図、
第２図は、第１図の■−■切断線における断面図、
第３図は１本発明の背景技術を説明するためのマザーチ
ップ型の半導体装置の断面図である。
図中、ｌ・・パッケージ基板、２・・・マザーチップ。
３・・・配線、４・・・外部リード、５・・・ボンディ
ングワイヤ、６・・突起電極、７・・・シリコンチップ
、８・・シリコン酸化膜、９・・ガリウムヒ素チップ、
１０・・絶縁膜である。
代理人 弁理士 高橋明夫１，２．．７、・７゛第
１ 図FIGS. 1 and 2 are diagrams for explaining the configuration of another embodiment in which the present invention is applied to a multi-chip semiconductor device. FIG. 1 is a plan view of the multi-chip semiconductor device, FIG. 2 is a sectional view taken along the cutting line -■ in FIG. 1, and FIG. 3 is a mother chip type for explaining the background art of the present invention. FIG. 2 is a cross-sectional view of the semiconductor device of FIG. In the figure, l: package board, 2: mother chip. 3... Wiring, 4... External lead, 5... Bonding wire, 6... Protruding electrode, 7... Silicon chip, 8... Silicon oxide film, 9... Gallium arsenide chip,
10...Insulating film. Agent Patent Attorney Akio Takahashi 1, 2. ．． 7,・7゛th
1 figure
Claims (1)
体チップを塔載したマルチチップ型半導体装置において
、前記複数個の半導体チップのうち少なくとも一個は異
なる材質の半導体チップとし、前記半導体チップ塔載基
板上に異なる材質の半導体チップの熱膨張率と略同一又
はそれに近い熱膨張率を有する材質の絶縁膜を選択的に
設け、該絶縁膜の上に異な材質の半導体チップを塔載し
たことを特徴とする半導体装置。 ２、前記絶縁膜を前記異なる半導体チップの材質と同じ
材質のエピタキシャル層で構成したことを特徴とする特
許請求の範囲第１項記載の半導体装置。 ３、前記絶縁膜を窒化アルミニウム（ＡｌＮ）で構成し
たことを特徴とする特許請求の範囲第１項記載の半導体
装置。 ４、前記半導体チップ塔載基板をシリコンで構成し、異
なる材質の半導体チップをガリウムヒ素チップとし、他
の半導体チップをシリコンチップとしたことを特徴とす
る特許請求の範囲第１項又は第２項記載の半導体装置。[Claims] 1. In a multi-chip semiconductor device in which a plurality of semiconductor chips are mounted on a semiconductor chip mounting substrate provided with wiring, at least one of the plurality of semiconductor chips is a semiconductor chip made of a different material. An insulating film made of a material having a coefficient of thermal expansion that is substantially the same as or close to that of the semiconductor chip made of a different material is selectively provided on the semiconductor chip mounting substrate, and a semiconductor made of a different material is provided on the insulating film. A semiconductor device characterized by mounting a chip. 2. The semiconductor device according to claim 1, wherein the insulating film is formed of an epitaxial layer made of the same material as the material of the different semiconductor chip. 3. The semiconductor device according to claim 1, wherein the insulating film is made of aluminum nitride (AlN). 4. Claim 1 or 2, characterized in that the semiconductor chip mounting substrate is made of silicon, the semiconductor chips made of different materials are gallium arsenide chips, and the other semiconductor chips are silicon chips. The semiconductor device described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59233105A JPS61112362A (en) | 1984-11-07 | 1984-11-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59233105A JPS61112362A (en) | 1984-11-07 | 1984-11-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS61112362A true JPS61112362A (en) | 1986-05-30 |
Family
ID=16949850
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59233105A Pending JPS61112362A (en) | 1984-11-07 | 1984-11-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS61112362A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310411A (en) * | 2005-04-26 | 2006-11-09 | Fujitsu Ltd | Semiconductor device |
| JP2016167635A (en) * | 2011-07-11 | 2016-09-15 | 三菱電機株式会社 | Semiconductor module for electric power |
-
1984
- 1984-11-07 JP JP59233105A patent/JPS61112362A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006310411A (en) * | 2005-04-26 | 2006-11-09 | Fujitsu Ltd | Semiconductor device |
| JP4707446B2 (en) * | 2005-04-26 | 2011-06-22 | 富士通セミコンダクター株式会社 | Semiconductor device |
| JP2016167635A (en) * | 2011-07-11 | 2016-09-15 | 三菱電機株式会社 | Semiconductor module for electric power |
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