JPS61100950A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPS61100950A
JPS61100950A JP22171384A JP22171384A JPS61100950A JP S61100950 A JPS61100950 A JP S61100950A JP 22171384 A JP22171384 A JP 22171384A JP 22171384 A JP22171384 A JP 22171384A JP S61100950 A JPS61100950 A JP S61100950A
Authority
JP
Japan
Prior art keywords
insulating layer
wiring pattern
etching
groove
shaped
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22171384A
Other languages
Japanese (ja)
Inventor
Yukio Tomita
富田　行雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP22171384A priority Critical patent/JPS61100950A/en
Publication of JPS61100950A publication Critical patent/JPS61100950A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate defective slip-off on etching and a disconnection, etc. due to side etching, and to form a wiring pattern fit for the increase of frequency and fining by shaping a groove to a surface insulator in a semiconductor element, attaching a metallic wiring material through evaporation and grinding the surface without an etching process to form the wiring pattern. CONSTITUTION:A diffusion layer 12 and an insulating layer 13 are shaped onto a semiconductor substrate 11 through a known method. The insulating layer 13 is formed by using a known surface flattening technique to shape the insulating layer having a flat surface. The insulating layer is formed in slightly thick size such as approximately 2mum. Grooves 15 for a wiring pattern are shaped to the insulating layer 13 by employing a photoetching techniquie. The depth of the groove is brought to size such as 1mum. A contact hole is formed by repeating a photoetching process. An electrode material 14 consisting of Al, etc. is attached onto the whole surface through evaporation or sputtering or the like. The surface is ground without executing a photo-resist pattern forming process and an etching process, thus obtaining the wiring pattern shaped into the groove sections.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子の製造方法に関し、特に高集積度、
小型化に適した配線パターンを形成する半導体素子の製
造方法に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing semiconductor devices, particularly for highly integrated and
The present invention relates to a method of manufacturing a semiconductor element that forms a wiring pattern suitable for miniaturization.

〔従来の技術〕[Conventional technology]

半導体素子、特に集積回路素子において、性能向上の一
つの手法として微細加工がチシ、微細加工は半導体素子
の高周波動作あるいは高集積化に対応するのに絶対必要
な技術である。微細化を１めて行くとき、当然の問題と
して起るのは配線パターンの微細化で素子に比例して微
細化し、その結果配線幅、配線間隔も狭くなる。しかし
従来の配線パターンの形成は第λ図に示すように、半導
体基板１の上の拡散層２に絶縁層３を介して電極配線４
が形成されている。この構造を形成するには、表面に付
着させたＡ１などの配線材料にマスクを施こし、エツチ
ングを行なってい友。Microfabrication is one of the techniques for improving the performance of semiconductor devices, especially integrated circuit devices, and microfabrication is an absolutely necessary technology to support high-frequency operation or high integration of semiconductor devices. When we first consider miniaturization, a natural problem that arises is the miniaturization of wiring patterns, which become finer in proportion to the elements, and as a result, the wiring width and wiring spacing become narrower. However, in the conventional wiring pattern formation, as shown in FIG.
is formed. To form this structure, a mask is applied to the wiring material such as A1 attached to the surface, and etching is performed.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述したように従来の配線パターンの形成には金属材料
のエツチングを行なっているため、微細化が進むとエツ
チングの抜は不良、またはサイドエツチングによる断線
等の問題が生じ微細化に限界を生じる。As mentioned above, conventional wiring patterns are formed by etching a metal material, and as the pattern becomes finer, problems such as poor etching or disconnection due to side etching occur, which limits the ability to make finer patterns.

そこで、本発明は上述したエツチングの抜は不良、サイ
ドエツチングによる断線等微細化にともなう配線パター
ンの問題を排除し、高周波化微細化に好適な配線パター
ンを形成オル半導体素子の製造方法を提供することを目
、的とする。Therefore, the present invention eliminates the problems of wiring patterns associated with miniaturization, such as defective etching and disconnection due to side etching, and provides a method for manufacturing an all-semiconductor element that forms a wiring pattern suitable for high frequency miniaturization. to aim at something.

〔問題を解決するための手段〕[Means to solve the problem]

本発明の半導体素子の製造方法は、半導体素子の表面絶
縁体に溝を設けた後、金属配線材料を蒸着あるいはスパ
ッタ等で付着させた後、エツチング工程を行なわずに表
面の研磨を行うととＫよ）配線パターンを形成すること
によ多構成される。The method for manufacturing a semiconductor device of the present invention includes forming a groove in a surface insulator of a semiconductor device, depositing a metal wiring material by vapor deposition or sputtering, and then polishing the surface without performing an etching process. K) It is constructed by forming a wiring pattern.

〔実施例〕〔Example〕

以下、本発明の実施例について、図面を参照して説明す
る。Embodiments of the present invention will be described below with reference to the drawings.

第７図は本発明の一実施例を説明するための半導体素子
の要部の断面図である。第２図に示すように、まず、半
導体基板１１に拡散層１２、絶縁層１３を公知の方法で
設ける。絶縁層１３の形成にあたりては公知の表面平坦
化技術を使用し表面が平坦な絶縁層とするまた絶縁層は
稍々厚めに、例えば２μｍ程度とする。FIG. 7 is a sectional view of a main part of a semiconductor element for explaining one embodiment of the present invention. As shown in FIG. 2, first, a diffusion layer 12 and an insulating layer 13 are provided on a semiconductor substrate 11 by a known method. In forming the insulating layer 13, a known surface flattening technique is used to form an insulating layer with a flat surface, and the insulating layer is made somewhat thick, for example, about 2 μm.

次に、絶縁層１３にホトエツチング技術を使用して配線
パターンの溝１５を形成する。溝の深さは例えば１μｍ
とする。次いでホトエツチング工程を〈シ返してコンタ
クト孔１６を形成する。Next, a groove 15 for a wiring pattern is formed in the insulating layer 13 using a photoetching technique. The depth of the groove is, for example, 1 μm.
shall be. Next, the photo-etching process is repeated to form contact holes 16.

次に、Ａ１等の電極材料１４を蒸着又はスパッタ等で表
面全体に付着させる。Next, an electrode material 14 such as A1 is deposited over the entire surface by vapor deposition, sputtering, or the like.

次に、ホトレジストパターン形成工程エツチング工程を
行うことなく表面研磨を行う、研磨技術が進歩したので
溝部以外の電極材料を比較的容易に除去することができ
溝部内に形成された配線パターンを得ることができる。Next, surface polishing is performed without performing the photoresist pattern forming process and the etching process.As polishing technology has advanced, electrode material other than the groove can be removed relatively easily, and a wiring pattern formed within the groove can be obtained. I can do it.

〔発明の効果〕〔Effect of the invention〕

以上説明したとおシ、本発明によれば：金属材料のエツ
チングに代シ絶縁層のエツチングの必要はあるが、それ
ぞれのエツチング・マージ／は、絶縁層の方がはるかに
小さく、よシ微細化が可能である。特に従来のエツチン
グによシエッチングの抜け不良、サイドエツチングによ
る断線等の問題は大幅に改善することができる。また配
線面が平坦であるので多層配線構造に特に有利である。As explained above, according to the present invention: Although it is necessary to etch the insulating layer instead of etching the metal material, the respective etching merges are much smaller for the insulating layer, and the insulating layer is finer. is possible. In particular, problems caused by conventional etching, such as incomplete etching and wire breakage due to side etching, can be significantly improved. Furthermore, since the wiring surface is flat, it is particularly advantageous for multilayer wiring structures.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例を説明するための午導体素子
の要部断面図、第２図は従来の半導体素子の製造方法を
説明するための一例の要部断面図である。 １．１１・・・・・・半導体基板、２，１２・・・・・
・拡散層、３．１３・・・・・・絶縁層、４．１４・・
・・・・電極配線材料、１５・・・・・・溝、１６・・
・・・・コンタクト孔。FIG. 1 is a cross-sectional view of a main part of a conductor element for explaining an embodiment of the present invention, and FIG. 2 is a cross-sectional view of a main part of an example for explaining a conventional method of manufacturing a semiconductor element. 1.11... Semiconductor substrate, 2,12...
・Diffusion layer, 3.13...Insulating layer, 4.14...
... Electrode wiring material, 15 ... Groove, 16 ...
...Contact hole.

Claims (1)

【特許請求の範囲】[Claims] 　半導体素子の表面絶縁体に溝を設けた後、金属配線材
料を蒸着あるいはスパッタ等で付着させた後、エッチン
グ工程を行なわずに表面の研磨を行うことにより配線パ
ターンを形成することを特徴とする半導体素子の製造方
法。A wiring pattern is formed by forming grooves in the surface insulator of a semiconductor element, depositing a metal wiring material by vapor deposition or sputtering, and then polishing the surface without performing an etching process. A method for manufacturing semiconductor devices.
JP22171384A 1984-10-22 1984-10-22 Manufacture of semiconductor element Pending JPS61100950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22171384A JPS61100950A (en) 1984-10-22 1984-10-22 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22171384A JPS61100950A (en) 1984-10-22 1984-10-22 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPS61100950A true JPS61100950A (en) 1986-05-19

Family

ID=16771098

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22171384A Pending JPS61100950A (en) 1984-10-22 1984-10-22 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS61100950A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62102543A (en) * 1985-10-28 1987-05-13 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Formation of conductive film and insulating film with same flat surface

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62102543A (en) * 1985-10-28 1987-05-13 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Formation of conductive film and insulating film with same flat surface

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