JPS5867069A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5867069A JPS5867069A JP56166741A JP16674181A JPS5867069A JP S5867069 A JPS5867069 A JP S5867069A JP 56166741 A JP56166741 A JP 56166741A JP 16674181 A JP16674181 A JP 16674181A JP S5867069 A JPS5867069 A JP S5867069A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- electrode
- forming
- insulating film
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 238000004519 manufacturing process Methods 0.000 title abstract description 10
- 239000000758 substrate Substances 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 9
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000006243 chemical reaction Methods 0.000 abstract description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 230000004083 survival effect Effects 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 26
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 241000255925 Diptera Species 0.000 description 1
- 235000016496 Panda oleosa Nutrition 0.000 description 1
- 240000000220 Panda oleosa Species 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 235000012976 tarts Nutrition 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は多層導電層構造、例えば多層ｆｆ−）電極構造
、を有する半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device having a multilayer conductive layer structure, for example a multilayer ff-) electrode structure.
一般に、この種の半導体装置においては、第１の導電層
と半導体基板との間、及び第１０導電層と第２の導電層
との間の耐圧が所望の値を保有するように製造すること
が信頼性の点から重要である。Generally, this type of semiconductor device is manufactured so that the breakdown voltage between the first conductive layer and the semiconductor substrate and between the tenth conductive layer and the second conductive layer has a desired value. is important from the point of view of reliability.
ところでかかる構造の半導体装置、例えば、ＭＯ８メイ
ナζツクＲＡＭを製造するＫは、従来次のような方法が
採用されている。まず第１図（、）に示すようＫＰＩＩ
シリコン基板１上に選択酸化法によシ、素子分離のため
のフィールド酸化膜２を形成する。つづいて第１図伽）
に示すように熱酸化処理を施して第１ダート絶縁膜とな
る厚さ３００１＠度の熱酸化膜３を成長させ更に第１の
ダート電極となる厚さ４０００１程度の多結晶シリコン
膜４を堆積し、これを光蝕刻法によ）Δターニングして
第１のｒ−）電極６を形成しさらに、同電極５をマスク
として熱酸化膜Ｊをエツチング除去して、第１ダート絶
縁ｊｌ［６を形成する（第１図（、）図示）。ひきつづ
き高温中のウェット酸素雰囲気中で熱処理を施して第１
のｒ−ト電極Ｉ周囲に層間絶縁膜となる厚いシリプン酸
化膜１を、露出する基板１上に厚さ５ｏｏ１８度Ｏ熱酸
化ｌ！＆８を成長させる（菓１図（、ｌｉ）図示）。次
いで全面に第２のｒ−）電極となる多結晶シリコン膜を
堆積し、これをノ量ターニングして、第２のダート電極
＃を形成し、更に蚊電極９をマスクとして熱酸化膜８を
エツチングして第２デート絶縁Ｈｘａを形成した後、露
出する半導体基板に砒素を拡散してｎ十拡散層１１を形
成する（第１図（・）図示）。その後、全面４ＣＣＶＤ
−８１０２ｇ １２ ｆ １１１積し、コノｃＶＤ−８
ｉＯ１１［１２にコンタクトホールを開孔した後、Ａｌ
属を堆積しＸ ）４ターニングして第１と第２のｒ−）
電極５，９及びｎ十拡散層１１とコンタクトホールを介
して接続したＡＩ配線１３．１４．１５を形成してＭＯ
ＳダイナミックＲＡＭを製造する（第１図（ｆ）図示）
。By the way, the following method has conventionally been adopted for manufacturing a semiconductor device having such a structure, for example, an MO8 main RAM. First, as shown in Figure 1 (,), KPII
A field oxide film 2 for element isolation is formed on a silicon substrate 1 by selective oxidation. Continued in Figure 1)
As shown in the figure, thermal oxidation treatment is performed to grow a thermal oxide film 3 with a thickness of 3001°C which will become the first dirt insulating film, and then a polycrystalline silicon film 4 with a thickness of about 40001°C which will become the first dirt electrode is deposited. Then, this is subjected to Δ turning by photoetching to form a first r-) electrode 6, and the thermal oxide film J is removed by etching using the same electrode 5 as a mask to form a first dirt insulator jl[6]. (Illustrated in FIG. 1(, )). Subsequently, heat treatment is performed in a wet oxygen atmosphere at high temperature to obtain the first
A thick silicone oxide film 1 serving as an interlayer insulating film is placed around the r-to-electrode I on the exposed substrate 1 to a thickness of 5mm to 18°C. &8 (illustrated in Fig. 1). Next, a polycrystalline silicon film that will become a second r-) electrode is deposited on the entire surface, and this is turned to form a second dirt electrode #, and then a thermal oxide film 8 is deposited using the mosquito electrode 9 as a mask. After forming the second date insulation Hxa by etching, arsenic is diffused into the exposed semiconductor substrate to form an n+ diffusion layer 11 (as shown in FIG. 1). After that, the entire surface was 4CCVD
-8102g 12 f 111 product, Kono cVD-8
After opening a contact hole in iO11[12, Al
Deposit the genus x) with 4 turns and the first and second r-)
AI wirings 13, 14, and 15 connected to the electrodes 5, 9 and the n+ diffusion layer 11 through contact holes are formed to form the MO
Manufacturing S dynamic RAM (as shown in Figure 1(f))
.
しかしながら上述したＭＯＳダイナミックＲＡＭの製造
方法にあっては、次のような欠点があった。すなわち全
面に第２のダート電極となる多結晶シリコン膜を堆積し
、これを光蝕刻法によシ、・母ターニングして、第２の
ダート電極９を形成する際に１第２図に示す如く、第１
のダー熱酸化膜８との段差部分にある多結晶シリコン９
′をエツチングするためにはかな９のオーバーエツチン
グが必要となシ、その結果、第２のダート電極の巾が著
しく細くなシ、ひいては＾密度微細・臂ターン加工の障
害となる。これを避ける丸めに、多結晶シリコン膜をジ
ャストエツチングして第２のｒ−）電極９を形成すると
、シリコン酸化膜７と熱酸化膜８との段差部分にある多
結晶シリコン９′が残少、これによって第２のｒ−）電
極間が短絡する。However, the method for manufacturing the MOS dynamic RAM described above has the following drawbacks. That is, a polycrystalline silicon film that will become the second dirt electrode is deposited on the entire surface, and then subjected to photolithography and main turning to form the second dirt electrode 9 as shown in FIG. Like, 1st
The polycrystalline silicon 9 in the step part with the thermal oxide film 8 of
In order to etch ', over-etching of the kana 9 is required, and as a result, the width of the second dart electrode cannot be made extremely narrow, which in turn becomes an obstacle to the density fine/arm turn processing. To avoid this, if the second r-) electrode 9 is formed by just etching the polycrystalline silicon film, the polycrystalline silicon 9' at the step between the silicon oxide film 7 and the thermal oxide film 8 will remain. , this causes a short circuit between the second r-) electrodes.
本発明はかかる従来の方法による欠点を解決することを
目的とし、基板上の絶縁膜と第１の導電層上の絶縁膜と
の段差を緩和させ、高密度の微細配線を備えた半導体装
置を提供しようとするものである。The present invention aims to solve the drawbacks of such conventional methods, and aims to reduce the difference in level between the insulating film on the substrate and the insulating film on the first conductive layer, thereby producing a semiconductor device with high-density fine wiring. This is what we are trying to provide.
即ち、本発明の半導体装置の製造方法は、半導体基板の
第１絶縁膜上に設けられた第１の導電層の側面に絶縁層
を形成し、この全面に第２の絶縁膜を形成し、この第２
の絶縁膜上に第２の導電層を形成することを特徴とする
ものである。That is, in the method for manufacturing a semiconductor device of the present invention, an insulating layer is formed on the side surface of a first conductive layer provided on a first insulating film of a semiconductor substrate, and a second insulating film is formed on the entire surface of the first conductive layer. This second
The second conductive layer is formed on the insulating film.
本発明に用いる絶縁膜としては１． ＣＶＤ−８１０゜
膜、窒化シリコン膜、熱酸化膜等を挙げることができる
。As the insulating film used in the present invention, 1. Examples include a CVD-810° film, a silicon nitride film, and a thermal oxide film.
但し、絶＃膜は、半導体基板上に直接形成されたもの、
或いは第１のダート電極配線周囲に設けられたもの等を
挙げることができ、特に第１の導電層を多結晶シリコン
、金属硅化物で構成し、この熱酸化によシ、成長された
酸化膜を絶縁膜として利用することができる。However, the insulation film is one formed directly on the semiconductor substrate,
Alternatively, the first conductive layer is formed around polycrystalline silicon or metal silicide, and the oxide film grown by this thermal oxidation is used. can be used as an insulating film.
本発明に用いる導電層材料としては、例えば多結晶シリ
コン、金属硅化物等を挙げることができる。Examples of the conductive layer material used in the present invention include polycrystalline silicon, metal silicide, and the like.
本発明における段差緩和用の絶縁膜のエツチング手段と
しては、例えば反応性イオンエツチング法を用いる方法
等を挙げることができる。In the present invention, as the etching means for the insulating film for reducing the step difference, for example, a method using a reactive ion etching method can be mentioned.
次に本発明を二層ｆ−）電極構造を有するＭＯＳダイナ
ミックＲＡＭの製造に適用した例について、第３図（ａ
）〜［有］）及び第４図、第５図を参照として説明する
。Next, an example in which the present invention is applied to the manufacture of a MOS dynamic RAM having a two-layer f-) electrode structure is shown in FIG.
) to [exist]) and FIGS. 4 and 5 will be described.
まず第３図伽）に示すようにＰ型（１００面）のシリコ
ン基板１０１（比抵抗１１〜１３ｏｈｍ、国）を窒化シ
リコンをマスクとして、選択酸化して、素子分離の丸め
の厚さ１μｍのフィールド酸化膜１０２を形成した。First, as shown in Fig. 3, a P-type (100-sided) silicon substrate 101 (resistivity 11-13 ohm, country) was selectively oxidized using silicon nitride as a mask to form a rounded layer with a thickness of 1 μm for element isolation. A field oxide film 102 was formed.
次いで、１０００℃のドライ酸素雰囲気中で熱処理して
シリコン基板１０１の素子形成領域上に厚さ３００Ｘの
熱酸化膜１０３を成長させ、更に、厚さ４ｏｏｏ１の多
結晶シリコン膜１０４を堆積したのち、この多結晶シリ
コン膜１０４にリン拡散を行ってリンをｌＸ１０２１Ａ
−ドーピングした（第３回軸）図示）。ひきつづき、リ
ント−！多結晶シリコン膜１０４を写真蝕刻により１４
ターニングして、第１のダート電極１０５を形成し、更
に骸電極１０５をマスクとして熱酸化膜１０３をセルフ
ァラインでエツチングし、第１ｒ−）絶縁膜１０６を形
成した（第３図（ｃ）図示）。Next, a thermal oxide film 103 with a thickness of 300X is grown on the element formation region of the silicon substrate 101 by heat treatment in a dry oxygen atmosphere at 1000°C, and a polycrystalline silicon film 104 with a thickness of 4001 is further deposited. Phosphorus is diffused into this polycrystalline silicon film 104 to
- Doped (as shown in the 3rd axis). Continue, Lindt! Polycrystalline silicon film 104 is etched 14 by photolithography.
Turning was performed to form a first dirt electrode 105, and the thermal oxide film 103 was etched with a self-line using the skeleton electrode 105 as a mask to form a first r-) insulating film 106 (as shown in FIG. 3(c)). ).
次いでＣＶＤ−８ｉｔｓ膜１０Ｆを全面に堆積させ（第
３図（ｄ）図示）、これを反応性イオンエツチング法で
全面エツチングした。このとき、第１のダート電極１０
５の側面には、ｃｖｏ−ｓｔｏ冨層１０１１が残るよう
にエツチング時間を調整した（第３図（、）、第４図図
示）。この第１のダート電極１０５の側面のＣＶＤ−８
ｉ Ｏｓ層１０８が、第１のダート電極ノ０５上の絶縁
膜と、基板１０ノ上の絶縁膜の段差を緩和するのである
。さらに、層間絶縁膜と第２ｆｆ−）絶縁膜形成のため
に８００℃のウェット酸累雰囲気中で熱処理を行う（第
３図（ｆ）図示）。Next, a CVD-8its film 10F was deposited on the entire surface (as shown in FIG. 3(d)), and the entire surface was etched using a reactive ion etching method. At this time, the first dirt electrode 10
The etching time was adjusted so that the CVO-STO rich layer 1011 remained on the side surface of 5 (as shown in FIGS. 3(a) and 4). CVD-8 on the side surface of this first dirt electrode 105
The iOs layer 108 alleviates the difference in level between the insulating film on the first dirt electrode 05 and the insulating film on the substrate 10. Furthermore, heat treatment is performed in a wet acidic atmosphere at 800° C. to form an interlayer insulating film and a second ff-) insulating film (as shown in FIG. 3(f)).
次いで、全面に第２のｅ−）電極材料としての厚さ４０
００Ｘのリント−！多結晶シリコン膜を堆積し、写真蝕
刻法によシ・ヤターニングして、第２のｒ−）電極１１
２を形成した。更に該電極１１２をマスクとして熱酸化
膜１１０をセルファラインでエツチングして第２ｒ−）
絶縁膜１１１を形成した後、砒素をシリコン基板１０１
にイオン注入して、訝拡散層１１３を形成し九（第３図
優）、第５図図示）。Then, a second e-) electrode material with a thickness of 40 mm is applied to the entire surface.
00X Lint! A polycrystalline silicon film is deposited and turned by photolithography to form a second r-) electrode 11.
2 was formed. Furthermore, using the electrode 112 as a mask, the thermal oxide film 110 is etched with a self-alignment layer (2r-).
After forming the insulating film 111, arsenic is applied to the silicon substrate 101.
Then, ions are implanted into the substrate to form a transparent diffusion layer 113 (see FIG. 3) and FIG. 5 (shown in FIG. 5).
このＣＶＤ−８ｉｎｓ膜１１４にコンタクトホールを開
孔した後、Ａｌ膜を堆積し、・母ターニングして、第１
層、第２層のり”−計電極１０５，１１２及ヒ、ｎ＋拡
散層１１３とコンタクトホールを介して接続したＡＩ配
線１１５．１１６．１１７を形成してＭＯＳダイナミッ
クＲＡＭを製造した（第３図（ｈ）図示）。After opening a contact hole in this CVD-8ins film 114, an Al film is deposited, and the first
A MOS dynamic RAM was manufactured by forming AI wirings 115, 116, and 117 connected to the second layer glue electrodes 105, 112, and the n+ diffusion layer 113 through contact holes (see Fig. 3). h) As shown).
上述した本実施例において第１のダート電極１０５を形
成したのちｃｖｏ−ｓｔｏ、膜ｘｏｖｔ全ＷＪエツチン
グして、第１のｒ−）電極の側面に残したため、そのの
ちのリンドープ多結晶シリコンの第２のダート電極１１
２の形成に際し、第２のｒ−）電極相互の短絡を招くこ
となくオーバーエツチング時間を少なくできることによ
シ、・ぐターン変換差を小さくおさえることができ、高
密度で微細な第２のｒ−）電極１１２を備え九ＭＯ８ダ
イナぐツクＲＡＭを製造できた。In this embodiment described above, after forming the first dirt electrode 105, the entire WJ etching of the cvo-sto film xovt was performed, and it was left on the side surface of the first r-) electrode. 2 dart electrode 11
2, by reducing the overetching time without causing short circuit between the second r-) electrodes, it is possible to suppress the difference in turn conversion to a small level, and to form a high-density and fine second r-) electrode. -) Nine MO8 dynamic RAMs equipped with electrodes 112 could be manufactured.
また得られ九ＭＯＳダイナミックＲＡＭは、第１のｒ−
）電極１０１５を形成したのち、第１のｒ−計電極１０
５の側面に絶縁層１０８が残るように絶縁膜１０７を全
面エツチングする工程から第１のダート電極１０５と第
２のｆ−）電極１１２の間に厚い絶縁層１０８′が介在
するため、それらの絶縁耐圧が著しく向上した。The nine MOS dynamic RAM obtained is also the first r-
) After forming the electrode 1015, the first r-meter electrode 10
Since a thick insulating layer 108' is interposed between the first dart electrode 105 and the second f-) electrode 112 due to the process of etching the entire surface of the insulating film 107 so that the insulating layer 108 remains on the side surfaces of the Dielectric strength has been significantly improved.
以上、詳述した如く、本発明によれば絶縁膜を第１のデ
ート電極の側面に残し、第１のｒ−計電極と第２のｒ−
）電極の層間絶縁膜を形成するため、第１のｒ−）電極
上の絶縁膜と基板上の絶縁膜の段差が緩和され、第２の
ｅ−）電極の形成時、電極相互の短絡を招くことなくオ
ーバーエツチング時間を少なくでき、ひいては高密度の
微細電極を備えた半導体装置を製造し得る方法を提供で
きる。As described in detail above, according to the present invention, the insulating film is left on the side surface of the first date electrode, and the first r-meter electrode and the second r-meter electrode are connected to each other.
) To form an interlayer insulating film for the electrode, the difference in level between the insulating film on the first r-) electrode and the insulating film on the substrate is alleviated, and when forming the second e-) electrode, short circuits between the electrodes can be prevented. It is possible to provide a method in which overetching time can be reduced without causing problems, and in turn, a semiconductor device having high-density fine electrodes can be manufactured.
第１図（、）〜（ｆ）は従来法による二層ダート電極構
造を有するＭＯＳダイナミックＲＡＭの製造工程を示す
断面図。第２図は、第１図０）の部分拡大断面図。第３
図（ｍ）〜（ｈ）は、本発明の実施例における二層ダー
ト電極構造を有するＭＯＳダイナミックＲＡＭの製造工
程を示す断面図。第４図は、第３図（・）の部分拡大断
面図。第５図は、第３図−）の部分拡大断面図である。
１０１・・・ＰＩＭシリコン基板、１０２・・・フィー
ルド酸イヒ膜、１０４・・・リンドープ多結晶シリコン
膜、１０５−・・第１ダート電極、１０６・・・第１タ
ート絶縁膜、１ ｏ ７ ＝−ＣＶＤ−８ｌｏｔ ｇ、
１０９−・・ＣＶＤ−８１０ｍ膜、１１１−・・第２ダ
ート絶縁膜、１１２・・・第２ダート電極、１１３・・
・１拡散層（デジットライン）、１１４ ・−ＣＶＤ−
８１０ｍ膜、１１５，１１６゜１１１・・・ＡＩ配線。
出願人代理人 弁理土鈴 圧式 彦
第１図
ｇａｌｌ
ｊｉ２図
１８３関
第３図
（ｆ）FIGS. 1(a) to 1(f) are cross-sectional views showing the manufacturing process of a MOS dynamic RAM having a two-layer dart electrode structure according to a conventional method. FIG. 2 is a partially enlarged sectional view of FIG. 1 (0). Third
Figures (m) to (h) are cross-sectional views showing the manufacturing process of a MOS dynamic RAM having a two-layer dart electrode structure in an embodiment of the present invention. FIG. 4 is a partially enlarged sectional view of FIG. 3 (-). FIG. 5 is a partially enlarged sectional view of FIG. 3-). DESCRIPTION OF SYMBOLS 101... PIM silicon substrate, 102... Field acid Ihi film, 104... Phosphorus-doped polycrystalline silicon film, 105-... First dirt electrode, 106... First tart insulating film, 1 o 7 = -CVD-8lot g,
109--CVD-810m film, 111--Second dirt insulating film, 112-Second dirt electrode, 113-...
・1 diffusion layer (digit line), 114 ・-CVD-
810m film, 115, 116° 111...AI wiring. Applicant's agent: Patent attorney Dorin Ushiki Hiko Figure 1 Gall ji 2 Figure 183 Figure 3 (f)
Claims (2)
導電層の側面に絶縁層を形成する工程と、この全面に新
たに第２の絶縁膜を形成する工程と、この第２の絶縁膜
上に第２の導電層を形成する工程とを含む、半導体装置
の製造方法。(1) A step of forming an insulating layer on the side surface of the first conductive layer provided on the first insulating film of the semiconductor substrate, a step of newly forming a second insulating film on this entire surface, forming a second conductive layer on the second insulating film.
２の導電層を第２ダート電極とすることを特徴とする特
許請求の範囲第（１）項記載の方法。(2) The method according to claim (1), wherein the first conductive layer is a first dirt electrode, and the second conductive layer is a second dirt electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56166741A JPS5867069A (en) | 1981-10-19 | 1981-10-19 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56166741A JPS5867069A (en) | 1981-10-19 | 1981-10-19 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5867069A true JPS5867069A (en) | 1983-04-21 |
Family
ID=15836884
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56166741A Pending JPS5867069A (en) | 1981-10-19 | 1981-10-19 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5867069A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62261147A (en) * | 1986-05-07 | 1987-11-13 | Nec Corp | Semiconductor device |
-
1981
- 1981-10-19 JP JP56166741A patent/JPS5867069A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62261147A (en) * | 1986-05-07 | 1987-11-13 | Nec Corp | Semiconductor device |
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