JPS6091666A - One-dimensional photoelectric conversion device - Google Patents
One-dimensional photoelectric conversion deviceInfo
- Publication number
- JPS6091666A JPS6091666A JP58198204A JP19820483A JPS6091666A JP S6091666 A JPS6091666 A JP S6091666A JP 58198204 A JP58198204 A JP 58198204A JP 19820483 A JP19820483 A JP 19820483A JP S6091666 A JPS6091666 A JP S6091666A
- Authority
- JP
- Japan
- Prior art keywords
- light
- elements
- bias
- receiving
- thin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000006243 chemical reaction Methods 0.000 title claims description 5
- 239000010409 thin film Substances 0.000 claims abstract description 11
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 2
- 239000010408 film Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 229910018110 Se—Te Inorganic materials 0.000 description 1
- 229910005091 Si3N Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 102100024063 Type I iodothyronine deiodinase Human genes 0.000 description 1
- 101710119122 Type I iodothyronine deiodinase Proteins 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14643—Photodiode arrays; MOS imagers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Facsimile Heads (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は、ファクシミＩＪあるいは複写機等の高速の密
着型１次元イメージセンサ−に使用する１次元光電変換
装置に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a one-dimensional photoelectric conversion device used in a high-speed contact type one-dimensional image sensor such as a facsimile IJ or a copying machine.
（従来例の構成とその問題点）
従来、ファク７ミリ等に用いられる１次元イメージセン
サ−には、Ｃｄ５Ｓｅを用いた薄膜の受光素子プレイが
王とｌ、て用いられて来た。(Structure of Conventional Example and Problems Therewith) Conventionally, a thin film light-receiving element made of Cd5Se has been used in one-dimensional image sensors used in 7mm facsimile and the like.
第１図は従来のＣｄ５Ｓｅを用いたマトリックス結線の
１次元センサーの回路構成を示すもので、Ｃｌ０Ｉ〜Ｃ
１６４は共通電極側スイッチ、５ＩＯＩ−８１３２は個
別電極側スイッチ、ＤＩＯＩ〜Ｄ１３２はＣｄ５Ｓｅ受
光ダイオードを示す。Figure 1 shows the circuit configuration of a matrix-connected one-dimensional sensor using conventional Cd5Se.
164 is a common electrode side switch, 5IOI-8132 is an individual electrode side switch, and DIOI to D132 are Cd5Se light receiving diodes.
これは、光電流の変化の大きな材料を用いることによっ
て受光素子の明抵抗が小さく（１００Ａ！ｘの照明時で
約１．２ＭΩ程度）、外部のスイッチング回路が容易に
構成でき、比較的素子電極間の浮遊容量の大きなマトリ
ックス結線多層配線を用いてコンパクトに安価にできる
利点があった。しかし、光応答ではＣｄ Ｓ Ｓｅを用
いた場合、５ ｍ 、８ｅｃ／ｌ ｉ’ｎｅ（但し、１
７２８素子数、８素子廓）の読み取り速度が限度と言わ
れており、このため、光応答の速い非晶質Ｓｅ−Ｔｅ
−Ａｓ 、水素化非晶質シリコン（以下、ａ−８ｉ ：
Ｈと記す。）を受光素子としたセンサーが試みられて
いる。これらの多くはダイオード特性を持ち、光電流を
容量に蓄積し、蓄積電荷をスイッチング素子等で読み出
す方法が多く試みられ、５ ｍ ｓｅｃ／１ｉｎｅ （
上記素子数）の夾績が得られている。しかし、これら電
荷蓄積型センサーでは、感度が向上する反面、高抵抗回
路のため外部のスイッチングによるノイズが浮遊容量を
介して混入し、ノイズ除去のだめの回路処理と、各素子
１つ１つにスイッチング素子を必要とするため、実装上
の困難を伴う。また、２ ｍ Ｂｅｃ／ｌ ｉｎｅ以上
の高速化には、誓積時間の減少と、高周波化のためのス
イッチングノイズの増加にょるＳ／Ｎ比の低下が問題と
なる。By using a material with a large change in photocurrent, the light resistance of the photodetector is small (approximately 1.2MΩ at 100A!x illumination), the external switching circuit can be easily configured, and the element electrode It has the advantage of being compact and inexpensive by using matrix-connected multilayer wiring with a large stray capacitance between them. However, in the photoresponse, when CdSSe is used, 5 m, 8ec/l i'ne (however, 1
It is said that the reading speed of 728 elements and 8 elements is the limit, and for this reason, amorphous Se-Te with fast photoresponse is used.
-As, hydrogenated amorphous silicon (hereinafter a-8i:
Write it as H. ) as a light-receiving element has been attempted. Many of these have diode characteristics, and many attempts have been made to accumulate photocurrent in a capacitor and read out the accumulated charge using a switching element, etc.
The results of the above-mentioned number of elements have been obtained. However, although these charge storage type sensors have improved sensitivity, their high resistance circuits allow noise from external switching to enter through stray capacitance, requiring circuit processing to remove noise and switching each element one by one. Since it requires an element, it is difficult to implement. Further, in increasing the speed to 2 m Bec/line or more, problems arise such as a decrease in the integration time and a decrease in the S/N ratio due to an increase in switching noise due to the increase in frequency.
このため、このような１％速領領域は、ノイズの少ない
シリコンＣＯＤが用いられてきた。しかし、ＣＯＤは多
チップを配列し、１次元センザーとするため、光学的な
調整や＠置のコンパクト化にも限度があるため、薄膜に
よる密着型高速センサーが望まれていた。For this reason, silicon COD with less noise has been used in such a 1% speed region. However, COD arrays multiple chips to create a one-dimensional sensor, and there are limits to optical adjustment and compactness of the @ placement, so a close-contact, high-speed sensor using a thin film has been desired.
（発明の目的）
本発明は、上記の欠点を克服し、コンパクトで高速なフ
ァクシミリ等に最適なラインセンサを提供することを目
的とする。(Object of the Invention) An object of the present invention is to overcome the above-mentioned drawbacks and provide a line sensor that is compact and suitable for high-speed facsimiles and the like.
（発明の構成）
本発明は、少なくとも受光部としては、バイアス印加さ
れた薄膜受光素子と、ドレインまたはソース接地の薄膜
トランジスタを１つの画素とし、１次元に多数配置した
ものを、マトリックス結線、または各画素に１個ずつの
スイッチング素子によって高速読み取シを行うようにし
たものである。(Structure of the Invention) The present invention provides at least a light-receiving section in which a bias-applied thin-film light-receiving element and a drain- or source-grounded thin-film transistor are arranged one-dimensionally in large numbers in a matrix connection or each High-speed reading is performed using one switching element for each pixel.
（実施例の説明）
第２図は本発明による１次元光電変換装置の一実施例の
回路構成を示すもので、Ｃ２０１〜Ｃ２６４は共通電極
側スイッチ％ ８２０１〜５２３２は個別電極側スイッ
チを示し、ここまでの構成は第１図に示した従来のもの
と同じである。本発明ではａ−阻：Ｈ受光素子Ｄ２０１
〜Ｄ２３２を用い、バイアス抵抗Ｒ２０１〜Ｒ２３２に
よってバイアス印加され、これらによって配分された電
圧は、ａ−８ｉ二Ｈによる薄膜トランジスタ（以下、Ｔ
ＰＴと記す。）である電界効果トランジスタＴ２０１〜
Ｔ２３２のゲート部に印加され、光照射によって生じた
電位変化をＴＰＴのドレインまたはソース側の負荷抵抗
Ｌ２を通じて出力として読み出すものである。(Description of Embodiment) FIG. 2 shows a circuit configuration of an embodiment of a one-dimensional photoelectric conversion device according to the present invention, in which C201 to C264 are common electrode side switches, 8201 to 5232 are individual electrode side switches, The configuration up to this point is the same as the conventional one shown in FIG. In the present invention, the a-block:H light receiving element D201
~ D232 is used, bias is applied by bias resistors R201 ~ R232, and the voltage distributed by these is applied to a thin film transistor (hereinafter T
It is written as PT. ) field effect transistor T201~
It is applied to the gate portion of T232, and the potential change caused by light irradiation is read out as an output through the load resistor L2 on the drain or source side of the TPT.
第３図はａ−８ｉ：Ｈ受光素子の電極構成を示す本ので
、厚さ約０．６μｍのａ−８ｉ：Ｈ膜３２Ｖｃ、くし形
電極３１を形成する。電極の幅は１０／ｊｍｓ素子サイ
ズは９０４ｍＸ１２０μｍ１素子間隔は１４０／ｊｍと
した。FIG. 3 shows the electrode structure of an a-8i:H light receiving element, and an a-8i:H film 32Vc with a thickness of about 0.6 μm and a comb-shaped electrode 31 are formed. The width of the electrode was 10/jms, the element size was 904 m x 120 μm, and the distance between each element was 140/jm.
第４図はＴＰＴの断面図を示し、基板４１上にＭ。FIG. 4 shows a cross-sectional view of TPT, with M on a substrate 41.
ゲート電極４２を形成し、Ｓｉ３Ｎ、絶縁ＨＡ ４３
トａ−８ｉ：Ｈ膜４４を形成し、その上にソース、ドレ
イン電極４５．４６を形成する。この時、電極とのオー
ミック接触を得るためｎ＋層を介在させる。A gate electrode 42 is formed, and Si3N, insulating HA 43 is formed.
A-8i:H film 44 is formed, and source and drain electrodes 45 and 46 are formed thereon. At this time, an n+ layer is interposed to obtain ohmic contact with the electrode.
この時のＢ ｉ ３ Ｎ４絶縁層、ａ−８ｉ：Ｈ膜の製
造榮件を下表に示す。The manufacturing conditions for the B i 3 N4 insulating layer and the a-8i:H film are shown in the table below.
表
第５図は、第４図に示したＴＰＴのチャンネル長１０μ
ｍ、ｆヤンネル幅２００μｍの場合のトランジスタ特性
を示すもので、横軸はゲート・ソース間電圧ＶＧＳ 、
縦軸はドレイン電流ＩＤ８を示し、ｖＤ ＝ １２Ｖ。Table 5 shows the TPT channel length 10 μ shown in FIG. 4.
This shows the transistor characteristics when the m and f channel width is 200 μm, and the horizontal axis is the gate-source voltage VGS,
The vertical axis shows the drain current ID8, vD = 12V.
ＶＧＳ ＝ １２Ｖ ”？’ （Ｄ トレイ７ ＩＥ
流ＩＩ）Ｂ ｕ ２ Ｘ １０−’ Ａ 以上のオン電
流が流れている。VGS = 12V "?' (D Tray 7 IE
Flow II) An on-current of B u 2 × 10−′ A or more is flowing.
次に、本実施例で用いた受光部にはＴＰＴの、ａ−８ｉ
：■と同一の膜を用いる。この場合、１〜２Ｖμｍの電
圧印加で１００ ｌｘの照度のｉｍａｅｅの元パルスで
電流変調度（明部電流／暗部電流） ＝ １０以上が得
られる。但し、この時の切地抵抗４Ｘ１５５ρ・は（１
００Ｊｘ時）、暗比抵抗は８Ｘ１０８ρ・硼である。ま
た、電極下にａ−ｓｉ：Ｈと８１３Ｎ４膜を介して、Ｔ
ＰＴ同様に全面ゲート電極を用いて受光素子ａ−８ｉ：
Ｈの膜の表面状態を、例えば電極を０電位に接地するこ
とによ多制御すれば、安全性、再現性も向上できる。Next, the light receiving section used in this example was made of TPT, a-8i
: Use the same membrane as ■. In this case, current modulation degree (bright area current/dark area current) = 10 or more can be obtained with the original pulse of imaee with an illuminance of 100 lx by applying a voltage of 1 to 2 V .mu.m. However, the cutting resistance 4×155ρ・ at this time is (1
00Jx), the dark specific resistance is 8X108ρ. In addition, T
Photodetector a-8i using a full gate electrode like PT:
Safety and reproducibility can also be improved by controlling the surface condition of the H film by, for example, grounding the electrode to zero potential.
バイアス抵抗には５００にρ〜５Ｍρが必要である。The bias resistor requires 500 to 5Mρ.
これには１０２Ω・儂の一層を用いる。０．４μｍの膜
厚では５０μｍ幅ＸＸ１００Ａ長のパターン化で５Ｍρ
が器の人力抵抗も含めて０．５Ｋｇとすれば、入力電圧
的１０ｍＶが得られ、この時のパルス立上りは、約１２
μｇｅｅであった。これはマトリックス配線の多層配線
部の上下配線間の容ｉが約９０９Ｆと、入力の増幅器の
スイッチの入力容量が約１０ｐＦ、増幅器の入力抵抗１
０にΩからの予測値と＃１は一致する。For this, I use a layer of 102Ω. With a film thickness of 0.4 μm, patterning with a width of 50 μm and a length of 100 A results in 5 Mρ.
If the resistance is 0.5Kg including the human resistance of the device, an input voltage of 10mV will be obtained, and the pulse rise at this time will be approximately 12
It was μgee. This means that the capacitance i between the upper and lower wiring of the multilayer wiring part of the matrix wiring is approximately 909F, the input capacitance of the input amplifier switch is approximately 10pF, and the input resistance of the amplifier is 1
The predicted value from Ω matches 0 with #1.
第６図は本発明の１次元光！変換装置の一実施例の配置
図、第７図はその断面図を示す。Figure 6 shows the one-dimensional light of the present invention! FIG. 7 is a layout diagram of an embodiment of the converting device, and a cross-sectional view thereof is shown.
第６図において、６１はａ−８ｔ：Ｈ受光部、６２はバ
イアス抵抗でＴＰＴに用いるｎ 層を用い、６３はＴＦ
Ｔ部、６４はケート＠ｈ、６５はドレイン電極であり、
両電極６４および６５の下には絶縁層として紫外線硬化
樹脂等が用いられる。また、第７図において、７１はＳ
ｉ ３Ｎ４膜、７２はａ−８ｉ：Ｈ，７３はｎ層、７
４はＴＦＴゲート電極、７５は紫外線硬化樹脂等の絶縁
層、７６はゲート部アルミ配線、７７はａ−８ｉ：Ｈ用
くし形を極、７８はソース電極を示す。In FIG. 6, 61 is an a-8t:H light receiving section, 62 is a bias resistor using an n layer used for TPT, and 63 is a TF
T part, 64 is a gate@h, 65 is a drain electrode,
Under both electrodes 64 and 65, an insulating layer made of ultraviolet curing resin or the like is used. Also, in FIG. 7, 71 is S
i 3N4 film, 72 is a-8i:H, 73 is n layer, 7
Reference numeral 4 indicates a TFT gate electrode, 75 an insulating layer such as an ultraviolet curable resin, 76 an aluminum wiring for a gate portion, 77 a pole for a-8i:H, and 78 a source electrode.
なお、本発明では受光部とＴＦＴ部には同一電源を用い
たが、独立電のとし、た方がバイアス電源を任意に設定
できる点で、素子のはらつきにも対応できるため便利で
ある。In the present invention, the same power source is used for the light receiving section and the TFT section, but it is more convenient to use independent power sources because the bias power source can be set arbitrarily and fluctuations in the elements can be dealt with.
このようにして得られる＠Ｎｆｊ１１次元イメージセン
サ−の出力は、１００Ｊｘの受光面照度の光学系を用い
て、８７Ｎ比２０ｄＢ以上で２ ｍ ｓｅｃ／ｊ！ｉｎ
ｅ以上の高速読み取シが可能であった。The output of the @Nfj 11-dimensional image sensor obtained in this way is 2 m sec/j with an 87N ratio of 20 dB or more using an optical system with a light-receiving surface illuminance of 100 Jx! in
It was possible to read at higher speeds than e.
また、上記説明ではＴＦＴ Ｉｃ ａ−８１：Ｈを用い
たが、他のＴＰＴ例えばｐｏｌｌ −Ｓｔ ＴＦＴを用
いれば、よシ高速化が可能であり、また、Ｃｄ８ｅ、
Ｔｅ、 ’ｒｐ”ｒも同様に用いることができる。In addition, although TFT Ic a-81:H was used in the above explanation, it is possible to increase the speed by using other TPTs, such as poll-St TFTs, and Cd8e,
Te, 'rp'r can also be used in the same way.
（発明の効果）
以上、説明したように１本発明によれは内部抵抗の大き
な受光素子を、薄膜トランジスタによって電源増幅又は
インピーダンス変換をすることによって１２ ｍ ｓｅ
ｃ／Ｊｉｎｅ以上のコンパクトな密着屋の１次元センサ
ーを提供することが可能となった。(Effects of the Invention) As explained above, according to the present invention, a light receiving element having a large internal resistance can be converted to 12 m se by amplifying the power supply or converting the impedance using a thin film transistor.
It is now possible to provide a one-dimensional sensor that is more compact than c/Jine.
第１図は従来のＣｄ８Ｓｅを用いた１次元センサーの回
路構成を示す図、第２図は本発明の一実施例の回路構成
図、第３図はａ−８１：Ｈ受光素子の電極構成図、第４
図はＴＰＴの断面図、第５図は本発明によるＴＰＴのト
ランジスタ特性図、第６図および第７図は本発明の一実
施例の配置図およびその断面図である。
Ｃ２Ｏ１−Ｃ２６４・・・・・・・・・共通電極側スイ
ッチ、８２０１〜８２３□・・・・・・・・・個別電極
側スイッチ、Ｄ２０１−Ｄ２３２ ””””−ａ−８ｉ
： １（受光素子 Ｒ２０１〜Ｒｚ’ａｚ・・・・・
・・・・バイアス抵抗、Ｔ２Ｇ１〜Ｔ２３□・・・・・
・・・・電界効果トランジスタ、３１・・・・・・・・
・ くし形電極、 ３２・・・・・・・・・ ａ−８１
：Ｈｇ、４１・・・・・・・・・基板、 ４２・・・・
・・・・・ＭＯゲート電極、４３・・・・・・・・・５
ｉＢＮ４絶縁膜、４４・・・・・・・・・ ａ−８ｔ
：Ｈｌ［，４５・・・・・・・・・ソース電極、４６・
・・・・・・・・ ドレイン電極、６１・・・・・・・
・・ ａ−８ｔ：Ｈ受光部、６２・・・・・・・・・バ
イアス抵抗、 ６３・・・・・・・・・ＴＦＴ部、６４
・・・・・・・・・ゲート電極、６５・・・・・・・・
・ ドレイン電極、７１、、−−−−−・＝ ＳｉａＮ
４１ｍ、 ７２・・・・・−ａ−８ｔ ：Ｈ１７３・・
・・・・・・・ ｎ層、７４・・・・・・・・・ＴＰＴ
ゲート電極、７５・・・・・・・・・紫外線硬化樹脂等
の絶縁層、７６・・・・・・・・・ケー）ｌｕｌｌアル
ミ配線、７７・・・・・・・・・ ａ−８ｉ：Ｈ用＜Ｌ
形！ｆｆｌ、７８・・・・・・・・・ソース電極。
第１図
第３図
第４図
第５図
Ｖｏｓ （ケ゛−ト・ソー又１５（庄）第６図 第７図
手続補正書（方式）
％式％
１・事件の表示 特願昭５８−１９８２０４号２、発
明 の名称
１次元光電変換装置
３ 補正をする者
事件との関係 出願人
住所 大阪府門真市大字門真１００６番地名称 （５８
２）松下電器産業株式会社代表者 山 下 俊 彦
５ 手続補正指令書 の日付
＼、
８、補正の内容 明細書の浄書（内容の変更なし）。
以 上Fig. 1 is a diagram showing the circuit configuration of a conventional one-dimensional sensor using Cd8Se, Fig. 2 is a circuit diagram of an embodiment of the present invention, and Fig. 3 is an electrode configuration diagram of the a-81:H light receiving element. , 4th
5 is a sectional view of a TPT, FIG. 5 is a transistor characteristic diagram of the TPT according to the present invention, and FIGS. 6 and 7 are a layout diagram and a sectional view thereof of an embodiment of the present invention. C2O1-C264......Common electrode side switch, 8201-823□......Individual electrode side switch, D201-D232 """"-a-8i
: 1 (light receiving element R201~Rz'az...
・・・Bias resistance, T2G1~T23□・・・・・・
...Field effect transistor, 31...
・Comb-shaped electrode, 32・・・・・・・・・ a-81
:Hg, 41......Substrate, 42...
...MO gate electrode, 43...5
iBN4 insulation film, 44...... a-8t
:Hl[, 45...... Source electrode, 46.
・・・・・・・・・ Drain electrode, 61・・・・・・
...a-8t: H light receiving section, 62......Bias resistor, 63...TFT section, 64
......Gate electrode, 65...
・Drain electrode, 71, --------・=SiaN
41m, 72...-a-8t: H173...
......n layer, 74......TPT
Gate electrode, 75... Insulating layer such as ultraviolet curing resin, 76......K) Lull aluminum wiring, 77... a-8i :For H<L
shape! ffl, 78... Source electrode. Fig. 1 Fig. 3 Fig. 4 Fig. 5 Vos (Kate Somata 15 (Sho)) Fig. 7 Procedural amendment (method) % formula % 1. Indication of case Patent application 1982-1982 Issue 2, departure
Name of one-dimensional photoelectric conversion device 3 Relationship with the case of the person making the amendment Applicant address 1006 Kadoma, Kadoma City, Osaka Prefecture Name (58
2) Toshihiko Yamashita, Representative of Matsushita Electric Industrial Co., Ltd. 5 Date of procedural amendment order＼, 8. Contents of amendment: Engraving of the specification (no change in content). that's all
Claims (1)
、ドレインまたはソース接地の薄膜トランジスタを１つ
の１ｉｌｊ素としたことを特徴とする１次元光電変換装
置。1. A one-dimensional photoelectric conversion device comprising a thin film light receiving element to which a bias is applied to at least a light receiving part and a thin film transistor whose drain or source is grounded as one 1ilj element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58198204A JPH0624234B2 (en) | 1983-10-25 | 1983-10-25 | One-dimensional photoelectric conversion device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58198204A JPH0624234B2 (en) | 1983-10-25 | 1983-10-25 | One-dimensional photoelectric conversion device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6091666A true JPS6091666A (en) | 1985-05-23 |
| JPH0624234B2 JPH0624234B2 (en) | 1994-03-30 |
Family
ID=16387208
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58198204A Expired - Lifetime JPH0624234B2 (en) | 1983-10-25 | 1983-10-25 | One-dimensional photoelectric conversion device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0624234B2 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62290170A (en) * | 1986-06-07 | 1987-12-17 | Canon Inc | Photoelectric conversion device |
| JPS632377A (en) * | 1986-06-23 | 1988-01-07 | Canon Inc | Photoelectric conversion device |
| EP0272152A2 (en) * | 1986-12-18 | 1988-06-22 | Canon Kabushiki Kaisha | Signal reading out circuit |
| US9698184B2 (en) | 2014-07-23 | 2017-07-04 | Nlt Technologies, Ltd. | Image sensor and driving method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56138358A (en) * | 1980-03-31 | 1981-10-28 | Canon Inc | Copy recorder |
| JPS56138966A (en) * | 1980-03-31 | 1981-10-29 | Canon Inc | Photoelectric converter |
-
1983
- 1983-10-25 JP JP58198204A patent/JPH0624234B2/en not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56138358A (en) * | 1980-03-31 | 1981-10-28 | Canon Inc | Copy recorder |
| JPS56138966A (en) * | 1980-03-31 | 1981-10-29 | Canon Inc | Photoelectric converter |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62290170A (en) * | 1986-06-07 | 1987-12-17 | Canon Inc | Photoelectric conversion device |
| JPS632377A (en) * | 1986-06-23 | 1988-01-07 | Canon Inc | Photoelectric conversion device |
| EP0272152A2 (en) * | 1986-12-18 | 1988-06-22 | Canon Kabushiki Kaisha | Signal reading out circuit |
| US4967067A (en) * | 1986-12-18 | 1990-10-30 | Seiji Hashimoto | Signal read-out circuit which lowers diffusion capacitance by limiting emitting current with resistive elements |
| US9698184B2 (en) | 2014-07-23 | 2017-07-04 | Nlt Technologies, Ltd. | Image sensor and driving method thereof |
| US9865644B2 (en) | 2014-07-23 | 2018-01-09 | Nlt Technologies, Ltd. | Image sensor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0624234B2 (en) | 1994-03-30 |
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