JPS59108460A - Solid-state image pickup device - Google Patents
Solid-state image pickup deviceInfo
- Publication number
- JPS59108460A JPS59108460A JP57217753A JP21775382A JPS59108460A JP S59108460 A JPS59108460 A JP S59108460A JP 57217753 A JP57217753 A JP 57217753A JP 21775382 A JP21775382 A JP 21775382A JP S59108460 A JPS59108460 A JP S59108460A
- Authority
- JP
- Japan
- Prior art keywords
- solid
- sit
- readout
- state image
- photosensitive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011159 matrix material Substances 0.000 claims abstract description 6
- 238000003384 imaging method Methods 0.000 claims description 22
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000003287 optical effect Effects 0.000 description 9
- 238000002955 isolation Methods 0.000 description 7
- 239000000758 substrate Substances 0.000 description 6
- 230000003321 amplification Effects 0.000 description 5
- 238000003199 nucleic acid amplification method Methods 0.000 description 5
- 238000000926 separation method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000035945 sensitivity Effects 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14679—Junction field effect transistor [JFET] imagers; static induction transistor [SIT] imagers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/112—Devices sensitive to infrared, visible or ultraviolet radiation characterised by field-effect operation, e.g. junction field-effect phototransistor
- H01L31/1124—Devices with PN homojunction gate
- H01L31/1126—Devices with PN homojunction gate the device being a field-effect phototransistor
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は固体撮像装置に関するものである。 ・従来固
体撮像装置としてはＯＯＤ等の電荷転送素子を用いるも
のや、ＭＯＳ）ランジスタを用いるものなどが広く用い
られている。しかし、これらの固体撮像装置は電荷転送
時に［４の洩れがあること、光検出感度が低いこと、集
積度が上から・・ないことなどの問題がある。このよう
な間類を一′挙に解決するものとして、静電誘導トラン
ジスタ（５ｔａｔｉＯＩｎ６ｕａｔｉｏｎ Ｔｒａｎｓ
ｌｓｔｏｒの頭文字をとってＳＩＴと呼ばれている）を
用いたものが新たに提案されている。例えば特開昭５５
−１５２２９号 −゛公報には、マトリックス状に配列
したＳＩＴのソースを行導線に接続し、ドレインを列導
線に接続し、ゲートをクリア導線に接続した固体撮像装
置が示されている。また、このような固体撮像装置をさ
らに発展させたものとして、ゲートにコンテ“□ンサを
接続したものが考えられている。第１図ＡおよびＢはこ
のよりなＳＩＴの構造を示す断面図および平面図である
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a solid-state imaging device. - Conventional solid-state imaging devices that use charge transfer devices such as OOD, and devices that use MOS (MOS) transistors are widely used. However, these solid-state imaging devices have problems such as leakage during charge transfer, low photodetection sensitivity, and low degree of integration. Static induction transistors (5tatiOIn6uation Transistors) can be used to solve these problems all at once.
A new method using the SIT (SIT, an acronym for Lstor) has been proposed. For example, Japanese Patent Application Publication No. 55
No. 15229-1 discloses a solid-state imaging device in which the sources of SITs arranged in a matrix are connected to row conductors, the drains are connected to column conductors, and the gates are connected to clear conductors. Furthermore, as a further development of such a solid-state imaging device, one in which a container is connected to the gate is considered. FIG.
第１図ＡおよびＢに示すように、Ｐ型基板１上にＳＩＴ
のソースを構成するｎ型埋込層２を形 １成すると共に
ｎ−型エピタキシャル層８を成長させ、このエピタキシ
ャル層８の表面に熱拡散法等によりｎ＋ドレイン領域４
お工びＰ＋ゲート領域５を形成する。ドレイン領域４の
拡散深さは、これとソース領域２との間に形成するチャ
ンネル領域・の開閉を確実に行々うために、ゲート領域
５の拡”散深さよりも浅くする。ドレイン領域４にはド
レイン電極６を接合して設け、ゲート領域５には絶縁層
７を介してゲート電極８を設けることによりすなわちＭ
ＩＳ構造とすることによりゲートコンデンサを形成する
。また、隣接するＳＩＴは、それらの間にエピタキシャ
ル層８を分離するように絶縁層９を設けて相互に電気的
に分離する。As shown in FIGS. 1A and 1B, the SIT
At the same time as forming an n-type buried layer 2 constituting a source of
A rough P+ gate region 5 is formed. The diffusion depth of the drain region 4 is made shallower than that of the gate region 5 in order to ensure the opening and closing of the channel region formed between the drain region 4 and the source region 2. A drain electrode 6 is bonded to and provided on the gate region 5, and a gate electrode 8 is provided on the gate region 5 with an insulating layer 7 interposed therebetween.
A gate capacitor is formed by forming an IS structure. Further, adjacent SITs are electrically isolated from each other by providing an insulating layer 9 between them so as to separate the epitaxial layer 8.
このような構成においては、光入力のない定常状態にお
いてゲート領域５をソース領域２に対しＭで逆バイアス
に設定すわば、チャンネル領域は空乏化されるから、ソ
ースドレイン間が順方向にバイアスされてもソースドレ
イン間には電流が流れない。このような状態で、光入力
によって正孔−電子対が発生すると、電子はソース領域
２またはＩ・ドレイン領域４に向かい蓄積またははき出
さね、正孔はゲート領域５に蓄積されてＭＩＳ構造によ
るゲートコンデンサを充電し、ゲート電位をΔｖＧだけ
変化させる。ここで、ゲートコンデンサノ容量と、エピ
タキシャル層８に対する空乏層容址と−・・・の和を０
゜、光入力によって発生され、ゲート領１域５に蓄積さ
れた電荷量をＱＬとすると、ΔＶｏ＝ ＱＩ、／、ｏと
なる。成る蓄積時間が経過した後、ゲート電極８にゲー
ト読出しパルスφＧを与えると、ゲート電位はφＧにΔ
ｖｏが加わったものとな。In such a configuration, if the gate region 5 is set to a reverse bias of M with respect to the source region 2 in a steady state with no optical input, the channel region is depleted, so that the source-drain region is forward biased. Even if the current does not flow between the source and drain. In such a state, when hole-electron pairs are generated by optical input, the electrons are accumulated or expelled toward the source region 2 or the I/drain region 4, and the holes are accumulated in the gate region 5 and connected to the gate by the MIS structure. Charge the capacitor and change the gate potential by ΔvG. Here, the sum of the capacitance of the gate capacitor, the capacity of the depletion layer for the epitaxial layer 8, and -... is 0.
If the amount of charge generated by optical input and accumulated in the gate region 1 region 5 is QL, then ΔVo=QI,/,o. When a gate read pulse φG is applied to the gate electrode 8 after an accumulation time of
It's like adding vo.
す、ゲート領域５とドレイン領域４との間の電位は低下
して空乏層が減少し、ソース−ドレイン間に光入力に対
応したドレイン電流が流れる。このドレイン電流はＳＩ
Ｔの増幅作用のためΔｖｏが増幅度倍されたものとなり
、大きなものとなる。１１．。Then, the potential between the gate region 5 and the drain region 4 decreases, the depletion layer decreases, and a drain current corresponding to the optical input flows between the source and the drain. This drain current is SI
Due to the amplification effect of T, Δvo is multiplied by the degree of amplification and becomes large. 11. .
た、ＳＩＴのソースとじレインとを入れ替えても同様の
動作をするものである。Furthermore, even if the source and the rain of the SIT are exchanged, the same operation will occur.
第２図人は上述したＳＩＴをマトリックス状に配列して
構成した固体撮像装置の回路構成を示すものであり、第
２図Ｂは同じくその動作を説明す。FIG. 2 shows a circuit configuration of a solid-state imaging device constructed by arranging the above-mentioned SITs in a matrix, and FIG. 2B similarly explains its operation.
るための信号波形図である。各５ＩＴＩＯ−１，１０−
２・・・・・・は上述した↓うにノーマリオフ形のｎチ
ャネルＢＩＴで、光入力に対する出力ビデオ信号をＸＹ
アドレス方式で読み出すようにしている。各画素を構成
するＪＴのソースは共通のリセット−１、線１１に接続
してバイアス電圧ｖ８を印加し、Ｘ方□向に配列された
一行のＳＩＴ群のゲートは、行ライン１２−１．１２−
２・・・・・・を介して垂直選択シフトレジスタ１Ｂに
接続する。また、Ｙ方向に配列さねた一列のＳＩＴ群の
ドレインは列ライン１４−１゜１４−２・・・・・・に
接続し、とわらの列ラインはそれぞれ水平選択シフトレ
ジスター５によって選択駆動される水平選択トランジス
ター６−１．１６−２・・・を介してビデオライン１７
に共通に接続する。FIG. Each 5ITIO-1,10-
2... is the normally-off type n-channel BIT mentioned above, and outputs the output video signal for the optical input by XY.
It is read using the address method. The sources of the JTs constituting each pixel are connected to the common reset-1 line 11 to apply a bias voltage v8, and the gates of the SIT groups in one row arranged in the X direction are connected to the row line 12-1. 12-
2... is connected to the vertical selection shift register 1B. In addition, the drains of the SIT groups in one row arranged in the Y direction are connected to the column lines 14-1, 14-2, etc., and the other column lines are selectively driven by the horizontal selection shift register 5. The video line 17 is connected to the video line 17 through horizontal selection transistors 6-1, 16-2...
Commonly connected to.
このビデオライン１７には負荷抵抗１８を経て電゛−圧
Ｖ を印加する＠
今、リセット線１１へのバイアス電圧ｖｓを適切に、例
えば零ボルトに設定して、１つのＳＩＴ画素の出力が読
出される場合について考えてみる。A voltage V is applied to this video line 17 via a load resistor 18. Now, set the bias voltage vs to the reset line 11 appropriately, for example, to zero volts, and read out the output of one SIT pixel. Let's think about a case where this happens.
例えば、垂直選択シフトレジスター８から行うイ□ン１
２−１に行選択パルスφＧ１を供給している期間に、水
平選択シフトレジスター５から水平選択トランジスター
６−ＩＫｉ出しパルスφＤ□を印加すると、３ＩＴ１０
−１が選択され、この５ＩＴＩＯ−１には負荷抵抗１８
、ビデオライン１７、水平選択パトランジスター６−１
および列ライン１４−１を経１てドレイン電流が流れ、
出力端子１９に出力電圧■ｏｕｔが発生する。上述した
ようにこのドレイン電流はゲート電圧の関数であり、こ
のゲート電圧は光入力の関数と々るから、暗時の出力電
圧からの□増加分Δｖｏｕ ｔは光入力に対応した電圧
となる。しかも、この電圧Δ■ｏｕｔはＳＩＴの増幅作
用によりΔｖＧが増幅度倍された大きなものとなる。次
に、水平選択シフトレジスター５から水平選択トランジ
スタ１６−２に読出しパルスφＤｚ”与えてＳ Ｉ Ｔ
”’１０−２の読出しを行ない、−桁分の読出しが終
了したら、垂直選択シフトレジスター８から次の行に行
選択パルスφＧ２を与えて、その行の１３ＩＴを１諏次
に読出す。For example, input 1 is performed from vertical selection shift register 8.
When the horizontal selection transistor 6-IKi output pulse φD□ is applied from the horizontal selection shift register 5 to the horizontal selection transistor 6-IKi during the period when the row selection pulse φG1 is supplied to the line selection transistor 2-1, 3IT10
-1 is selected, and this 5ITIO-1 has a load resistance of 18
, video line 17, horizontal selection transistor 6-1
and a drain current flows through the column line 14-1,
An output voltage ■out is generated at the output terminal 19. As described above, this drain current is a function of the gate voltage, and since this gate voltage is a function of the optical input, the □ increase Δvout from the output voltage in the dark becomes a voltage corresponding to the optical input. Moreover, this voltage Δ■out becomes a large value, which is ΔvG multiplied by the amplification degree, due to the amplification effect of the SIT. Next, a read pulse φDz" is applied from the horizontal selection shift register 5 to the horizontal selection transistor 16-2, and S I T
``'10-2 is read out, and when the reading of -digits is completed, the row selection pulse φG2 is applied to the next row from the vertical selection shift register 8, and 13IT of that row is read out one by one.
しかしながら、−上述した固体撮像装置において１は、
入射光の強度が高いとＱＬが非常に大きくなってΔｖＧ
が高くなり、始めに設定した逆バイアス値Ｖに対し、ｖ
Ｇ十Δ■Ｇ（ΔｖＧ〉０）がＳＩＴの設定ソース電位ｖ
ｓに対するピンチオフ電圧Ｖ、を上まわると、そのＳＩ
Ｔが選択されていなくてもこれ−・・が不所望に導通し
て他の選択している行ラインか□ら流れ出次信号電流と
共に同一の列ラインを経て電、流が流れ、画素間の信号
干渉を起す不具合がある。このため、か＼る固体撮像装
置は露光量に制限があり、実用上間順であった。However, in the solid-state imaging device described above, 1 is
When the intensity of the incident light is high, QL becomes very large and ΔvG
becomes higher, and with respect to the initially set reverse bias value V, v
G+Δ■G (ΔvG〉0) is the set source potential v of SIT
When the pinch-off voltage V for s is exceeded, its SI
Even if T is not selected, this current becomes undesirably conductive and flows from the other selected row line □.The current flows along with the signal current through the same column line, and the current flows between the pixels. There is a problem that causes signal interference. For this reason, such solid-state imaging devices have limitations on the amount of exposure, and are limited in practical terms.
本発明の目的は、上述した不具合を解決し、入射光の強
度が高くても画素間の信号干渉を起すことなく、゛各画
素信号を有効に読出し得るよう適切に構成した固体撮像
装置を提供しようとするものである。An object of the present invention is to solve the above-mentioned problems and provide a solid-state imaging device appropriately configured to effectively read out each pixel signal without causing signal interference between pixels even when the intensity of incident light is high. This is what I am trying to do.
本発明の固体撮像装置は、入射光を受光する感光用トラ
ンジスタと、この感光用トランジスタでの光電変換出力
を選択的に読出す読出し用トランジスタとを有し、それ
らの主電流通路を直列に接続して成る固体撮像素子を、
複数の行線および列ｌ線で構成されるマトリックスの各
交点にそれぞれ設け、これら行線および列線に前記固体
撮像素子の読出し用トランジスタを接続し、その感光用
トランジスタをリセット線に接続したことを特徴とする
ものである。The solid-state imaging device of the present invention has a photosensitive transistor that receives incident light and a readout transistor that selectively reads out the photoelectric conversion output of this photosensitive transistor, and their main current paths are connected in series. A solid-state image sensor made of
A readout transistor of the solid-state image sensor is provided at each intersection of a matrix composed of a plurality of row lines and a plurality of column lines, and a readout transistor of the solid-state image sensor is connected to the row line and column line, and the photosensitive transistor is connected to a reset line. It is characterized by:
以下図面を参照して本発明の詳細な説明する。′第８図
ＡおよびＢは本発明の固体撮像装置に用いる固体撮像素
子の一例の構成を示す断面図および平面図である。本例
では、感光用トランジスタ２１および読出し用トランジ
スタ２２を共にＳＩＴ構造として同−基板に形成する。The present invention will be described in detail below with reference to the drawings. 'FIGS. 8A and 8B are a sectional view and a plan view showing the structure of an example of a solid-state imaging device used in the solid-state imaging device of the present invention. In this example, both the photosensitive transistor 21 and the readout transistor 22 are formed on the same substrate as an SIT structure.
すなわち、Ｐ型基板２８上に感光用５ＩＳ２］のドレイ
ン領域および読出し用５ＩＴ２２のソース領域を構成す
るｎ＋埋込層２４を形成すると共に、これら基板２８お
よび埋込層２４上にｎ−エピタキシャル層ｇ５を １パ
成長させ、このエピタキシャル層２５の表面に、感光用
５ＩＴ２１を構成するｎ ソース領域２６、Ｐ＋ゲート
領域２７および読出し用ＳＩＴ’２を構成するｎ＋ドレ
イン領域２８、Ｐ＋ゲート領域２９をそれぞれ熱拡散法
等により形成する。感光用 １ＳＩＴ２１および続出し
用５ＩＴ２２は、５ＩＴ２１のドレイン領域および５Ｉ
Ｔ２Ｂのソース領域を共通のｎ＋埋込層２４をもって構
成する以外は、とのｎ＋埋込層２４からエピタキシャル
層２５の表面に亘って設けた絶縁層８０によって電気的
に分離２・・することによりそれらの主電流通路を直列
に接続□し、また隣接する固体撮像素子間はＰ型基板２
Ｂからエピタキシャル層２５の表面に亘って同様に絶縁
層８０を設けて相互に電気的に分離する。感光用ＳＩ’
１４１のソース領域２６にはソース電極８１を接合して
設け、また読出し用ＳＩＴ２ｇのドレイン領域２８およ
びゲート領域２９にｕ −ｔ ｈ。That is, an n+ buried layer 24 constituting the drain region of the photosensitive 5IS2] and the source region of the readout 5IT22 is formed on the P-type substrate 28, and an n- epitaxial layer g5 is formed on the substrate 28 and the buried layer 24. The n source region 26 and the P+ gate region 27 constituting the photosensitive 5IT 21 and the n+ drain region 28 and the P+ gate region 29 constituting the readout SIT'2 are heated on the surface of the epitaxial layer 25, respectively. Formed by a diffusion method or the like. 1SIT21 for photosensitive and 5IT22 for continuous printing are connected to the drain region of 5IT21 and 5I
Except for configuring the source region of T2B with a common n+ buried layer 24, it is electrically isolated by an insulating layer 80 provided from the n+ buried layer 24 to the surface of the epitaxial layer 25. Their main current paths are connected in series □, and a P-type substrate 2 is connected between adjacent solid-state image sensors.
An insulating layer 80 is similarly provided from B to the surface of the epitaxial layer 25 to electrically isolate them from each other. SI' for photosensitive
A source electrode 81 is connected to the source region 26 of 141, and u-th is connected to the drain region 28 and gate region 29 of the read SIT 2g.
ぞれドレイン電極８２およびゲート電極８Ｂを接合して
設け、その他の表面は表面絶縁膜８４で被覆する。すな
わち、本例では感光用ＳＩＴ ２１に′□はゲート電極
を設けない。したがって、ゲート電極による透過光量損
失がないから、短波長感度を向上させることができる。A drain electrode 82 and a gate electrode 8B are connected to each other, and the other surfaces are covered with a surface insulating film 84. That is, in this example, the photosensitive SIT 21 is not provided with a gate electrode. Therefore, since there is no loss in the amount of transmitted light due to the gate electrode, short wavelength sensitivity can be improved.
また、本例のように感光用５ＩＴ２１と読出し用５ＥＴ
２２との分離お↓びこれら感光用ＳＩＴと読出し用ＳＩ
Ｔとから成る −固体撮像素子間の分離を絶縁層８０に
↓つて行えば、それらの電気的分離をほぼ完全にできる
から電流の制御性、増幅特性が良好となる。In addition, as in this example, 5IT21 for photosensitive and 5ET for reading
Separation from 22 and these photosensitive SIT and readout SI
By separating the solid-state image sensing elements consisting of T by using the insulating layer 80, their electrical isolation can be almost completely achieved, resulting in good current controllability and amplification characteristics.
第４１凶ＡおよびＢは本発明の固体撮像装置に用いる固
体撮像素子の他の例の構成を示す断面図お−・・よび平
面図である。本例では、感光用５ＩＳ２１と゛続出し用
５ＥＴ２．２との分離およびこれら感光用ＢＩＴと読出
し用ＳＩＴとから成る固体撮像素子間の分離を、上述し
た絶縁層８０によらず、ｎ−エピタキシャル層２５の表
面に゛Ｐ＋分離ゲート領域□８６を形成すると共にこの
分離ゲート領域８６に分離ゲート電極８７を接合して設
け、この分離ゲート電極８７に所定の電圧を印加するこ
とに工り分離ゲート領域８６下のエピタキシャル層ｚ５
に空乏層を形成して行なうようにした点のみが、第１′
８図のものと異なる本のであり、第８図に示す符号と同
一符号は同一のものを表わす。この↓うに分離ゲート領
域８６を形成し、これにノ（イアスを与えることにより
形成される空乏層によって素子間の分離および素子中の
感光用ＳＩＴ？に１と読出し１・用５ＩＴ２２との電気
的分離を行なう場合には、素子の高密度化が計りる利点
がある。41st figures A and B are a cross-sectional view and a plan view showing the structure of another example of the solid-state imaging device used in the solid-state imaging device of the present invention. In this example, the separation between the photosensitive 5IS 21 and the continuous output 5ET 2.2 and the solid-state image sensing device consisting of the photosensitive BIT and the readout SIT is performed using an n-epitaxial layer instead of the above-mentioned insulating layer 80. 25, a P+ isolation gate region 86 is formed, an isolation gate electrode 87 is bonded to this isolation gate region 86, and a predetermined voltage is applied to this isolation gate electrode 87. Epitaxial layer z5 below 86
The only point where the depletion layer is formed in the first
This book is different from the one shown in FIG. 8, and the same reference numerals as those shown in FIG. 8 represent the same things. An isolation gate region 86 is formed in this manner, and a depletion layer formed by applying a voltage to the isolation gate region 86 isolates the elements and electrically connects the photosensitive SIT? In the case of separation, there is an advantage that the density of elements can be increased.
第５図は本発明の固体撮像装置の要部の一例の構成を示
す回路図である。本例では、第８図あるいは第４図に示
した固体撮像素子を同一基板に多−・・数個マトリック
ス状に形成したものを用いる。各□固体撮像素子４０−
１．４０−２．・・・の感光用ＳＩＴのソースは共通の
リセット線４１に接続してバイアス電圧Ｖを印加し、Ｘ
方向に配列された一行の素子群の読出し用ＳＩＴのゲー
トは、行ライン４２−１．４２−２．・・・を介して垂
直選択シフトレジスタ４Ｂに接続する。また、Ｙ方向に
配列された一列の素子群の読出し用ＳＩＴのドレインは
列 ゛ライン４４−１．４４−２．・・・に接続し、こ
れらの列ラインはそれぞれ水平選択シフトレジスタ４５
１□′によって選択駆動される水平選択トランジスタ４
６−１．４６−２．・・・を介してビデオライン４７に
共通に接続する。このビデオライン４７には負荷、抵抗
４８を経て電圧Ｖ。ｆ：印加し、垂直選択シフトレジス
タ４Ｂ、水平選択シフトレジスタ４５１を第２図におい
て説明したと同様に制御して出力端子４９から時系列的
な画素情報を得るようにする。FIG. 5 is a circuit diagram showing an example of the configuration of a main part of the solid-state imaging device of the present invention. In this example, a plurality of solid-state imaging devices shown in FIG. 8 or 4 are formed in a matrix on the same substrate. Each □solid-state image sensor 40-
1.40-2. The sources of the photosensitive SITs are connected to the common reset line 41, a bias voltage V is applied, and X
The readout SIT gates of one row of element groups arranged in the row line 42-1, 42-2. ... is connected to the vertical selection shift register 4B. In addition, the drains of the readout SITs of one row of element groups arranged in the Y direction are connected to the columns 44-1, 44-2. ..., and each of these column lines is connected to a horizontal selection shift register 45.
Horizontal selection transistor 4 selectively driven by 1□′
6-1.46-2. . . are commonly connected to the video line 47 via... A voltage V is applied to this video line 47 via a load and a resistor 48. f: is applied, and the vertical selection shift register 4B and horizontal selection shift register 451 are controlled in the same manner as explained in FIG. 2, so that time-series pixel information is obtained from the output terminal 49.
か＼る構成において、ある列ラインが選択された場合、
その列ラインに接続された一列の素子群・・の読出（７
用ＳＩＴのうち、行ラインが選択されて □いる素子の
読出し用ＳＩＴを除き、他の読出し用ＳＩＴはこれと直
列に接続された感光用ＳＩＴのゲート電位が上昇してピ
ンチオフレベル以上に達していても、読出し用ＳＩＴを
介して高いドレイン電位が印加されることはないから、
電流は流れず、したがって画素間の信号干渉は起らない
。また、こ＼で感光用ＳＩＴのゲート電位が更に上昇し
、そのソース電位（リセット線４１に印加するバイアス
電圧ｖｓ）に対して順方向にバイアスされ１°゛てゲー
ト領域に蓄積された一定鎗以上の正孔がソースを通して
はき出されても、感光用ＳＩ’ｌ’のオン動作に結びつ
くことはない。なお、素子のリセットはリセット＋ＩＪ
４１に印加するバイアス電圧ｖ８をパルス的に引下げて
、各感光用ＳＩＴのソース １・−ドレイン間を強制的
に順方向にバイアスすることにより全素子同時に行なう
ことができる。In this configuration, if a certain column line is selected,
Reading out a column of elements connected to that column line (7
Among the readout SITs, except for the readout SIT of the element whose row line is selected □, the other readout SITs have the gate potential of the photosensitive SIT connected in series with it rise to reach the pinch-off level or higher. However, since a high drain potential is not applied via the read SIT,
No current flows, so no signal interference between pixels occurs. Also, at this point, the gate potential of the photosensitive SIT further rises, and the fixed beam accumulated in the gate region is biased in the forward direction by 1° with respect to its source potential (bias voltage vs. applied to the reset line 41). Even if more holes are ejected through the source, they will not turn on the photosensitive SI'l'. In addition, to reset the element, use reset + IJ.
By lowering the bias voltage v8 applied to 41 in a pulse manner and forcibly biasing the source 1 to drain of each photosensitive SIT in the forward direction, it is possible to perform the same operation on all the elements at the same time.
本例においては、入射光の強度が高く感光用ＳＩＴのゲ
ート電位がピンチオフレベル以上になっても、続出用Ｓ
Ｉ’ｌ’が選択されない限り、この−・・・読出し用Ｓ
工Ｔおよび感光用ＳＩＴを通して電流カド流れることは
ないから、画素間の不所望な信号干渉が生じない。また
、各素子を第８図および第４図に示したように、その感
光用ＳＩＴにゲート電極を設けず、これをフローティン
グにして入射光を受光するようにしたから、電極による
入射光、特に短波長成分の透過損失がなく、したがって
分光特性を向上させることができる。In this example, even if the intensity of the incident light is high and the gate potential of the photosensitive SIT exceeds the pinch-off level,
Unless I'l' is selected, this --... read S
Since no current flows through the sensor T and photosensitive SIT, no unwanted signal interference between pixels occurs. Furthermore, as shown in FIGS. 8 and 4, the photosensitive SIT of each element is not provided with a gate electrode and is made floating to receive incident light. There is no transmission loss of short wavelength components, and therefore the spectral characteristics can be improved.
なお、本発明は上述した例にのみ限定されるものではな
く、幾多の変形または変更が可能である８・・例えば上
述した例では固体撮像素子を構成する感光用および読出
し用トランジスタをそれぞれＳＩＴをもって構成したが
、これらをそれぞれ電界効果トランジスタ（ＦＥＴ）を
もって構成することもできるし、一方をＳＩＴ、他方１
ＦＥＴをもって構・成することもできる。また、これら
トランジスタはｎチャンネル型に限らずｎチャンネル型
で構成することもできる。更に、第８図および第４図で
は感光用ＳＩＴ ２１のドレイン領域および読出し用５
ＩＴ２ ｍのソース領域を共通のｎ埋込層２４・・をも
って形成することにより、感光用５ＩＴ２１お１よび読
出し用ＳＩＴ ２２の各主電流通路を直列に接続するよ
うにしたが、各領櫨を分離して形成してこれらを電気的
に接続する等の他の方法により接続することもできる。Note that the present invention is not limited to the above-mentioned example, and can be modified in many ways.8 For example, in the above-mentioned example, the photosensitive and readout transistors constituting the solid-state image sensor are each provided with an SIT. However, each of these can also be configured with a field effect transistor (FET), or one can be configured with an SIT and the other with a field effect transistor (FET).
It can also be constructed using FETs. Further, these transistors are not limited to n-channel type transistors, but may also be configured as n-channel type transistors. Furthermore, in FIGS. 8 and 4, the drain region of the photosensitive SIT 21 and the readout 5
By forming the source region of the IT2m with a common n-buried layer 24..., the main current paths of the photosensitive 5IT21 and the readout SIT22 were connected in series. Connections can also be made by other methods, such as forming them separately and electrically connecting them.
更にまた、第５図においては全ての固体撮像素子４０−
１．４０−１．・・・の感光用ＳＩＴのソースを共通の
リセット線４１に接続して同時にリセットする工うにし
たが、リセット線４１を行毎に分離して行毎にリセット
することもできる。Furthermore, in FIG. 5, all the solid-state image sensors 40-
1.40-1. Although the sources of the photosensitive SITs of .
以上述べたように本発明によれば、入射光の強度が高く
ても画素間の信号干渉を起すことなく、各画素信号を有
効に読出すことができるから、露光量が制限されること
はない。As described above, according to the present invention, each pixel signal can be effectively read out without causing signal interference between pixels even when the intensity of incident light is high, so the exposure amount is not limited. do not have.
第１図ＡおよびＢはＳＩＴの構成を示す断面図および平
面図、
第２図ＡおよびＢはＳＩＴを用いる固体メ像装置の構成
およびその動作ｔ−説明するための回路図および信号波
形図、
第８図ＡおよびＢは本発明の固体撮像装置に用□いる固
体撮像装置の一例の構成を示す断面図および平面図、
第４図Ａお工びＢは同じく他の例の構成を示す断面図お
よび平面図、
第６図は本発明の固体撮像装置の要部の一例の構成を示
す回路図である。
２１・・・感光用ＳＩＴ ２２・・・読出し用ＳＩ
’ｌ’２Ｂ・・・ｐ型基板 ２４・・・ｎ 埋込
層２５・・・ｎ−エピタキシャル層
２６・・・ｎ ソース領域
２７．２９・・・ｐゲート領域
２８・・・ｎ ドレイン領域 ８０・・・絶縁層８１・
・・ソース電極 ８２・・・ドレイン電極８Ｂ・・
・ゲート電極 ８４・・・表面絶縁膜８６−・・ｐ
分離ゲート領域８７・・・分離ゲート電極４０−１．４
０−２・・・固体撮像装置４１・・・リセット線 ４
２−１．４２−２・・・行ライン４８・・・垂直選択シ
フトレジスタ
４４−１．４４−２・・・列ライン
４５・・・水平選択シフトレジスタ
４６−１．４６−２・・・水平選択トランジスタ４７・
・・ビデオライン ４８・・・負荷抵抗４９・・・出
力端子。
特許出願人 オリンパス光学工業株式会社同 出願人
西 澤 潤 −
第１図
第２図
ψＤｆ−ローー→→几−ヨ。
第５図
手続補正書
昭和５９年 ３ 月８ 日
、事件の表示
昭和５７年 特 許 願第２１７７５３号：０発明の名
称
固体撮像装置
、補正をする者
事件との関係 特許出願人
（０３７） オリンパス光学工業株式会社西 澤
潤 −
補正の対象 明細書の「発明の詳細な説明」の欄補正の
内容（別紙の通り）
１明細書第１２頁第１３行の「素子Ｊ？ｉ：ｒ感光用５
ＩＴＪに訂正し、
向頁第１５〜１６行°の「ソース−ドレイン」を１ゲー
ト−ソース」に訂正する。
（２）
３１３−1A and B are a sectional view and a plan view showing the structure of the SIT; FIGS. 2A and B are a circuit diagram and a signal waveform diagram for explaining the structure and operation of a solid-state image device using the SIT; 8A and 8B are a sectional view and a plan view showing the configuration of an example of a solid-state imaging device used in the solid-state imaging device of the present invention, and FIG. 4A and B are a cross-sectional view showing the configuration of another example. Figures and Plan Views FIG. 6 is a circuit diagram showing an example of the configuration of a main part of the solid-state imaging device of the present invention. 21... SIT for photosensitive 22... SI for reading
'l'2B...p-type substrate 24...n buried layer 25...n-epitaxial layer 26...n source region 27.29...p gate region 28...n drain region 80 ...Insulating layer 81.
...Source electrode 82...Drain electrode 8B...
・Gate electrode 84...Surface insulating film 86-...p
Separation gate region 87... Separation gate electrode 40-1.4
0-2...Solid-state imaging device 41...Reset line 4
2-1.42-2...Row line 48...Vertical selection shift register 44-1.44-2...Column line 45...Horizontal selection shift register 46-1.46-2... Horizontal selection transistor 47
...Video line 48...Load resistor 49...Output terminal. Patent Applicant: Olympus Optical Industry Co., Ltd. Applicant: Jun Nishizawa - Figure 1 Figure 2 ψDf-Ro-→→R-Yo. Figure 5 Procedural Amendment Document March 8, 1980, Display of Case 1982 Patent Application No. 217753: 0 Name of Invention Solid-state Imaging Device, Person Making Amendment Relationship to Case Patent Applicant (037) Olympus Optical Industry Co., Ltd. Nishizawa
Jun - Target of amendment Contents of amendment in the "Detailed Description of the Invention" column of the specification (as attached) 1 "Element J?i:r photosensitive 5
ITJ, and on the 15th and 16th lines of the opposite page, ``source-drain'' is corrected to ``1 gate-source''. (2) 313-
Claims (1)
用トランジスタの光重変換出力を選択的に読出す読出し
用トランジスタとを有し、それらの主電流通路を直列に
接続して成る固体撮像素子を、複数の行線および列線で
構成されるマトリックスの各交点にそれぞれ設け、これ
ら行線および列線に前記固体撮像素子の１”続出し用ト
ランジスタを接続し、その感光用トランジスタをリセッ
ト線に接続したことを特徴とする固体撮像装置。1. A solid-state image sensor comprising a photosensitive transistor that receives incident light and a readout transistor that selectively reads out the light weight conversion output of this photosensitive transistor, and whose main current paths are connected in series. , are provided at each intersection of a matrix consisting of a plurality of row lines and column lines, and the 1" continuous output transistor of the solid-state image sensor is connected to these row lines and column lines, and the photosensitive transistor is connected to the reset line. A solid-state imaging device characterized in that:
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57217753A JPS59108460A (en) | 1982-12-14 | 1982-12-14 | Solid-state image pickup device |
| DE3345147A DE3345147C2 (en) | 1982-12-14 | 1983-12-14 | Solid-state image pickup converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57217753A JPS59108460A (en) | 1982-12-14 | 1982-12-14 | Solid-state image pickup device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59108460A true JPS59108460A (en) | 1984-06-22 |
Family
ID=16709203
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57217753A Pending JPS59108460A (en) | 1982-12-14 | 1982-12-14 | Solid-state image pickup device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPS59108460A (en) |
| DE (1) | DE3345147C2 (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6058781A (en) * | 1983-09-09 | 1985-04-04 | Olympus Optical Co Ltd | Solid-state image pickup device |
| US4746984A (en) * | 1985-04-24 | 1988-05-24 | Olympus Optical Co., Ltd. | Solid state image sensor with lateral-type stactic induction transistors |
| JPH0714042B2 (en) * | 1986-02-26 | 1995-02-15 | 三菱電機株式会社 | Solid-state image sensor |
| JPH06334920A (en) * | 1993-03-23 | 1994-12-02 | Nippon Hoso Kyokai <Nhk> | Solid state image pickup element and driving method thereof |
| DE19740612B4 (en) * | 1997-08-30 | 2005-10-13 | Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. | Arrangement of image sensor elements |
| EP1013076B1 (en) | 1997-09-12 | 2001-02-28 | Fraunhofer-Gesellschaft Zur Förderung Der Angewandten Forschung E.V. | Image detection members |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5515229A (en) | 1978-07-18 | 1980-02-02 | Semiconductor Res Found | Semiconductor photograph device |
| JPS58105672A (en) * | 1981-12-17 | 1983-06-23 | Fuji Photo Film Co Ltd | Semiconductor image pickup device |
| JPS5930376A (en) * | 1982-08-13 | 1984-02-17 | Olympus Optical Co Ltd | Solid-state image pickup device |
| DE3236073A1 (en) * | 1982-09-29 | 1984-03-29 | Siemens AG, 1000 Berlin und 8000 München | TWO-DIMENSIONAL SEMICONDUCTOR IMAGE SENSOR WITH AN ARRANGEMENT FOR REDUCING OVER-RADIATION |
-
1982
- 1982-12-14 JP JP57217753A patent/JPS59108460A/en active Pending
-
1983
- 1983-12-14 DE DE3345147A patent/DE3345147C2/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE3345147A1 (en) | 1984-06-14 |
| DE3345147C2 (en) | 1986-10-02 |
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