JPS6085800U - Semiconductor read-only memory - Google Patents
Semiconductor read-only memoryInfo
- Publication number
- JPS6085800U JPS6085800U JP17821583U JP17821583U JPS6085800U JP S6085800 U JPS6085800 U JP S6085800U JP 17821583 U JP17821583 U JP 17821583U JP 17821583 U JP17821583 U JP 17821583U JP S6085800 U JPS6085800 U JP S6085800U
- Authority
- JP
- Japan
- Prior art keywords
- input
- circuit
- terminal
- decoder
- memory cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来の縦積み方式のROMの一例の要部のブロ
ック図、第2図は第1図に示す縦積み方式のROMの詳
細回路図、第3図は本考案の一実施例の回路図である。
1・・・メモリセル・トランジスタ、2・・・メモリセ
ル列、3,3′・・・Xデコーダ、4,4′・・・Yデ
コーダ、5・・・センスアンプ、6・・・入力端子、7
・・・チップイネーブル信号入力端子、8・・・出力端
子、9・・・ti端子、10・・・プリチャージ用トラ
ンジスタ、11・・・セル列切換用トランジスタ、12
.13・・・インバータ、14・・・m入力NOR回路
、15・・・n入力NAND回路、16・・・テスト端
子、17・・・インバータ、1B・・(n+1)入力N
AND回路、19・・・インバータ、20・・・(m+
1)入力NOR回路、21・・・2人力NOR回路。
カl圀
6
1 μ4 CYJ4
− 〜乃2g」Figure 1 is a block diagram of the main parts of an example of a conventional vertically stacked ROM, Figure 2 is a detailed circuit diagram of the vertically stacked ROM shown in Figure 1, and Figure 3 is an example of an embodiment of the present invention. It is a circuit diagram. DESCRIPTION OF SYMBOLS 1...Memory cell transistor, 2...Memory cell column, 3, 3'...X decoder, 4,4'...Y decoder, 5...Sense amplifier, 6...Input terminal ,7
... Chip enable signal input terminal, 8 ... Output terminal, 9 ... ti terminal, 10 ... Precharge transistor, 11 ... Cell row switching transistor, 12
.. 13... Inverter, 14... m input NOR circuit, 15... n input NAND circuit, 16... test terminal, 17... inverter, 1B... (n+1) input N
AND circuit, 19...inverter, 20...(m+
1) Input NOR circuit, 21...2 manual NOR circuit. Kakuni 6 1 μ4 CYJ4 - ~no 2g"
Claims (1)
るメモリセル列を複数列配置して構成されるメモリセル
アレイと、該メモリセルアレイの各行のトランジスタの
ゲートに共通に出力端が接続するn入力NAND回路の
列を含んで構成されるXデコーダと、入力端子の一つに
チップイネーブル信号を入力し他の端子にYデコーダ信
号を入力するNOR回路の列と該NOR回路の各々の出
力端にそれぞれゲートが接続するトランジスタの列から
成るメモリセル列切換えデコーダと、チップイネーブル
信号をゲートに入力するプリチャージ用トランジスタと
を含んで構成されるYデコーダとを有する半導体読出し
専用メモリにおいて、前記XデコーダのNAND回路を
(n+1)入力NAND回路とし、前記YデコーダのN
OR回路を(m 十1)入力NOR回路とし、前記新し
く追加されたNAND回路の入力端子をすべて接続し、
インバータを介して新しく設けたテスト端子に接続し、
前記YデコーダのNOR回路の新しく追加された入、力
端子をすべて共通接続しかつインバータを介して接続し
、前記チップイネーブル信号入力端子に入力端子の一つ
が接続し他の入力端子が前記(m+1)入力NOR回路
の新しく追加された入力端子に接続し出力端子が前記プ
リチャージ用トランジスタのゲートに接続する2人力N
OR回路を設けたことを特徴とする半導体読出し専用メ
モ1几A memory cell array configured by arranging a plurality of memory cell columns each having a plurality of memory cells/transistors connected in series, and an n-input NAND whose output end is commonly connected to the gates of transistors in each row of the memory cell array. An X decoder including a row of circuits, a row of NOR circuits that input a chip enable signal to one of the input terminals and a Y decoder signal to the other terminal, and an output terminal of each of the NOR circuits. In a semiconductor read-only memory having a memory cell column switching decoder consisting of a column of transistors whose gates are connected, and a Y decoder including a precharging transistor inputting a chip enable signal to the gate, the The NAND circuit is an (n+1) input NAND circuit, and the NAND circuit of the Y decoder is
The OR circuit is made into a (m 11) input NOR circuit, and all the input terminals of the newly added NAND circuit are connected,
Connect to the newly installed test terminal via the inverter,
The newly added input and output terminals of the NOR circuit of the Y decoder are all commonly connected and connected via an inverter, one of the input terminals is connected to the chip enable signal input terminal, and the other input terminal is connected to the (m+1) input terminal. ) A two-power NOR circuit whose output terminal is connected to the newly added input terminal of the input NOR circuit and whose output terminal is connected to the gate of the precharge transistor.
1 liter of semiconductor read-only memo featuring an OR circuit
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17821583U JPS6085800U (en) | 1983-11-18 | 1983-11-18 | Semiconductor read-only memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17821583U JPS6085800U (en) | 1983-11-18 | 1983-11-18 | Semiconductor read-only memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6085800U true JPS6085800U (en) | 1985-06-13 |
JPS6338480Y2 JPS6338480Y2 (en) | 1988-10-11 |
Family
ID=30386983
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17821583U Granted JPS6085800U (en) | 1983-11-18 | 1983-11-18 | Semiconductor read-only memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6085800U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61289600A (en) * | 1985-06-17 | 1986-12-19 | Fujitsu Ltd | Semiconductor memory device |
-
1983
- 1983-11-18 JP JP17821583U patent/JPS6085800U/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61289600A (en) * | 1985-06-17 | 1986-12-19 | Fujitsu Ltd | Semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
JPS6338480Y2 (en) | 1988-10-11 |
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