JPS6083382A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

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Publication number
JPS6083382A
JPS6083382A JP58190745A JP19074583A JPS6083382A JP S6083382 A JPS6083382 A JP S6083382A JP 58190745 A JP58190745 A JP 58190745A JP 19074583 A JP19074583 A JP 19074583A JP S6083382 A JPS6083382 A JP S6083382A
Authority
JP
Japan
Prior art keywords
layer
film
amorphous silicon
semiconductor device
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58190745A
Other languages
Japanese (ja)
Inventor
Koichi Seki
浩一 関
Hideaki Yamamoto
英明 山本
Toshio Nakano
中野　寿夫
Akira Sasano
笹野　晃
Toshihisa Tsukada
俊久 塚田
Juichi Shimada
嶋田　寿一
Ken Tsutsui
謙 筒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP58190745A priority Critical patent/JPS6083382A/en
Publication of JPS6083382A publication Critical patent/JPS6083382A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/075—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PIN type, e.g. amorphous silicon PIN solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/548—Amorphous silicon PV cells

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Sustainable Development (AREA)
  • Sustainable Energy (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To upgrade the photoelectric conversion efficiency of a semiconductor device by a method wherein a transparent conductive layer, which is formed by an interfacial reaction of an amorphous silicon with a metal, is used as a transparent electrode. CONSTITUTION:A Cr electrode 42 is formed on a glass substrate 41. A P-containing amorphous silicon hydride (n layer) 431, an amorphous silicon hydride (i layer) 432 and a B-containing amorphous silicon hydride (p layer) 433 are successively formed thereon. Cr (Pt) is formed on the whole surface thereof in a thickness of 0.1mum by evaporation and Al(Au) is formed thereon in a thickness of 1mum by evaporation. Lastly, CrAl(Pt-Au) only at parts, which respectively function as an interdigital electrode 45, is left, CrAl(Pt-Au) at other parts is removed, and a transparent electrode 44 and the interdigital electrodes 45 are formed. According to this method, a high sensitive amorphous silicon light-receiving element can be obtained by a simple manufacturing process.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は透明゛成極を有する半導体装置及び、その製造
方法に係るものである。例えば太陽電池、ホトダイオー
ド、或いは撮像装置等に通用されるものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device having transparent polarization and a method for manufacturing the same. For example, it is commonly used in solar cells, photodiodes, imaging devices, and the like.

〔発明の背景〕[Background of the invention]

従来、例えば太陽電池においては周知のように第１図に
示すような構造が採用されている。第１図において、１
ｆ′ｉ基板、２は下部電極、３は半導体、４は透明電極
、５は金属ヲくシ形に形成した上部電極である。透明電
極４に光を照射することで半導体３中に発生する正孔及
び電子を下Ｓ電極２と上部１極５とを通して外部に取出
すものである。また、例えばホトダイオードは、従来、
第２図に示す断面構造で実現されている。縞２図にお込
て、２１は基板、２２は下部電極、２３ｉｌｔ＃−尋坏
、２４は透明電極、２５！電流取出し用の上部電極で一
般に金属が用いられる。透明電極２４に光を入射するこ
とによム下部′に極２２と上部電極２５との間に入射光
に応じた電流が流れる。Conventionally, for example, a solar cell has adopted a structure as shown in FIG. 1, as is well known. In Figure 1, 1
In the f'i substrate, 2 is a lower electrode, 3 is a semiconductor, 4 is a transparent electrode, and 5 is an upper electrode formed in the shape of a metal wedge. Holes and electrons generated in the semiconductor 3 by irradiating the transparent electrode 4 with light are extracted to the outside through the lower S electrode 2 and the upper one pole 5. Furthermore, for example, photodiodes are conventionally
This is realized with the cross-sectional structure shown in FIG. In the stripe diagram 2, 21 is the substrate, 22 is the lower electrode, 23 is the base electrode, 24 is the transparent electrode, and 25! Metal is generally used for the upper electrode for current extraction. When light is incident on the transparent electrode 24, a current corresponding to the incident light flows between the pole 22 and the upper electrode 25 in the lower part' of the membrane.

このように従来の透明電極を備えた光電変換素子は、透
明電極の上に金層よりなる上部１！僕を形成する２重ｆ
ＩＬ極構造であり、従ってその製造工程としても、透明
電極の形成とその加工％蛍属より夏る上部電極の形成と
その加工という工程が必要で、あった。さらに、透明！
極としてはＩＴＯ（Ｉｎｄｉｕｍ　’ｌ’ｉｎ　Ｑｘｉ
ｄｅ）が用いられるが、この材料は通常、スパッタ蒸着
によりフレ成され、従って、ＩＴＯ形成形成生導体表面
に欠陥を生せしめたり・また、良質のＩＴＯＭｔ−得る
のが殖しいなどの問題点ｔもってしる。In this way, the conventional photoelectric conversion element equipped with a transparent electrode has an upper part 1 consisting of a gold layer on the transparent electrode. The double f that forms me
It has an IL polar structure, and therefore, its manufacturing process requires the formation of a transparent electrode and its processing, forming an upper electrode that is higher than the fluorophore. Plus, it's transparent!
As a pole, ITO (Indium 'l'in Qxi
de) is used, but this material is usually formed by sputter deposition and therefore has problems such as defects on the ITO formed raw conductor surface and difficulty in obtaining good quality ITOMt. I have it.

さらに、ＩＴＯ換上に下部電極となる金属をホトエツチ
ングで加工するときに、ＩＴＯは憾めて耐薬品性が弱い
材料であることから、ＩＴＯも溶解してしまうというこ
ともあシ、透明電極にＩＴＯを・匣用するには多くの問
題点があった。Furthermore, when processing the metal that will become the lower electrode on top of the ITO by photoetching, since ITO is a material with poor chemical resistance, there is a risk that the ITO will also dissolve. There were many problems in using ITO.

〔光明の目的〕[Purpose of illumination]

本発明の目的は透明を惚として金層と水素化非晶質シリ
コｙ（ａ−８ｉ二Ｈ）層との加熱反応によって形成され
る導電体層を使用した半導体装置の光電変換効率を高め
る事にある。The purpose of the present invention is to improve the photoelectric conversion efficiency of a semiconductor device using a conductor layer formed by a heating reaction between a gold layer and a hydrogenated amorphous silicon y (a-8i diH) layer while maintaining transparency. It is in.

〔発明の４ｇ要〕 本発明の骨子は次の通シである。水素化非晶質シリコン
層（ａ−７９ｉ：Ｈ）を有する半導体を用い、この水素
化非晶質シリコン層とＣｒｅＭｏ、ＷｔＴｉ、Ｖ＠Ｚｒ
＊　Ｎｂ＊　Ｔａｇ　Ｈｆ、Ｎｉ、Ｐｔ。[4g essential points of the invention] The gist of the present invention is as follows. Using a semiconductor having a hydrogenated amorphous silicon layer (a-79i:H), this hydrogenated amorphous silicon layer and CreMo, WtTi, V@Zr
*Nb* Tag Hf, Ni, Pt.

Ｐｄ、　ｋＬｈおよびＣｏの群から選ばれた少なくとも
一考を含有する金１４膜との界面反応によって両者の界
面に形成される透光性の導電体層を透明電極として用い
さらに、前記透明電極上に、干渉膜を設け、半導体素子
の高感度化ｔ−４成するものでｌある。A transparent conductive layer formed at the interface between the gold-14 film and the gold-14 film containing at least one material selected from the group of Pd, kLh and Co is used as a transparent electrode, and further, a transparent conductive layer is formed on the transparent electrode. In addition, an interference film is provided to increase the sensitivity of the semiconductor element.

従って、七の製造法の骨子は久の通フである。Therefore, the gist of the manufacturing method for No. 7 is Hisanotsufu.

所定基板上に水素化非晶質シリコン層を形成し、吏ｖｃ
こｔｖ上ｍに前述のＣｒ＊ｍｏ＊ＶＶ＊Ｐｔ＊Ｐｄ、些
り等を含有する所定の金ＳＳを形成し、その両−を界面
反応を生せしめその界面に透光性の導電体層を形成させ
る。そしてこの導電体層を形成するに当って用いた金属
膜を除去する。さらに、前記透光性の導電層上に、干＃
１換を形成する工程を含むことｔ％徴とするものである
。forming a hydrogenated amorphous silicon layer on a predetermined substrate;
A predetermined gold SS containing the aforementioned Cr*mo*VV*Pt*Pd, etc. is formed on this TV, and an interfacial reaction is caused between the two to form a transparent conductive layer at the interface. to form. Then, the metal film used to form this conductor layer is removed. Further, on the transparent conductive layer, a dry #
The inclusion of a step of forming a monomer is considered to be a t% characteristic.

なお、前記干渉膜は、素子への入射率を高めるものであ
るから、一様な膜が形成されれば良いので膜厚に関して
それ程選択性はない。例えば、素子の断面の凸凹を埋め
、表面が平面になるように形成してもよいものである。Note that since the interference film is intended to increase the incidence rate to the element, it is sufficient to form a uniform film, so there is not much selectivity regarding the film thickness. For example, the unevenness of the cross section of the element may be filled so that the surface becomes flat.

また、前記の金属膜としては１４１１記した金属の単体
のみでなく、その相互の九合物、合金、或いはＰ　ｔ−
Ａｕ、　Ｃｒ　−ＡＬ、　Ｃｒ−Ｎ　ｉ、　Ｃｒ　−Ｎ
　１−Ａｔ等前述した金層を含Ｍする金属膜を用ｉるこ
也が出来るこの金属膜の厚さは、この金属層を透明導電
体）−を形成後へしてしまうのでそれ程選択性！−ｔな
いが、通常、３００人〜２０００人　よシ好ましくは５
００Ａ〜２０００Ａ　程ＦＩＬを用いるａｍり膜がうず
いと膜の均一性に劣る。一方、余〕厚い膜を用いても特
に利点はなく、かえって金属膜の応力によって半導体層
に悪影響をおよぼす可能性が増大する。In addition, the above-mentioned metal film may be made of not only the single metals listed in 1411, but also their mutual combinations, alloys, or Pt-
Au, Cr-AL, Cr-Ni, Cr-N
It is possible to use a metal film containing M, such as the gold layer described above, such as 1-At. ! -No, but usually 300 to 2000 people, preferably 5
From 00A to 2000A, the film using FIL is dull and the film is poor in uniformity. On the other hand, there is no particular advantage in using an extra thick film, and on the contrary, the possibility that stress in the metal film will adversely affect the semiconductor layer increases.

反応温度は１ｏｏｃ〜２５０Ｃの範囲を用いる。時に２
５０Ｃ以上になると水素化非晶ｊｔ７リコ／の変質がは
じまるので好ましくない。反応時間は反応温度にもよる
が２０分〜１時間程度である。余シ長時間加熱しても特
に利点はない。The reaction temperature ranges from 100C to 250C. sometimes 2
If the temperature exceeds 50C, deterioration of the hydrogenated amorphous jt7 lico/ starts, which is not preferable. The reaction time is about 20 minutes to 1 hour, depending on the reaction temperature. There is no particular advantage to heating the remaining material for a long time.

又、金属膜形成時に加熱しても（加熱蒸着）良く、更に
勿論金属膜形成後加熱処理しても艮い。Further, heating may be performed during the formation of the metal film (heated evaporation), and of course, heat treatment may also be performed after the formation of the metal film.

更に、水素化非晶質シリコン層上への金属膜の形成の直
前に同シリコン層の表面を除去し、いわゆる表面酸化層
と思われる層を除去した場合、特に加熱処理を施こさな
くとも透明導電体層の形成が可能となる。金属蒸着源よ
多の加熱によって、　６０Ｃ〜７０Ｃの加熱が試料にな
され透明導電体層が形成される。Furthermore, if the surface of the hydrogenated amorphous silicon layer is removed immediately before forming a metal film on the silicon layer, and what is considered to be a surface oxidation layer is removed, the layer becomes transparent without any special heat treatment. It becomes possible to form a conductor layer. By heating the metal vapor deposition source, the sample is heated to 60 to 70 C to form a transparent conductor layer.

水素化非晶質シリコン層としてはその伝導型がｐ型、ｉ
［、ｎ型のいずれの場合も同様に透明導電膜が形成され
る。勿論、Ｐ、Ｈ，Ｎ、Ｃ，０、或いｆｉ、Ｇｅ等の不
純物を含有していても同様である。The conductivity type of the hydrogenated amorphous silicon layer is p type, i
A transparent conductive film is formed in the same way in both [ and n-type cases. Of course, the same applies even if impurities such as P, H, N, C, 0, fi, Ge, etc. are contained.

又非晶質シリコンのダングリングボンド（ｄａｎｇｌｉ
ｎｇ　ｔ）ｏｎｄ）のターミネートするため導入されて
いるＨの代シにＦ’（ｒ用いてターミネートした非晶質
シリコンの場合も同様の透光性導電膜が形成される。さ
らに、非晶質ｓｉＣや非晶質５ｉＱｅも同様の透光性導
電膜が形成されることはもちろんである。Also, dangling bonds of amorphous silicon
A similar transparent conductive film is formed in the case of amorphous silicon that is terminated with F' (r) instead of H introduced to terminate the amorphous silicon. Of course, a similar light-transmitting conductive film can be formed using siC or amorphous 5iQe.

こうして形成された透光性導電体層は光透過性も十分実
用的であり、一方抵抗値も約１０に９７口以下でこれも
実用上問題ない範四にめる。The light-transmitting conductive layer thus formed has sufficient light transmittance for practical use, and the resistance value is also about 10 to 97 or less, which is also in the fourth range, which poses no problem for practical use.

本発明は、上記発見による非晶質シリコンと金属との界
面反応で形成される透明導電体層を透明電極とするもの
である。本発明によれば、例えば第１図の太陽電池を作
る場合、半導体３の上に水素化非晶質シリコン層を形成
し、その上に例えばＣｒを加熱蒸着し、仄に必要なＣｒ
部分だけを残しあとのＣｒｆ除去してやるだけで太陽電
池が児成してしまう。製造工程が従来法に比べて半減し
、ＩＴＯの場合のような問題点もない。この場合、Ｃｒ
膜のＩＡ着としては、抵抗加熱蒸着、電子ビーム蒸着、
スパッタ蒸着のいずれの方法でも全く同様の透明電極が
自然に形成されることを確認した。The present invention uses a transparent conductor layer formed by an interfacial reaction between amorphous silicon and a metal as a transparent electrode based on the above discovery. According to the present invention, for example, when manufacturing the solar cell shown in FIG.
A solar cell can be produced by simply leaving only that part and removing the rest of the Crf. The manufacturing process is halved compared to the conventional method, and there are no problems like ITO. In this case, Cr
Film IA deposition methods include resistance heating evaporation, electron beam evaporation,
It was confirmed that completely similar transparent electrodes were naturally formed using either sputter deposition method.

水素化非晶質シリコンあるいはＰ（リン）をドープした
ｎ型の非晶質シリコンは光分利用できるものである。た
だし、こ几らの非晶質シリコンは自然酸化されやすく、
１ケ月程度空気中に放置すると厚みが数ｌＯ人程度の酸
化膜が形成さ几、この酸化膜がある場合、その上にＣｒ
ｆ形成しても、酸化膜か反応防止の役割を果たし、透光
性の導電体層が形成されなくなる。従ってこの酸化膜は
除去してから本発明を適用する心安がある。一方、Ｂを
ドープした水素化非晶質シリコンは上記のものよシ化学
的に安定であシ、１０ケ月程度放置しても酸化ｍはでき
ず、常に導電体層を得ることができた。Hydrogenated amorphous silicon or n-type amorphous silicon doped with P (phosphorous) can be used for optical purposes. However, Koori et al.'s amorphous silicon is easily oxidized naturally.
If left in the air for about a month, an oxide film with a thickness of several liters will form.If this oxide film exists, Cr
Even if f is formed, the oxide film plays the role of preventing reaction, and a light-transmitting conductive layer is not formed. Therefore, it is safe to apply the present invention after removing this oxide film. On the other hand, hydrogenated amorphous silicon doped with B was chemically more stable than the above-mentioned silicon, and no oxidation occurred even after being left for about 10 months, and a conductive layer could always be obtained.

更に本発明では、前記透光性の導電体層の有する特徴を
改善したものである。すなわち、以下に述べるような干
渉膜を設けない半導体装置では照射光の一部が表面での
反射によって装置内部にとシこまれない。すなわちＩ　
ＴＯ（Ｉｎｄｉｕｍ　ＴｉｎＱｘｉｄｅ　）を透明電極
とする装置と比較すると単に透光性の導電体層のみを有
する半導体装置の光電変換効率は低いのである。しかも
ＩＴＯを使用する場合であれば、その膜厚を制御する墨
によって所望の波長の光に対してほぼ無反射とする事が
できるが、金属と非晶質シリコン層の加熱反応によって
形成される層は薄く、シかもその膜厚の制御は困難であ
る。よって光電変換動　率を膜厚の制御で高めるのは難
しいのである。Furthermore, the present invention improves the characteristics of the light-transmitting conductive layer. That is, in a semiconductor device not provided with an interference film as described below, a portion of the irradiated light is reflected from the surface and is not absorbed into the device. That is, I
Compared to a device using TO (Indium Tin Qxide) as a transparent electrode, a semiconductor device having only a transparent conductive layer has a low photoelectric conversion efficiency. Moreover, when using ITO, it is possible to make it almost non-reflective to light of the desired wavelength by controlling the film thickness, but ITO is formed by a heating reaction between the metal and the amorphous silicon layer. The layer is thin and its thickness is difficult to control. Therefore, it is difficult to increase the photoelectric conversion rate by controlling the film thickness.

ここで、屈折率と膜厚及び反射率の関係番明らかにする
。Here, the relationship between refractive index, film thickness, and reflectance will be clarified.

第３図のような屈折率ｎ２の物質Ａの上−ノ函折率ｎ１
−さｄの薄膜Ｂを形成した場合の反射率Ｒは次式モ表わ
される。図中、Ｃは光の反射を示している。簡単のため
垂直入射を仮定する。□λ：光の波長 この式から無反射となる条件は ｎｌ”＝ｎｌ ｄ−λ／４ｎｔ　ｘ　（２ｒｎ＋１　）　（ｍ＝（Ｌ±
１．±２・・・・・・・・・）で与えられる。即ち、屈
折率がｆｉｔ　ｂ厚さが（２ｍ＋１　）λ／４ｎ１であ
る薄膜を堆積する事により無反射とする事ができる。The upper-fold refractive index n1 of a substance A with a refractive index n2 as shown in FIG.
The reflectance R when the thin film B of −sd is formed is expressed by the following formula. In the figure, C indicates light reflection. For simplicity, we assume normal incidence. □λ: Wavelength of light From this formula, the condition for no reflection is nl"=nl d-λ/4nt x (2rn+1) (m=(L±
1. It is given by ±2・・・・・・・・・）. That is, by depositing a thin film having a refractive index of fit b and a thickness of (2m+1)λ/4n1, it is possible to make it non-reflective.

実際には過当な材料が存在しない、所望の波長域が広い
などの理由で無反射とする！ｔｒｔｍ＆しい。In reality, it is made non-reflective because there are no inappropriate materials, the desired wavelength range is wide, etc. trtm&shii.

そのような場合にはｎｌをｎ２よシ小さくする事によっ
て素子内部に取シとまれる光電を上げる事ができる。In such a case, by making nl smaller than n2, it is possible to increase the amount of photoelectricity captured inside the element.

以上は単層の場合であるが、多層とし、保々に屈折率が
小さくなるように積層しても良い。Although the above is a case of a single layer, it is also possible to have multiple layers and laminate them so that the refractive index keeps decreasing.

また、この膜に適轟な材料を選ぶことによって透光性導
を腺の保賎膜として請かす事ができる。In addition, by selecting a suitable material for this membrane, it can be used as a protective membrane for the glands to transmit light.

通常、この膜の厚みは先の式に従い、与えられた屈折ｇ
ｎｌ、ｎ２に対して反射率が最小となるように選ぶ事が
厳も望ましいが、どのような膜厚であっても反射率は小
さくなる。保譲膜として働かせるためにはある程度厚く
堆積する事が必要となる。Usually, the thickness of this film is determined according to the above formula, given the refraction g
Although it is strictly desirable to select nl and n2 so that the reflectance is minimized, the reflectance will be small no matter what the film thickness is. In order to function as a preservation film, it is necessary to deposit it to a certain degree of thickness.

なお、前記干渉層の材料としては無機、有機を問わず、
榎々のものが９罷であるが、非晶質水素化シリコンの耐
熱性かたかだが３００ｃであるため、できるだけ低温で
堆積できる事が条件となる。Note that the material for the interference layer may be inorganic or organic;
Enoki's method has 9 cracks, but since the heat resistance of amorphous hydrogenated silicon is 300c, the condition is that it can be deposited at as low a temperature as possible.

このような条件を満たすものとしてはＳ；３Ｎ４゜５ｊ
Ｏｚ・Ｓ　ｉＯＮ、　Ｓ　ｉｏ、　５ＯＧ（スピン　オ
ン　グラス）ｆｔどｏガラス系の材料がまずあげられる
。S;3N4゜5j satisfies these conditions.
The first examples are glass-based materials such as Oz・SiON, Sio, and 5OG (spin-on glass).

Ｓ　’　ｓ　Ｎ４　ｓ　Ｓ　ｉＯＮはグラ、１．−ｒ　
ＣＶ　Ｄ法によ、ｔ１２００〜３００Ｃの低温で堆積で
きる。８ｉＣｈＵスパッタリング−８ｉＯは蒸着、ＳＯ
Ｇはスピンコードで形成できる。これらの材料はＳｉＯ
＊除けば可視領域では透明とみなす事ができる。所望の
波長にあった材料を使９必妥がある。S' s N4 s S iON is graphic, 1. -r
By CVD method, it can be deposited at a low temperature of t1200 to 300C. 8iChU sputtering - 8iO evaporation, SO
G can be formed by spin cord. These materials are SiO
*It can be considered transparent in the visible region except for *. It is necessary to use a material that matches the desired wavelength.

また透光性の有機樹脂も勿論使用することができる。ホ
トダイ穿−ドの感光波長が限足されているあるいは感光
波長が狭くてよい場合には感光波長に合せて有色性の刹
機樹脂も勿論利用できる。　、使用できる有機樹脂の代
表例としてはエポキシ樹脂、アクリル樹脂、ポリスチレ
ン樹脂、フェノール樹脂、ポリイミド樹脂等があり、極
めて多くの透明樹脂全埜げることができる。Of course, a translucent organic resin can also be used. If the photosensitive wavelength of photo-die drilling is limited or only needs to be narrow, colored resins can of course be used depending on the photosensitive wavelength. Typical examples of organic resins that can be used include epoxy resins, acrylic resins, polystyrene resins, phenolic resins, and polyimide resins, and a wide variety of transparent resins can be used.

これらの有機樹脂は一般にスピンコードなどの方法で被
膜とすることができ、４ＥＬ膜の強化のためにあらかじ
め架橋剤を添加し樹脂液をコートして被膜とした仮適当
に加熱架橋することもできる。These organic resins can generally be made into a film by a method such as spin cording, and in order to strengthen the 4EL film, a crosslinking agent can be added in advance and a resin liquid coated to form a film, which can then be temporarily crosslinked by heating. .

例えばエポキシ樹脂ではアミン系や有機酸無水物やヒド
ロキシベンゾフエ７ノ系めるいは低分子量のフェノール
樹脂崎が架橋剤として有効である。For example, in the case of epoxy resins, amines, organic acid anhydrides, hydroxybenzophenols, and low molecular weight phenolic resins are effective as crosslinking agents.

これらの有機樹脂はホトレジストのような感光性樹脂で
あることがおおむね望ましい。利用できるホトレジスト
としては、遠紫外光よりエネルギーの大きい放射線感応
性のものにはポリグリシジルメタクリレート、ポリメタ
クリンート、ポリビニルフェノールあるいはフェノール
ノボラック樹脂にジアジド化合物例えば３３′ジアジド
ジフエ二ル、２．ルホ／を加えた樹脂、あるいは環化ゴ
ム系レジンに前記のようなジアジド化合物を〃口えた樹
脂等があシ、これらは無色透明膜を与え、３６５〜４５
０Ｈｍ光に対して感光性のホトレジストには一般市販の
ホトレジスト例えば東京応化製ＯＭＩＬ８３又は、０Ａ
４Ｒ−８５等あるいはコダック製ＫＴＦ’Ｒ等があシ、
これらは淡く黄色を呈する。またこれらルシストハ加熱
すると着色が淡くなるものが多い。It is generally desirable that these organic resins be photosensitive resins such as photoresists. Usable photoresists include polyglycidyl methacrylate, polymethacrylate, polyvinylphenol, or phenol novolak resin, diazide compounds such as 33' diazidiphenyl, 2. There are resins containing fluorocarbons, or cyclized rubber resins mixed with diazide compounds such as those mentioned above, which give a colorless transparent film.
As a photoresist sensitive to 0Hm light, commercially available photoresists such as OMIL83 manufactured by Tokyo Ohka Co., Ltd. or 0A
4R-85 etc. or Kodak KTF'R etc.
These are pale yellow in color. In addition, many of these lucistophores become lighter in color when heated.

またこれらの樹脂に染料などを浸透させることで色フイ
、ルタのような役割を持たせることもＯｆ能であり１．
更に樹脂をパターン化することで多色のカラーセンサと
することも可能、である。これら染料を浸透させる樹脂
としてはゼラチンのようなものがオリ用できる。It is also possible to make these resins function as color fillers and ruta by impregnating them with dyes, etc. 1.
Furthermore, by patterning the resin, it is possible to create a multicolor sensor. A resin such as gelatin can be used as a resin for penetrating these dyes.

このほか、絶縁性を必要としない場合や、そのようにパ
タニン化する事を前提とすればＩＴＯ。In addition, ITO can be used if insulation is not required or if it is intended to be patterned.

５ｉＯ２等、の従来からの透光性傘栖化合物も用いる事
ができる。。特に太陽電池等亨偽抵抗が低い事が望まれ
る場合には非晶質水素化どリコンと金属の反応物の上に
Ｉｎ０ａあるいは５ｎＯｚあるいは５ｎＱ２ドープＩｎ
Ｏ３を積層する事により凌れた特性の素招を得る事がで
きる。こうすれば非晶質水素化シリコンとＩＴＯ等の従
来の透明電極の間のような界面の問題はなくなる。Conventional light-transmitting umbrella compounds such as 5iO2 can also be used. . In particular, when low false resistance is desired, such as in solar cells, In0a, 5nOz, or 5nQ2 doped In0a, 5nOz, or 5nQ2 doped In
By stacking O3, superior characteristics can be obtained. This eliminates the interface problem between amorphous hydrogenated silicon and conventional transparent electrodes such as ITO.

もちろん、上記の異なる種類の°膜を積層してもよい。Of course, the above-mentioned different types of films may be laminated.

また、非晶質半導体としては水素化あるいは弗素化非晶
質シリコンはもちろんの事、Ｓ；のほかＫＧｅ、Ｃ＝ａ
−含む非晶質半導体にも適用可能である。もちろん、こ
れ以外の不純物元素Ｂ、Ｐ、Ｎ、。In addition, examples of amorphous semiconductors include hydrogenated or fluorinated amorphous silicon, as well as S;, KGe, C=a
- It is also applicable to amorphous semiconductors containing Of course, other impurity elements B, P, N, etc.

０を言んでいても良い。You can say 0.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面によシ説明する。 Embodiments of the present invention will be described below with reference to the drawings.

実施例１ ここでｌ”ｔまず太陽電池に応用した場合の例を第４図
によシ述べる。尚（）内は、別金属を用いた場合を示す
。ガラス基板４１の上にＣｒ電極４２を例えばＡｒガス
を雰囲気とするスパッタ蒸着によシ膜厚０．３μｍに形
成する。その上にプラズマＣＶ　Ｄ　（Ｃｈｅｍｉｃａ
ｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉ　Ｌｉｏｎ）法で、基板
温度２３０ＣでＰ　Ｈ３ガスと５ＩＨ４ガスとを混合（
混合比ＰＨａ／ＳｉＨ４≧０．５■襲）したガスを用い
て、Ｐを含んだ水素化非晶質シリコン（ｎ増）４３１　
（ｉ層、つぎにｓ　ｉＨ４ガスのみで水素化非晶質シリ
コン（ｉ層）４３２を、さらにその上に＆Ｈｓ　ガスと
５ＬＨ４ガスとを混合（混合比Ｂ２Ｈ６／５ｉｉｔ４≧
０．５Ｖ％）したガスを用いてＢを含んだ水素化非晶質
シリコン（ｐ層）４３３を＋ｙｔ仄形酸形成。Embodiment 1 First, an example of application to a solar cell will be described with reference to FIG. is formed to a thickness of 0.3 μm by, for example, sputter deposition in an Ar gas atmosphere.
PH3 gas and 5IH4 gas are mixed at a substrate temperature of 230C using the Vapor Deposit Lion method.
Hydrogenated amorphous silicon containing P (n increase) 431 using a gas with a mixing ratio of PHa/SiH4≧0.5
(i-layer, then hydrogenated amorphous silicon (i-layer) 432 using only s iH4 gas, and on top of that, &Hs gas and 5LH4 gas (mixture ratio B2H6/5iit4≧
Hydrogenated amorphous silicon (p layer) 433 containing B was formed into a +yt-shaped acid using a gas containing 0.5V%).

各層の膜厚は例えば１層３００人、１層５４００Ａ、ｐ
層２００程度度で良い。つぎにその上全面に、基板温度
を１００〜２５０Ｃの範囲内（１００Ｕ以下では反応速
度が遅くなり、２５０層以上では水素が扱は出る割合が
多くなる）とし、　Ｃｒ（ｆ’ｔ）をＱ、１μｍ、その
上にＡｔ（Ａｕ）　を１　μｍ　（０，１μｍ）の厚み
に、蒸着（スパッタリング）で形成する。The thickness of each layer is, for example, 300 layers per layer, 5400 A per layer, p
A layer of about 200 degrees is sufficient. Next, on the entire surface, set the substrate temperature within the range of 100 to 250C (below 100U, the reaction rate will be slow, and above 250 layers, the proportion of hydrogen that will be released will increase), and set Cr(f't) to Q. , 1 μm thick, and At (Au) is formed thereon to a thickness of 1 μm (0.1 μm) by vapor deposition (sputtering).

この場合の所要加熱時間は約６０〜３０分である。The required heating time in this case is approximately 60 to 30 minutes.

もちろん、Ｃｒ（Ｐｔ）　のみを０．４μＩｎの厚みに
（ある程度厚く）形成しても良いが、　Ａ７．（ＡＬＩ
）を用いる方が電極抵抗が低くなる点で有利である。Of course, Cr(Pt) alone may be formed to a thickness of 0.4 μIn (to some extent thick), but A7. (ALI
) is advantageous in terms of lower electrode resistance.

即ち、以後の加工処理を容易にする点と電気抵抗値を破
適範囲にする点から、Ｃｒ（Ｐｔ）　の厚みは０．１〜
０．４μＩｎの範囲とすることが好筐しい。最後にホト
エツチング刀日工により、くシ形電極４５となる部分の
ＣｒｋＬ　（Ｐ　ｔ　−Ａ”　）だけを残し、その他の
部分のＣｒｋｔ　（Ｐ　ｔ−Ａｕ）は除去する。なお、
Ａｔ（Ｐｉ、Ａｕ）に対してはリン酸系（硝酸、塩酸系
）のエツチング１Ｍｆｔ用い、Ｃｒに対しては硝酸第２
セリウムアンモン溶液を用いる。これで、透明電極４４
とくし形電極４５とが形成できた。なお、上記の場合は
ガラス基板１１の上に’Ｉ　１１９層の顔に堆積すると
したが、全く逆の順に堆積しても艮い。この透明電極の
製法としては、基板を加熱せずに、Ｃｒ及び、Ａｔを蒸
着し、その後２００Ｃ程厩で加熱してもよい。さらに、
この上に例えば、スピンコードなどの方法で、干渉膜（
ＳＯＧ）　４６’を被覆する。これによシ、効率の高い
太陽電池が完成する。同、太陽電池は、上部くし形゛電
極４５が、相互に絶縁されている必＊は無いので、上記
干渉膜は、４電性のものも使用するととができる。もち
ろん、周囲の配線領域にあってはこの限シでないことは
、当然である。In other words, the thickness of Cr(Pt) should be 0.1 to 0.1 to facilitate subsequent processing and keep the electrical resistance within an appropriate range.
It is preferable to set it in the range of 0.4 μIn. Finally, by photo-etching, only CrkL (Pt-A'') in the part that will become the comb-shaped electrode 45 is left, and Crkt (Pt-Au) in the other parts is removed.
For At (Pi, Au), use 1Mft of phosphoric acid (nitric acid, hydrochloric acid) etching, and for Cr, use nitric acid (II) etching.
Use cerium ammonium solution. Now the transparent electrode 44
A comb-shaped electrode 45 was formed. In the above case, it is assumed that the 'I 119 layer is deposited on the glass substrate 11, but it is also possible to deposit it in the completely reverse order. This transparent electrode may be manufactured by depositing Cr and At without heating the substrate, and then heating the substrate at about 200C. moreover,
An interference film (
SOG) 46' is coated. This completes a highly efficient solar cell. Similarly, in the solar cell, the upper comb-shaped electrodes 45 do not necessarily have to be insulated from each other, so a tetraelectric interference film may also be used as the interference film. Of course, this is not the case in the surrounding wiring area.

ここでは、（）内で、Ｐｔ′ｔ−用いた例を示したが、
Ｐｄ、ルｈ、Ｃｏも使用できる。特にｐｔとｐｄは非晶
質シリコン層との間に゛電子に対する高い障壁を作るの
で、暗電流を低くおさえることができる。Here, an example is shown in which Pt't- is used in parentheses, but
Pd, Leh, and Co can also be used. In particular, since pt and pd create a high barrier to electrons between them and the amorphous silicon layer, dark current can be kept low.

障壁の高さが低い場合にはｐｆｆｌ非晶賀シリコン層を
金属と非晶質シリコン層の間に介伍させてやれば良い。If the height of the barrier is low, a pffl amorphous silicon layer may be interposed between the metal and the amorphous silicon layer.

実施例２ つぎにホトダイオードの場合の例を第５図によシ説明す
る。第５図は、断面構造を示す。ガラス基板５１の上に
Ｃｒを０．３μｍの厚みに形成し、ホトエツチング加工
によりＣｒ屯積極５２形成する。その上に、実施例１の
場合と全く同様國、〜プラズマＣＶＤｍで水素化非晶質
シリコンの１層５３１．１層５３２．９層５３３を順次
形成し、その後、ホトエツチング加工によシ一部分の水
素化非晶質シリコンを残し、あとは除去する。１除去は
ＣＦ４ｆ用いたプラズマアッシャで行なう。その後、基
板温度を１００〜２５０Ｃの範囲内とし、Ｃｒ７ｉ−０
゜１μｍ厚、ＡＡ’：１μｍ厚、抵抗加熱蒸着で形成す
る。最後にホトエツチング加工により一部分のＣｒ−Ａ
ｔ５５ｉ残し、その他のＣｒ−ＡＡは除去する。この部
分のみに相互作用により形成された透明電極５４が残り
、ここが即ち、ホトダイオードの受光窓となる。このよ
うに光を入射させたい部分のＣｒ−Ａｔを除去すればそ
こに透明電極が残）、その他の部分は遮光用の金属をも
兼ねるの士、受光面積を正確にしかも簡単に規定できる
ことになる。その後、実施例ｌと同様にして、干渉膜５
６を形成する。これでホトダイオードが完成する。Embodiment 2 Next, an example in the case of a photodiode will be explained with reference to FIG. FIG. 5 shows a cross-sectional structure. Cr is formed to a thickness of 0.3 μm on a glass substrate 51, and a Cr layer 52 is formed by photoetching. On top of that, one layer 531, one layer 532, and nine layers 533 of hydrogenated amorphous silicon were sequentially formed by plasma CVD in exactly the same manner as in Example 1, and then a portion of the silicon layer 533 was removed by photoetching. The hydrogenated amorphous silicon is left behind and the rest is removed. 1 removal is performed with a plasma asher using CF4f. After that, the substrate temperature was set within the range of 100 to 250C, and the Cr7i-0
゜1 μm thick, AA': 1 μm thick, formed by resistance heating vapor deposition. Finally, a portion of the Cr-A is etched by photo-etching.
Leave t55i and remove other Cr-AA. The transparent electrode 54 formed by interaction remains only in this portion, which becomes the light receiving window of the photodiode. In this way, if you remove the Cr-At in the area where you want light to enter, a transparent electrode remains there), and the other areas also serve as light-shielding metal, making it possible to accurately and easily define the light-receiving area. Become. Thereafter, in the same manner as in Example 1, the interference film 5
form 6. The photodiode is now completed.

ここでハ藺単のため、１１固のホトダイオードを形成す
る場合の例を示し之が、全く同様に、ホトマスクを変え
ることによシ、−次元あるいは二次元のホトダイオード
アレイを形成することも容易にできることはもちろんで
ある。なお、前記の場合、Ｃｒの上にＡｔを形成した金
属を用いたが、Ｃｒの代わシにＣｒ３Ｃ主体とするＣｒ
ｐＪ　ｉのような金属やＭＯ＃　Ｗも使用でき、また、
Ａｔの代わりにｈｕ、　Ｎｉ、ｐｉなども使用できるこ
とはもちろんである。さらに、水素化非晶質シリコンの
９層５３３はなくても実用上差しつかえない。For the sake of simplicity, we will show an example of forming an 11-dimensional photodiode, but in the same way, it is also easy to form a -dimensional or two-dimensional photodiode array by changing the photomask. Of course it is possible. In the above case, a metal in which At was formed on Cr was used, but instead of Cr, Cr mainly composed of Cr3C was used.
Metals such as pJi and MO#W can also be used, and
Of course, hu, Ni, pi, etc. can also be used instead of At. Further, the nine layers 533 of hydrogenated amorphous silicon may be omitted for practical purposes.

実施例３ 一次元センサとして、マトリクスｍｓ着層形センサがあ
る。この例として、特開昭５２−１２９２５８　がある
。この棟の一次元センサは、第６図に示すように、２つ
のダイオード（図中にＤｉ、Ｄｐと表示）が互いにその
極性が逆になるｔう直列に接続されたものが複数個−次
元に配列された構成となっている。２６は駆動回路、２
７は読取回路である。Example 3 As a one-dimensional sensor, there is a matrix ms layered sensor. An example of this is JP-A-52-129258. As shown in Figure 6, the one-dimensional sensor in this building consists of two diodes (indicated as Di and Dp in the diagram) connected in series with opposite polarities. The structure is arranged in . 26 is a drive circuit, 2
7 is a reading circuit.

本発明はこのようなダイオード構成の一次元センサを製
作するのに最も適している。以下第７図を用いてその製
作工程を説明する。第７図（ａ）は平面構造を、（ｂ）
に断面構造を示す。２８はガラス基板であυ、この上に
基板温就２００ＣでＣａ膜を０．２μｍ厚に真空蒸着あ
るいはスパック蒸着する。The present invention is most suitable for manufacturing a one-dimensional sensor having such a diode configuration. The manufacturing process will be explained below using FIG. 7. Figure 7 (a) shows the planar structure, (b)
shows the cross-sectional structure. Reference numeral 28 denotes a glass substrate, on which a Ca film is vacuum-deposited or spun-deposited to a thickness of 0.2 μm at a substrate temperature of 200C.

その後、ホトエツチング加工によ１）Ｃｒ寛他極２９形
成する。この上に、実施例１，２の場合と同様に、水素
化非晶質シリコン３７を堆積し、図のように加工する。Thereafter, 1) Cr-free other electrode 29 is formed by photo-etching. Hydrogenated amorphous silicon 37 is deposited thereon in the same manner as in Examples 1 and 2, and processed as shown in the figure.

この層はプラズマＣＶＤ（Ｃｈｅｍｉｃａｌ　■ａｐｏ
ｒ　Ｄｅｐｏｓｉｔｉｏｎ）法によシ基板温［２００Ｃ
〜２５０Ｃで形成する。各層の作成には原料ガスとして
ｎ層にはＰＨｓガスと５ＩＨ４ガスとを混合したガス（
混合比ＰＨｓ　／　８　ｉＨ４≧０．５体積チ）１−１
層層には５ｉＩ（４ガスを、ｐ層には＆　Ｈａガラス５
１）（４ガスとを混合したガス（混合比ＢｇＨａ／Ｓ’
Ｈ４≧０．５体積ｑ６）を用いる。各層の膜厚は例えば
１層３００人、１層５４００ｃ％ｐｔｍ２５０Ａ程度で
良い。この水素化非晶質シリコン層のうちダイオードと
する部分のみを残してエツチングする。つぎに、全面に
絶ｄ膜３０（１＋ｉｌえば石英ガラスが使用できる）を
スパッタ蒸着によシ１μｍ厚以上形成し、ホトエツチン
グ加工によりコンタクト穴ａｉ、３２’、３３．ａ４＊
形成する。This layer is made using plasma CVD (Chemical ■apo
The substrate temperature [200C
Form at ~250C. To create each layer, the raw material gas is a mixture of PHs gas and 5IH4 gas (
Mixing ratio PHs/8 iH4≧0.5 volume CH) 1-1
5iI (4 gas for the layer, &Ha glass 5 for the p layer)
1) (Gas mixed with 4 gases (mixture ratio BgHa/S'
H4≧0.5 volume q6) is used. The thickness of each layer may be, for example, about 300 layers per layer and 5400 c% PTM 250 A per layer. This hydrogenated amorphous silicon layer is etched leaving only the portion to be used as a diode. Next, an insulated film 30 (quartz glass can be used if 1+il) is formed on the entire surface by sputter deposition to a thickness of 1 μm or more, and contact holes ai, 32', 33. a4*
Form.

エツチング液としては７ツ販系のエツチング液を使用す
る。この上に１基板温度ｔ−１００〜２５０Ｃとして、
ＣｒをＱ、１μｍ厚、Ａｔを１．５μｍ厚、蒸着で形成
する。その後、ホトエツチング加工エによυＣｒ−Ａｔ
ｔｉ１極３５を形成する。このとき。As the etching liquid, a commercially available etching liquid is used. On top of this, one substrate temperature is t-100~250C,
A 1 μm thick Cr film and a 1.5 μm thick At film are formed by vapor deposition. After that, υCr-At was processed by photo-etching process.
ti1 pole 35 is formed. At this time.

ホトダイオード近傍上のコンタクト穴３２の内部のＣｒ
−人ｔをも同時に除去することにより、ホトダイオード
上には透光性め導電体層である透明電極３６が残ること
にな）、これが光入射のための窓となる。さらに、この
上に絶縁性干渉膜７６を形成することにょ如素子の保護
をもでき為ものである。このように、本実施例に本発明
を適用すれば、簡単な製作工程で７２クスＮＩＡ動形の
一次元センサが実現できる。ここではＣｒ’酊＋ｆ＆２
９を用いるとしたが、この他にも、’　Ｔ　ａ＊　ＮＩ
　Ｃｒ　。Cr inside the contact hole 32 near the photodiode
- By removing the person t at the same time, a transparent electrode 36, which is a light-transmitting conductive layer, remains on the photodiode), which serves as a window for light incidence. Furthermore, by forming an insulating interference film 76 thereon, the elements can be protected. As described above, by applying the present invention to this embodiment, a 72x NIA dynamic type one-dimensional sensor can be realized with a simple manufacturing process. Here Cr'drunk + f&2
9 was used, but in addition to this, ' T a * NI
Cr.

ＭＯ，ｗ＊　Ａｌ、Ｐ　ｔ、ｐｔｉなどの全編も同様に
使用できる二また、これらを多層にしても勿緬良い。MO, w*Al, Pt, pti, etc., can be used in the same way, and it is also possible to use these in multiple layers.

また透明電極を形成するための金ＦＡ膜及びこれを〃ロ
エして得た上部金属配置３５にはＣｒ−Ａｔの２層構造
としたが、Ｃｒ、Ｍｏｂ　Ｔｉｎ　ＶｔＺｒ、Ｎｂ、ｌ
　Ｔａ＃　ｗ、Ｈｆａ　Ｎｉ、Ｐ　ｔ、ｐｃｉ。In addition, the gold FA film for forming the transparent electrode and the upper metal arrangement 35 obtained by rolling it had a two-layer structure of Cr-At, but Cr, Mob Tin VtZr, Nb, l
Ta#w, Hfa Ni, Pt, pci.

Ｃｏ、ｉｈのうちの１４′Ｉｉまたはそれを主体とする
金属を非晶質シリコン層と接触する層とする構造であれ
ば１層であっても多層であっても問題はない。またここ
では加熱して堆積したが、堆積後１００〜２５０Ｃで加
熱してもよい。There is no problem whether the layer is one layer or multiple layers, as long as the layer is made of 14'Ii of Co, ih, or a metal mainly composed of 14'Ii of Co, ih, and is in contact with the amorphous silicon layer. Further, although the deposition was performed here by heating, it may be heated at 100 to 250 C after deposition.

さらにここでは共通配線側を分離ダイオードとしたが、
分離ダイオードとホトダイオニドの位置を入れかえても
よい。Furthermore, here the common wiring side is used as a separation diode, but
The positions of the separation diode and the photodiode may be interchanged.

実施例４ 本実施例の断面構造を第８図に示す。これは実施例３と
ほとんど同じであシ、異なる点は、実施汐ｌ１３ではホ
トダイオード上だけに透明電極３６を残したが、本実施
例ではホトダイオード近傍の図示Ａの部分のＣｒ−Ａｔ
を除去している点である。Example 4 The cross-sectional structure of this example is shown in FIG. This is almost the same as in Example 3, and the difference is that in Example 113, the transparent electrode 36 was left only on the photodiode, but in this example, the Cr-At part in the area A near the photodiode was left.
The point is that it removes.

こうすることによって、図中に矢印で示すようにカラス
基板２８の下側から先天を入射させることが可ＭＱとな
る。即ち、ガラス基板２８の下側から光りを入射させ、
七ンテに近接して配置された原稿Ｍで反射した光をホト
ダイオードに入射させ、光電変換して原稿Ｍを読取る方
式の素子として用いることができる。By doing so, it is possible to make the MQ possible to enter the congenital light from the lower side of the glass substrate 28 as shown by the arrow in the figure. That is, light is incident from the lower side of the glass substrate 28,
It can be used as an element for reading the original M by making the light reflected by the original M placed close to the scanner enter the photodiode and photoelectrically converting it.

また、ここではスピンコードによるＳＯＧを用いた例を
示したが、先に述べたごと＜　Ｓ　１３Ｎ４　。In addition, here we have shown an example using SOG using a spin code, but as stated earlier < S 13N4.

５ｉＣｈ、ＳｉＯ，５ｉＯＮ　、　ホ）ＶジスＸＤｊう
な４機物質、ＩＴｏ、８ｒ１０２等の透明導電物質であ
ってもよい。It may also be a transparent conductive material such as 5iCh, SiO, 5iON, 5iCh, SiO, 5iON, ITo, 8r102, etc.

実施例５ 本発明は、特にＩＴＯや５ｎＯ−のごとき透明導電膜を
積層する場合には本発明の効果が顕著に現われる。Example 5 The effects of the present invention are particularly apparent when transparent conductive films such as ITO and 5nO- are laminated.

第９図は本実施例の断面図でステンレス基板９１の上に
グロー放電法によ−Ｊ）ｐ−ｉ−ｎ接点のａ−８３：Ｈ
膜９３１，９３２．９３３ｔ−積層堆積する。その厚さ
は各々５００，５２００．１８０人であった。次にＣｒ
９４を基板謳［２００Ｃで２００人蒸着する。この場合
の加熱時間は約２０分間であった。次に硝＊第２セリウ
ムアンモン溶液を用いてＳｉと反応していないＣｒをエ
ツチングして除去する。次に電子ビーム、蒸庸法により
ＩＴＯＱ５を約２０００人堆積させ、太陽電池を構成し
た。この株な構造、特にａ−８ｉとＩＴＯの間にＢｉと
反応したＣｒ　９４層を形成することによりＩＴＯ９５
とａ−８ｉ９３１．９３２，９３３の直接の反応を防ぎ
、ＩＴＯ９５とａ−８ｉ９３１゜９３２．９３３の接触
抵抗を小さくすることが出来た。そのためＣｒ膚を用い
ない太１１！ｉ［池のＡＭ−１（ｉ　ｏ　ｏ　ｒｎＷ／
ａ／１　）光に対Ｔ　るｆ！変［３ｄ１６．７チに比べ
て、本発明の４３図の構成の太陽電池は７．１チと萬い
効４をもつことが明らかとなった。この株な効果はａ−
８ｉとＩＴＯＯ間だけでなく、微結晶を含むＳｉとの間
や、これらと５ｎＣｈ等の酸化物透明！極との間でも効
果があることがわかった。また第１θ図のスタンクドセ
ル構造の場合のセル間の低抵抗接続のためにも有効であ
ることがわかった。FIG. 9 is a cross-sectional view of this embodiment, and a glow discharge method was applied on a stainless steel substrate 91 to a-83:H of the pin contact.
Films 931, 932, and 933t are stacked and deposited. Their thickness was 500, 5200, and 180 people respectively. Next, Cr
94 was deposited on the substrate by 200 people at 200C. The heating time in this case was about 20 minutes. Next, Cr that has not reacted with Si is removed by etching using a solution of nitric acid and ceric ammonium. Next, approximately 2,000 ITOQ5 layers were deposited by electron beam and evaporation methods to construct a solar cell. This unique structure, in particular, by forming a Cr94 layer reacted with Bi between a-8i and ITO, ITO95
It was possible to prevent the direct reaction between ITO95 and a-8i931.932,933, and to reduce the contact resistance between ITO95 and a-8i931°932.933. Therefore, 11 times without using Cr skin! i [Ike no AM-1 (i o o rnW/
a/1) T against light f! It has been revealed that the solar cell of the present invention having the configuration shown in Figure 43 has an efficiency of 7.1 inches, compared to 16.7 inches (3d and 16.7 inches). This strain's effect is a-
Transparent not only between 8i and ITOO, but also between Si containing microcrystals, and between these and 5nCh oxides! It was found to be effective even between poles. It has also been found that this method is effective for low-resistance connections between cells in the case of the stood cell structure shown in FIG. 1θ.

第１０図において、１０１は基板、１０２は例えばＣＴ
ａ極、１０３１．１０３２．１０３３．１０３４゜１０
３５及び１０３６はａ−８ｉ：Ｈで６Ｄ、それぞれＨ−
ｉ　−ｐの層状ＶＣなっている。１０４１及び１０４２
は、ＣｒとＳｉの反応した透明電極層、１０５はＩＴＯ
である。In FIG. 10, 101 is a substrate, 102 is, for example, a CT
a pole, 1031.1032.1033.1034°10
35 and 1036 are a-8i:H and 6D, respectively H-
It is an i-p layered VC. 1041 and 1042
is a transparent electrode layer made of reacted Cr and Si, 105 is ITO
It is.

このような構成を採ることにより、上層と、下層の特性
ｔ−変え、主として吸収する波長ヲ震えてやると、更に
高効率の太陽電池が得られるものである。By adopting such a configuration, if the characteristics t of the upper layer and the lower layer are changed and the wavelengths that are mainly absorbed are made to oscillate, a solar cell with even higher efficiency can be obtained.

実施例６ 本発明を光導電膜を用いた固体４ＪｔＬ像素子に適用し
た例を示す。これは特−昭５１−１０７１５に示されて
いるように二次元状に配列したスイッチと上記スイッチ
を介して取出した光学像に相当する光電荷を転送する走
査する走査素子を少なくとも有する半導体基板（走査用
ＩＣ基板）上に光電変換用として非晶貞水素化シリコン
等の光導電体層よりなる光導電膜を形成され更に干ｅｒ
ａで被覆されている素子である。第１１図はこの素子の
基本的構造を示している。走査用ＩＣｓ分は通常の半導
体装置の工程を用いて製造される。ｐ形シリコン基板６
１上に８００人程鹿の薄い８ｊＯｘ膜を形成し、この８
ｊＯｚ膜上の所定の位置に１４００Ａ程度の８１ｓＮ＜
膜を形成する。８１Ｃｈ膜は通常のＣＶＤ法−８”ｓＮ
Ｊ！はＳ　ｊｓＮ４．　Ｎ　ｘを流したＣＶＤ法によっ
た。次いでル：０２＝１：８雰囲気中でシリコンを局所
酸化し、５ｊＯｚ層６８を形成する。この方法は一般に
ＬＯＣＯ８と呼ばれている素子分離のためのシリコンの
局所酸化法である。一度、前述ｏＢｓ、Ｎ４膜および５
ｊＯｚ膜を除去し、ＭＯ８）　５ンジスタのゲート絶縁
膜をＳｉｎ！！で形成する。Example 6 An example in which the present invention is applied to a solid-state 4JtL image element using a photoconductive film is shown. As shown in Japanese Patent Application No. 51-10715, this is a semiconductor substrate ( A photoconductive film made of a photoconductor layer such as amorphous hydrogenated silicon is formed on the scanning IC substrate for photoelectric conversion, and further dried.
This is an element covered with a. FIG. 11 shows the basic structure of this element. The scanning ICs are manufactured using normal semiconductor device processes. p-type silicon substrate 6
Form a thin 8jOx film of about 800 people on top of 1, and this 8
81sN of about 1400A at a predetermined position on the jOz film
Forms a film. 81Ch film is made by normal CVD method - 8”sN
J! is S jsN4. A CVD method using Nx was used. Next, the silicon is locally oxidized in a 1:8 atmosphere to form a 5jOz layer 68. This method is generally called LOCO8 and is a local oxidation method of silicon for element isolation. Once, the aforementioned oBs, N4 membrane and 5
Remove the JOz film and apply the MO8) 5 resistor gate insulating film to Sin! ! to form.

次いでポリシリコンによるゲート部６９および拡散領域
７０．６０を形成し、更にこの上部に８ｊＯｘ膜ｆ：形
成する。そしてこの膜中に不純物領域６．０１ｃ対する
電極域シ出し口をエツチングで開孔する。電極６２１と
してＡｔｋ８０００人蒸着する。Next, a gate portion 69 and diffusion regions 70 and 60 made of polysilicon are formed, and an 8jOx film f: is further formed on top of the gate portion 69 and diffusion regions 70 and 60. Then, an opening for the electrode area corresponding to the impurity region 6.01c is opened in this film by etching. Atk 8000 is deposited as the electrode 621.

更にＳｉＯ＊ｍ６３ｔ−１５００人形成し、続イテ不純
物領域７０の上部にこれに対する′ｌＬ極取り出し口を
エツチングで開孔し、′＃Ｌ極６２２としてＡｔ又はＭ
　ｏ　ｆ　１μｍ蒸着する。なお電極６２２は領域７０
．６０およびゲート部を覆う如く広く形成した。これは
素子間の信号処理領域に光が入射するとプルーミングの
原因となシ望ましくないためである。Further, 63t-1500 SiO*m were formed, and a 'lL electrode outlet for this was etched on the upper part of the subsequent impurity region 70, and At or M was formed as the '#L electrode 622.
Deposit o f 1 μm. Note that the electrode 622 is located in the area 70.
．． 60 and the gate portion. This is because if light enters the signal processing region between the elements, it may cause pluming, which is undesirable.

光導電膜６５はスパッタリングによって形成する。雰囲
気はＡｒと水素の混合ガスで０．２Ｔｏｒｒとした。水
素富有蓋は６モルチである。シリコンｐ−ゲントｅ用い
、周波数１３．５６ＭＨ２，入力３００Ｗで反応性スパ
ッタを行ない、前記走査用ＩＣｉ板上に光導電膜を１μ
ｍ堆積する。この後、Ｐｔをスパッタリングによ〃基板
温度１００〜２５０ｃで２０００人堆槓す堆積その後、
第１２図の画素部分の平面図のよりに画素を区切る形に
パターン化する。これによ、！ｌｌ１画素上部には透明
導電１１！６４が形成され、同時に一画素の光のとりこ
み角ｋ　１ｌｌＪ限して解像度を上げる遮光＄６７とす
る串ができる。The photoconductive film 65 is formed by sputtering. The atmosphere was a mixed gas of Ar and hydrogen at 0.2 Torr. The hydrogen-rich lid is 6 molt. Using silicon p-gent e, reactive sputtering was performed at a frequency of 13.56 MH2 and an input of 300 W, and a photoconductive film of 1 μm was deposited on the scanning ICi plate.
Deposit m. After this, Pt was deposited by sputtering for 2000 times at a substrate temperature of 100-250c.
The pixel is patterned into sections according to the plan view of the pixel portion shown in FIG. This is it! A transparent conductor 11!64 is formed above the ll1 pixel, and at the same time, a skewer is formed that limits the light intake angle k 1llJ of one pixel to a light shielding angle of $67 to increase the resolution.

透光部６７は、半導体と反応していない金属層によって
、構成されている。The light-transmitting portion 67 is made of a metal layer that does not react with the semiconductor.

この後、透明電膜６４及び、透光部６７の上部に、干渉
膜６６を設けて、本発明の構成を得る。Thereafter, an interference film 66 is provided on the transparent electrical film 64 and the transparent portion 67 to obtain the structure of the present invention.

ここでは走査用ＩＣとしてはＭＯＳ）ランジスタを用い
たものを使ったが１．　Ｃ０Ｄ−Ｂ１３Ｄ　を利用した
ものについても同様に適用ｃｒＪ能である事はいうまで
もない。Here, a scanning IC using a MOS transistor was used.1. It goes without saying that crJ functions can be similarly applied to those using C0D-B13D.

遮光部６７ｆ、必要としない場合は、肌面の周辺部のみ
にｐｔを残しても特に問題はない。If the light shielding part 67f is not needed, there is no problem in leaving the pt only on the peripheral part of the skin surface.

水素化非晶質シリコンに対するドーパントとしてここで
はＢとＰを用いた例であるが、Ｎ、Ｃ。In this example, B and P are used as dopants for hydrogenated amorphous silicon, but N and C are also used.

０、Ｇｅ等も使える事はいうまでもない。またダングリ
ングボンドのターミネータとしてＨのかわシにＦを用い
てもよい。It goes without saying that 0, Ge, etc. can also be used. Further, F may be used in place of H as a terminator for a dangling bond.

〔発明の効果〕〔Effect of the invention〕

本発明によれば高感度な非晶質シリコン受光累子を簡単
な製造工程により得る事ができる。筐た、干渉膜の材料
１１：適当に選べば保護膜の役割を果させる事ができる
。According to the present invention, a highly sensitive amorphous silicon photodetector can be obtained through a simple manufacturing process. Material 11 for the casing and interference film: If selected appropriately, it can serve as a protective film.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、従来技術による太陽電池の断面図、第２図は
、従来技術によるホトダイオードの断面図、第３図は、
光の反射に対する干渉膜の影響を示す図、第４図は本発
明を太陽電池に適用した場合の断面図、第５図は、本発
明をホトダイオードに適用した場合の断面図、第６図は
、−次元センサの回路図、第７図（ａ）は−次元センサ
の平面図、第７図（ｂ）Ｉ′ｉ、−次元センサの断面図
、第８図、第９図、第１０図及び、第１１図は、本発明
の更に他の実施例を示す断面図、第１２図は、第１１図
の千圓図である。 １．２１，２８，４１，５１，６１，９１，１０１・・
・基板、２，２２．２９，４２，５２，６２１゜６２２
．１０２・・・電極層、３．２３．３７，４３１４３２
゜４３３，５３１，５３２，５３３，９３１゜９３２、
９３３．１０３１．１０３２．１０３３．１０３４゜１
０３５．１０３６・・・半導体層、４，２４．３６゜４
４．５４，９４．１０４ｉ、１０４２・・・透明電極層
、５．２５，３５，４５．５５・・・上部電極、４６゜
５６．６６．７６．９６．・１′０６・・・干＃膜、６
５・・・光導電膜、６３．６８・・−酸化膜、６９・・
・ゲート第　１　図 第　２　図 第　３　国 第　！５　図 第　７　図 ３、．５ 第　８　図　。FIG. 1 is a sectional view of a solar cell according to the prior art, FIG. 2 is a sectional diagram of a photodiode according to the prior art, and FIG. 3 is a sectional view of a photodiode according to the prior art.
A diagram showing the influence of an interference film on light reflection. Figure 4 is a cross-sectional view when the present invention is applied to a solar cell. Figure 5 is a cross-sectional view when the present invention is applied to a photodiode. Figure 6 is a cross-sectional view when the present invention is applied to a photodiode. , a circuit diagram of the -dimensional sensor, FIG. 7(a) is a plan view of the -dimensional sensor, FIG. 7(b) is a sectional view of the -dimensional sensor, FIGS. 8, 9, and 10. 11 is a sectional view showing still another embodiment of the present invention, and FIG. 12 is a 1000-degree diagram of FIG. 11. 1.21, 28, 41, 51, 61, 91, 101...
・Substrate, 2, 22.29, 42, 52, 621°622
．． 102... Electrode layer, 3.23.37, 431432
゜433,531,532,533,931゜932,
933.1031.1032.1033.1034゜1
035.1036...Semiconductor layer, 4,24.36°4
4.54, 94.104i, 1042... Transparent electrode layer, 5.25, 35, 45.55... Upper electrode, 46° 56.66.76.96.・1'06...Dry #membrane, 6
5... Photoconductive film, 63.68... - Oxide film, 69...
・Gate 1st figure 2nd figure 3rd country! 5 Figure 7 Figure 3. 5 Figure 8.

Claims (1)

【特許請求の範囲】 １、所定基板上に半導体よシなる第１の層と、との第１
の層と金属膜との界面反応によって形成４’） された透光性が導電性の第２の層を少なくとも有する半
導体装置において、この′ＩＡ２の層の上に、少なくと
も１層の透光性の＃を有する事を特徴とする半導体装置
。 ２、上記第１）＃ｋが８１′ｆｃ主体とし、少なくとも
水素または弗素を言む非晶質半廊体である事を特徴とす
る特許請求の範−第１ＪＡの半導体装置。 ３、上記第１層がＳｉを主体とし、少なくとも水片 累または弗素を含む、かつｃ、　Ｇｅのいずれかを言む
事を特徴とする特許請求の範囲第１項の半導体装置。 ４−前Ｆｅ金属膜は、Ｃｒ、Ｍｏ＋　Ｗｅ　Ｔ’＃　Ｌ
Ｚｒ、ＮｂｅＴａ、Ｈｆ、Ｎｉ、Ｐｔ、Ｐｄ＋Ｈ，ｈ及
びＣＯのうちいずれか一つ又は、二以上の金塊を含むこ
とを特徴とする特許請求の範囲第１項記載の半導体装置
。 ５、所定基板上に半導体層を形成する工程、該半導体層
上に金属膜を形成する工程、前記半導体層と前記金属膜
を反応させる工程、該反応によって形成された層と反応
していない並属層のうちプ望部分を床去する工程、上記
金属層及び、又は、反応層上に干渉膜を形成する工程よ
シ成ることを％倣とする半導体装置の製造方法。[Claims] 1. A first layer made of a semiconductor on a predetermined substrate;
In a semiconductor device having at least a conductive second layer formed by an interfacial reaction between a layer of IA2 and a metal film, at least one light-transmitting layer is formed on this layer of IA2. A semiconductor device characterized by having #. 2. The semiconductor device according to claim 1 JA, characterized in that #1) #k is an amorphous half-cell body containing at least 81'fc and at least hydrogen or fluorine. 3. The semiconductor device according to claim 1, wherein the first layer is mainly composed of Si, contains at least water particles or fluorine, and is either c or Ge. 4-Pre-Fe metal film is Cr, Mo+ We T'#L
The semiconductor device according to claim 1, characterized in that the semiconductor device contains gold ingots of one or more of Zr, NbeTa, Hf, Ni, Pt, Pd+H, h, and CO. 5. A step of forming a semiconductor layer on a predetermined substrate, a step of forming a metal film on the semiconductor layer, a step of reacting the semiconductor layer and the metal film, and a step of forming a layer that has not reacted with the layer formed by the reaction. A method for manufacturing a semiconductor device comprising the following steps: removing a desired portion of the metal layer, and forming an interference film on the metal layer and/or the reaction layer.
JP58190745A 1983-10-14 1983-10-14 Semiconductor device and manufacture thereof Pending JPS6083382A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58190745A JPS6083382A (en) 1983-10-14 1983-10-14 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58190745A JPS6083382A (en) 1983-10-14 1983-10-14 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS6083382A true JPS6083382A (en) 1985-05-11

Family

ID=16263042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58190745A Pending JPS6083382A (en) 1983-10-14 1983-10-14 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS6083382A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0235785A2 (en) * 1986-03-03 1987-09-09 Kanegafuchi Kagaku Kogyo Kabushiki Kaisha Semiconductor device
JP2014130982A (en) * 2012-11-29 2014-07-10 Kyocera Corp Photoelectric conversion device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0235785A2 (en) * 1986-03-03 1987-09-09 Kanegafuchi Kagaku Kogyo Kabushiki Kaisha Semiconductor device
JP2014130982A (en) * 2012-11-29 2014-07-10 Kyocera Corp Photoelectric conversion device

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