TW451320B

TW451320B - Method of integrating anti-reflection layer and salicide block

Info

Publication number: TW451320B
Application number: TW89110938A
Authority: TW
Inventors: Chung-Yau Chen; Jen-Bin Lin; Feng-Ming Liou
Original assignee: United Microelectronics Corp
Priority date: 2000-06-05
Filing date: 2000-06-05
Publication date: 2001-08-21

Abstract

This invention provides a method to integrate anti-reflection layer and salicide block, which at least consists of: provision of a substrate containing at least a sensor area and a transistor area, in which the sensor area at least includes a doped area and the transistor area contains at least a transistor formed by gate, source and drain; formation of a composite layer on the substrate covering the doped area and transistor to increase the reflection rate of light entering the composite layer at the doped area; use of lithography and etching processes to remove certain area of composite layer to expose the top of gate, source and drain; and performing salicide process to form metal silicide at the top of gate, source and drain. This method is characterized mainly by the employment of the composite layer which can function as both an anti-reflection layer for the sensor area and a salicide block for the transistor area. The composite layer consists of many overlapping layers and the adjacent layers have different refractive indexes.

Description

451320 五、發明說明（1) 5-1發明領域：本發明係有關於整合反反射層（an t i_ref 1 ect i 〇n layer)與自行對準石夕化物阻塞（saHcide block)的方法’特別是可以簡化光線偵測元件之製造程序的方法。 5-2發明背景：隨著半導體技術的進步以及是場對小尺寸元件日益增加的需求，將多數不同功能單元整合在一個晶片中之微小高功能元件的重要性是日漸重要的，例如同時使用了光線二極想（photodiode)與電晶艘（transistor)的光線偵測元件°但由於任一個具某特定功能的單元皆有其特定的結構與製造程序，因此在整合多數不同功能之單元時，常常會遇到彼此的製程不相容的困擾，特別是當某個單元顯然較為繁複時（如互補式金氧半導體）^而最常見的解決方法便是將整個元件（晶片）分成數個部份，而不同部份係分別製造的（亦即在處理某個部份時先將其它部份以光阻等覆蓋） ’然而如此作法無可避免地會遇到製造時·間增加以及反應物銷耗量增加等的缺失。就常用在諸如數位相機與掃瞄器等的光線偵測元件而言’如第一 A圖所示之基本結構示意圖，光線偵測元件係形成在底材10上並至少包含偵測器區域（sensor area)ll451320 V. Description of the invention (1) 5-1 Field of the invention: The present invention relates to a method for integrating an anti-reflective layer (an t i_ref 1 ect i 〇n layer) and a self-aligned saHcide block. It is a method that can simplify the manufacturing process of light detection elements. 5-2 Background of the Invention: With the advancement of semiconductor technology and the increasing demand for small-sized components, the importance of integrating small and highly functional components with most different functional units in one chip is becoming increasingly important, such as simultaneous use The photodiode and the light detector of the transistor are included. However, since any unit with a specific function has its specific structure and manufacturing process, when integrating most units with different functions, , Often encounter the problem of incompatible processes, especially when a unit is obviously more complicated (such as complementary metal-oxide semiconductors) ^ and the most common solution is to divide the entire component (chip) into several Parts, and different parts are manufactured separately (that is, the other parts are covered with photoresist, etc. when processing one part) 'However, this method will inevitably encounter increase in production time and response Lack of increased consumption of goods, etc. As for the light detection elements commonly used in digital cameras and scanners, as shown in the first diagram A, the light detection elements are formed on the substrate 10 and include at least the detector area ( sensor area) ll

451320 五、發明說明（2) 與電晶體區域（transistor area)12二個部份。在此底材 10上存在多數個隔離1〇2，在偵測器區域Η存在一些彼此間被隔離102所分開的攙雜區ιοί，而在電晶體區域12中存在一些由閘極121、源極122 '汲極123與間隙壁124所組成的電晶艘’並且金屬矽化物125位於閘極121、源極122與汲極123之上》此外’介電層13位於底材1〇上並覆蓋所有前述的結構，多重内連線14位於介電層13上並且可以進一步連接到各電晶體’而覆蓋層15則位於介電層13上並完整覆蓋住多重内連線14，並且濾光器16位於偵測器區域11内之覆蓋層15上。此外’由於濾光器16是用來讓特定波長的光線直接投射在特定的攙雜區1〇1中，因此不僅在任一個換雜£101上通常存在一個渡光器16，而且除了連接到挽雜區11邊緣的導線外’不會有任何不透光線的結構（如多重内連線14)會位於任一個攙雜區101與相對應的濾光器16 之間。無論如何’在偵測器區域丨丨中，由於經濾光器丨6入射到攙雜區101的光線的部份會被反射，而由於入射的光線並非總是垂直入射，因此反射光線是任何方向都可能的。顯然地’此時若反射回去的光線又被不透光的多重内連線 14所反射’很可能會造成不同之攙雜區1〇1相互干擾，造成所謂的交叉干擾現像（crosstalk phenomena)。亦即任一個攙雜區101皆無法分辨所接收的光線是直接自相對應的濾光器16進來光線或是自多重内連線丨4而來的雜訊。因451320 V. Description of the invention (2) and transistor area 12 two parts. There are a plurality of isolations 102 on this substrate 10, and there are some impurity regions separated from each other by the isolation 102 in the detector region. In the transistor region 12, there are some gates 121 and source electrodes. 122 'Electric crystal boat composed of drain 123 and spacer wall 124' and metal silicide 125 is located on gate 121, source 122 and drain 123. In addition, 'dielectric layer 13 is located on substrate 10 and covered In all the aforementioned structures, the multiple interconnects 14 are located on the dielectric layer 13 and can be further connected to the transistors', while the cover layer 15 is located on the dielectric layer 13 and completely covering the multiple interconnects 14 and the filter 16 is located on the cover layer 15 in the detector area 11. In addition, 'because the filter 16 is used to directly project light of a specific wavelength into a specific impurity region 101, there is usually not only an optical filter 16 on any one of the hybrids £ 101, but in addition to the There will not be any opaque structures (such as multiple interconnects 14) outside the wires at the edges of the area 11 between any doped area 101 and the corresponding filter 16. In any case 'in the detector area, since the part of the light incident on the doped area 101 through the filter 6 is reflected, and since the incident light is not always incident perpendicularly, the reflected light is in any direction Both are possible. Obviously, 'at this time, if the reflected light is reflected by the opaque multiple interconnects 14', it is likely to cause different doped areas 101 to interfere with each other, resulting in so-called crosstalk phenomena. That is, any of the noise regions 101 cannot distinguish whether the received light is light coming directly from the corresponding filter 16 or noise coming from the multiple interconnections 4. because

451320 五、發明說明（3) 此，如第一 B圖所示，必需在形成介電層13前先形成反反射層17於各攙雜區101之上’藉以確保自任一攙雜區反射的光線都會在被反射回去兒不會相互干擾。一般而言，反反射層17的材料為氮化欽、欽或鶴欽化合物。除此之外，在電晶體區域12中，金屬矽·化物125的重要性是隨著尺寸縮小而增加的。但由於金屬石夕化物125並不需要形成在整個電晶體區域12中，因此需要在形成金属矽化物125之前’先形成自行對準矽化物阻塞18在底材1〇上並覆蓋住電晶體區域12中所有不要形成金屬矽化物125 的區域’如第一Β圖所示’然後才能進口形成金屬矽化物的程序。一般而言，自行對準矽化物阻塞18的材料必需是不會與金屬反應的材料，如四氧乙基矽（ TETRAETHYL-ORTHOSILICATE， TEOS ) » 由前面的討論可以看出，由於反反射層17與自行對準矽化物阻塞18的材料不同，因此僅管二個區域的攙雜區域 101與隔離102是可以一起形成以簡化犁造程序，但接下來的製造程序便需要在二個區域中各自進行，直到金屬矽化物125已形成好後，才可以再合併二個區域的製造程序。無論如何’由第一Β圖可以看出二個區域基本上不能合併的製造程序只有筆因於結構完全不同的閘極121製造程序、金屬矽化物125製造程序以及濾光器16製造程序。因此如何整合反反射層17與自行對準矽化物阻塞18二者的製造451320 V. Description of the invention (3) Therefore, as shown in the first figure B, it is necessary to form an anti-reflection layer 17 on each doped region 101 before forming the dielectric layer 13 to ensure that the light reflected from any doped region will be They will not interfere with each other when they are reflected back. In general, the material of the anti-reflection layer 17 is a nitride, chitin or hechin compound. In addition, in the transistor region 12, the importance of the metal silicide 125 increases as the size decreases. However, since the metal oxide compound 125 does not need to be formed in the entire transistor region 12, it is necessary to 'form a self-aligned silicide block 18 on the substrate 10 and cover the transistor region before forming the metal silicide 125. All regions in 12 that do not form metal silicide 125 are 'shown in the first B figure' before the procedure for forming metal silicide can be imported. Generally speaking, the material for self-aligning silicide block 18 must be a material that does not react with metals, such as TETRAETHYL-ORTHOSILICATE (TEOS) »As can be seen from the previous discussion, the anti-reflective layer 17 Different from the material for self-aligned silicide block 18, only the two regions of the doped region 101 and the isolation 102 can be formed together to simplify the plowing process, but the subsequent manufacturing process needs to be performed in each of the two regions. Until the metal silicide 125 has been formed, the manufacturing process of the two regions can be merged. In any case, from the first B diagram, it can be seen that the manufacturing process of the two regions that cannot be merged basically is only the gate 121 manufacturing process, the metal silicide 125 manufacturing process, and the filter 16 manufacturing process due to completely different structures. So how to integrate the manufacture of the retro-reflective layer 17 and self-aligned silicide block 18

第6頁 451320 五、發明說明（4) 程序，便成為簡化光偵測元件製造程序與降低程本的重要關鍵。 5- 3發明目的及概述：本發明的主要目的在於提供可整合反反射層之製造程序以及自行對準矽化物阻塞之製造程序的方法。Page 6 451320 V. Description of the invention (4) The program has become an important key to simplify the manufacturing process and reduce the cost of the light detection element. 5-3 Objects and Summary of the Invention: The main object of the present invention is to provide a method capable of integrating a manufacturing process of an anti-reflection layer and a manufacturing process of self-aligned silicide blocking.

本發明的另一目的係在於提供一種可以同時形成反反射層以及自行對準矽化物阻塞的方法。本發明的目的尚包含以相同的材料來形成反反射層以及自行對準$夕化物阻塞，使得反反射層與自行對準砍化物阻塞二者可以同時形成。本發明的又一目的是提供可實際應用在生產線上之形成反反射層與自行對準矽化物阻塞的方法。Another object of the present invention is to provide a method capable of simultaneously forming a reflective layer and self-aligning silicide blocking. The object of the present invention also includes forming the anti-reflection layer with the same material and self-aligning the material blocking, so that both the anti-reflection layer and the self-aligning blocking material can be formed at the same time. Another object of the present invention is to provide a method for forming an anti-reflection layer and self-aligned silicide blocking which can be practically applied to a production line.

I: 本發明之再一目的則是提供一種光線偵測元件的形成方法，其中防止不同像素（pixel)間交又干擾現像的反反射層與確定金屬矽化物位置用之自行對準矽化物阻塞係一併形成的’藉以簡化製程與提昇生產效率。I: Another object of the present invention is to provide a method for forming a light detecting element, in which the anti-reflection layer that prevents the intersecting of different pixels from interfering with the image and the self-aligned silicide block for determining the position of the metal silicide are provided. The system is formed to simplify processes and increase production efficiency.

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本發明所提出之較佳實施例至少包含下列步驟：提供至少可分為偵測器區域與電晶體區域的底材，丨中偵測器區域至少包含攙雜區而電晶體區域至少包含由閘極、源極與汲極所形成的電晶體；形成複合層在底材上，此複合層同時覆蓋攙雜區與電晶體，並且可以增大自攙雜區進入複合^之光線的反射率；以微影蝕刻程序移除.部份的複合層，藉以使彳寸閘極的頂部、源極與汲極皆未被複合層所覆蓋 ;以及執行自行對準矽化物程序，形成金屬矽化物在閘極的頂部、源極與沒極之上β 再者’而當此實施例是具體應用在形成光偵測元件時，還進一步包含下列步驟：移除自行對準矽化物程序剩餘的反應物；形成多數多重内連線在這些電晶體與這些隔離的上方’這些多重内連線係位於複合層的上方；以介電層覆蓋底材，並元成覆羞這些攙雜區與這些多重内連線；以及形成多數濾光器在介電層上，其中這些濾光器係位於這些攙雜區的上方。 ' 顯然地，本發明的主要特點是以複合層同時作為彳貞測器區域的反反射層以及電晶體區域的自行對準矽化物阻塞〔，因此在攙雜區域與電晶體都形成好後，可以將谓測器區域與電經體區域的製造程序合併。其中複合層係由多個基層交錯相疊而成’其中相鄰之數個基層的折射率都不同，以改變入射光線的方向，並且形成金屬矽化物用的金屬不 ΙΗΒΊΗΕ" ίΤ頁 451320 五、發明說明（6) 會附著在複合層上。 5-4發明詳細說明：首先’本發明的發明者指出自行對準矽.化物阻塞是用來使形成金屬珍化物用的金屬不會附著在底材上不需要形成金屬矽化物的區域，因此其材料使用介電質即可如四氧乙基矽。相對地，反反射層是用來減少入射到底材之光線的反射強度，因此反反射層材料的選擇條件其對由底材入射光線的反㈣（最好是全反：：： = 發生干擾的可能）。接著’本發明的發明者提出一個解決此問題的切入點 :由於一般用來形成自行對準矽化物阻塞之介電層為具有一定折射率之可透光的材料，因此利用光學上光線自高折射率材料入射到低折射率材料時可能發生全反射的概念，可以合理的推知若將不只一層不同折射率之介電質相疊而形成一複合層，此複合層有可能將特定方向之入射光完全反射回去，亦即可以作為反反射層用。換句話說，本發明的發明者指出藉由將多個介電層相疊成一可具全反射功能之複合層的作法，可以用形成自行對準矽化物阻塞的材料來形成反反射層，藉以同時滿足反反射層改變光線傳播方向與自行對準矽化物阻塞適當隔離金屬與部份底材的需要The preferred embodiment of the present invention includes at least the following steps: providing a substrate that can be divided into at least a detector region and a transistor region, wherein the detector region includes at least a doped region and the transistor region includes at least a gate electrode; The transistor formed by the source, the drain, and the drain; a composite layer is formed on the substrate, and the composite layer covers the doped region and the transistor at the same time, and can increase the reflectance of the light entering the compound from the doped region; The etching process removes part of the composite layer, so that the top, source, and drain of the 彳 -inch gate are not covered by the composite layer; and a self-aligned silicide process is performed to form a metal silicide on the gate. The top, the source and the non-pole β are again, and when this embodiment is specifically applied to form a light detection element, it further includes the following steps: removing the remaining reactants in the self-aligned silicide process; forming a majority Multiple interconnections are above these transistors and these isolations. These multiple interconnections are above the composite layer; the substrate is covered with a dielectric layer, and these doped regions and these multiple interconnections are covered. Line; and a majority filter on the dielectric layer, wherein the filter is positioned above the lines of these doped areas. 'Obviously, the main feature of the present invention is that the composite layer simultaneously serves as the anti-reflection layer in the sensor region and the self-aligned silicide block in the transistor region [, so after the doped region and the transistor are formed, it can be Merge the manufacturing process of the detector area with the electrical warp body area. Among them, the composite layer is formed by staggering a plurality of base layers, wherein the refractive indexes of adjacent base layers are different to change the direction of incident light, and the metal silicide used to form the metal silicide is not 页 Τ 页 451451. DESCRIPTION OF THE INVENTION (6) will adhere to the composite layer. 5-4 Detailed description of the invention: First, the inventor of the present invention pointed out that the silicon is self-aligned. The material blocking is used to prevent the metal used to form the metal precious metal from adhering to the area where the metal silicide is not needed, so The material can be a dielectric such as tetraoxyethyl silicon. In contrast, the anti-reflection layer is used to reduce the reflection intensity of the light incident on the substrate. Therefore, the selection of the material of the anti-reflection layer depends on the reflection of the incident light from the substrate (preferably total reflection :: = = interference occurs). may). Then 'the inventor of the present invention proposes an entry point to solve this problem: Since the dielectric layer generally used to form self-aligned silicide blocks is a light-transmitting material with a certain refractive index, it uses optical light to be high. The concept of total reflection may occur when a refractive index material is incident on a low refractive index material. It can be reasonably reasoned that if more than one layer of dielectric materials with different refractive indices are stacked to form a composite layer, the composite layer may be incident in a specific direction. The light is completely reflected back, that is, it can be used as an anti-reflection layer. In other words, the inventor of the present invention pointed out that by stacking a plurality of dielectric layers into a composite layer having a total reflection function, a self-aligned silicide blocking material can be used to form an anti-reflection layer, thereby At the same time, it meets the needs of the anti-reflective layer to change the direction of light transmission and self-aligned silicide to block the metal and some substrates.

第9頁 4513 20 五、發明說明（7) ，亦即可以整合反反射層製造程序以及自行對準矽化物阻塞製造程序》以下將以本發明之一較佳實施例，一種整合反反射層與自行對準矽化物阻塞的方法，來具體介紹本發明的主要内容，請參造第二A圖到第二D囷所描繪的各基本步驟：如第二A圖所示’提供底材2〇，底材20至少可分為偵測器區域21與電晶體區域22 ’其中债測器區域21至少包含攙雜區23而電晶趙區域22至少包含由閘極241、源極242、波極243與間隙壁244所形成的電晶體。在此偵測器區域η 與電晶體區域22係以隔離201所分開。如第二B圓所示，形成複合層25在底材20上，複合層 25同時也覆蓋住攙雜區23與電晶體。在此複合層25係用以增大自攙雜區23進入複合層25之光線的反射率，亦即是用作為反反射層" 在此複合層25係由多數個基層所交錯相疊而成，其中每一個基層的折射率皆與相鄰的其它基層的折射率不同。由於當光自高折射率材率進入低折射率材料時可能會發生全反射，但光自低折射率材率進入高折射率材料時不可能會發生全反射，因此藉由適當地調整各基層的折射愈度等因素，顯然可以使自攙雜區23進入複合層25的光&被 4513 20 五、發明說明（8) 完全反射（至少大幅降低通過複合層25的機率）^亦即即使形成複合層25的材料是透光的介電質，但複合層25仍可以發揮反反射層的作用。當然，各基層之間折射率與厚度等的關係須視實際的需要來調整，但大致上越靠近攙雜區23 之基層的折射率越高，越遠離攙雜區23之基層的折射率越低。 —般而s ’複合層25的材料至少包含電榮增益四氧乙基矽（plasma enhanced TE0S)以及電漿増益氮化石夕（ plasma enhanced silicon nitride )等可透光的介電質 ’而且為了配合電晶體區域22中自行對準石夕化物阻塞的需要通常係由至少一層的電漿增益四氧乙基矽層與至少一層的電漿增益氮化矽層所交錯相疊而成。在此，電聚增益四氧乙基矽層一般係以電漿增益化學氣相沉積程序所形成的 ’而電漿增益氮化矽層係以電漿增益化學氣相沉積程序所形成的。並且，複合層25的厚度大約為5〇〇埃。如第二C圖所示，以一微影蝕刻程序移除部份的複合層25，藉以使得閘極241的頂部、源極242與沒極243皆未被複合層25所復蓋。其中閘極241頂部的材料為多晶矽。如第二D圖所示，執行一自行對準矽化物程序，藉以形成金屬矽化物26在閘極241的頂部、源極242與汲極243 之上。在此由於複合層25的材料和習知技術令自行對準矽Page 9 4513 20 V. Description of the invention (7), that is, the manufacturing process of the anti-reflection layer and the self-aligned silicide blocking manufacturing process can be integrated. The following will describe a preferred embodiment of the present invention, an integrated anti-reflection layer and The method of self-aligning silicide blocking, to specifically introduce the main content of the present invention, please refer to the basic steps depicted in the second A to the second D 囷: As shown in the second A 'providing the substrate 2. The substrate 20 can be divided into at least a detector region 21 and a transistor region 22 ′, wherein the debt detector region 21 includes at least a doped region 23 and the transistor Zhao region 22 includes at least a gate electrode 241, a source electrode 242, and a wave electrode 243. A transistor formed with the spacer 244. The detector region η is separated from the transistor region 22 by an isolation 201. As shown by the second circle B, a composite layer 25 is formed on the substrate 20, and the composite layer 25 also covers the doped region 23 and the transistor at the same time. Here, the composite layer 25 is used to increase the reflectivity of the light that enters the composite layer 25 from the doped region 23, that is, it is used as a retroreflective layer. Here, the composite layer 25 is formed by staggering and overlapping a plurality of base layers. The refractive index of each base layer is different from the refractive index of other neighboring base layers. Since total reflection may occur when light enters the low-refractive index material from the high-refractive-index material rate, total reflection is unlikely to occur when the light enters the high-refractive-index material from the low-refractive-index material rate. Factors such as the degree of refraction, can obviously make the light from the doped region 23 enter the composite layer 25 & 4513 20 V. Description of the invention (8) Complete reflection (at least greatly reduce the probability of passing through the composite layer 25) ^ That is, even if formed The material of the composite layer 25 is a light-transmitting dielectric, but the composite layer 25 can still function as an anti-reflective layer. Of course, the relationship between the refractive index and the thickness of each base layer must be adjusted according to actual needs, but generally the higher the refractive index of the base layer closer to the doped region 23, the lower the refractive index of the base layer farther from the doped region 23 is. —Generally, the material of the composite layer 25 includes at least light-transmitting dielectrics such as plasma enhanced TEOS and plasma enhanced silicon nitride ', and to match The need for self-alignment of silicon oxide in the transistor region 22 is usually formed by staggering and overlapping at least one plasma gain tetraoxyethyl silicon layer and at least one plasma gain silicon nitride layer. Here, the electro-polymerization gain tetraoxyethyl silicon layer is generally formed by a plasma gain chemical vapor deposition process and the plasma gain silicon nitride layer is formed by a plasma gain chemical vapor deposition process. The thickness of the composite layer 25 is approximately 500 angstroms. As shown in FIG. 2C, a part of the composite layer 25 is removed by a lithographic etching process, so that the top of the gate electrode 241, the source electrode 242, and the non-electrode 243 are not covered by the composite layer 25. The material on the top of the gate electrode 241 is polycrystalline silicon. As shown in FIG. 2D, a self-aligned silicide process is performed to form a metal silicide 26 on top of the gate electrode 241, the source electrode 242, and the drain electrode 243. Self-alignment of silicon due to the material and know-how of the composite layer 25

4 51 3 20 五、發明說明（9) 化物阻塞的材料相當，因此以複合層25作為自行對準矽化物阻塞並不會有任何的不良副作用。顯然地，在此實施例中複合層25除了在形成金屬矽化物26於電晶體區域22的過程中，發揮了自行對準矽化物阻塞的功能外；被形成在攙雜區域23上的複合層25，也可以發揮反反射層的功能。換言之，本發明是.一種成功地整合了反反射層之製造程序以及自行對準矽化物阻塞之製造程序的方法。特別是由於形成複合層25的過程只是連續形成不只一層的介電質層而已，因此這個方法還是一種可實際地應用在生產線上的方法。再者’當此實施例被實際應用在提供一種形成光線偵測元件的方法時，還至少包含下列數個基本步驟：如第二E圖所示，移除自行對準矽化物程序剩餘的反應物’並形成第一介電層27覆蓋複合層25與金屬矽化物26 之上。如第二F圖所示，先形成多數個多重内連線28在第一介電層27上’再以第二介電層29覆蓋在第一介電層27與多重内連線28之上《^這些多重内連線28係位於電晶體與隔離 201的上方並且通常係連接到電晶體，當然也可以耦合到攙雜區23。4 51 3 20 V. Description of the invention (9) The material blocked by the compound is equivalent, so using the composite layer 25 as a self-aligned silicide block does not have any adverse side effects. Obviously, in this embodiment, in addition to the function of self-aligned silicide blocking formed in the process of forming the metal silicide 26 on the transistor region 22, the composite layer 25 is formed on the doped region 23 , Can also play the role of anti-reflective layer. In other words, the present invention is a method for successfully integrating the manufacturing process of the retroreflective layer and the manufacturing process of self-aligned silicide blocking. In particular, since the process of forming the composite layer 25 only continuously forms more than one dielectric layer, this method is also a method that can be practically applied to a production line. Furthermore, when this embodiment is actually applied to provide a method for forming a light detecting element, it further includes at least the following basic steps: As shown in the second figure E, the remaining reaction of the self-aligned silicide process is removed. And a first dielectric layer 27 is formed to cover the composite layer 25 and the metal silicide 26. As shown in FIG. 2F, a plurality of multiple interconnects 28 are formed on the first dielectric layer 27 ', and then the second dielectric layer 29 is covered on the first dielectric layer 27 and the multiple interconnects 28. These multiple interconnects 28 are located above the transistor and isolation 201 and are usually connected to the transistor. Of course, they can also be coupled to the doped region 23.

第12頁 4 51 3 2 0 五、發明說明（ίο)Page 12 4 51 3 2 0 V. Description of the Invention (ίο)

如第二G圓所示，形成多數個濾光器（color filter) 295在第二介電層29上，這些濾光器295係位於攙雜區23的上方》其中濾光器295的可能種類至少包含紅光線濾光器、藍光線濾光器以及綠光線濾光器，並且一般來說，每一個攙雜區23的上方皆有一個濾光器295。As shown by the second circle G, a plurality of color filters 295 are formed on the second dielectric layer 29. These filters 295 are located above the doped region 23. The possible types of the filters 295 are at least It includes a red light filter, a blue light filter, and a green light filter. Generally, there is a filter 295 above each doped region 23.

附帶地，隨者半導體元件結構的日漸複雜，底材20更包含多數個電阻器（resistor)(未顯示於各圖示），這些電阻器係耦合到該些電晶體，以及被複合層25所完全覆蓋，並且係用以提供完整電路所需要的電阻。一般而言，電阻器為位於隔離2 0 1上的多晶矽結構，並且通常這些多晶矽結構係與各電晶體之閘極2 41頂部的多晶矽部份一起形成的。藉由比較第二G圖與第一B圖，可以看出由於在此方法中複合層25可以有效地扮演反反射層的角色，因此^透光之多重内連線2 8y使任何一個攙雜區23接收到自其它攙雜區 23反射之光線的機率可以降至最低。換句話說，本發明可以有效地防治交叉干擾現像’因此是一個適用於光偵測元件製程的方法。、以上所述僅為本發明之較佳實施例而已，並非用以限定本發明之申請專利範圍；凡其它未脫離本發明所揭示之Incidentally, the structure of the accompanying semiconductor device is becoming more and more complicated. The substrate 20 further includes a plurality of resistors (not shown in each figure). These resistors are coupled to the transistors and are covered by the composite layer 25. Completely covered and used to provide the required resistance for the complete circuit. Generally speaking, the resistor is a polycrystalline silicon structure on the isolation 201, and usually these polycrystalline silicon structures are formed together with the polycrystalline silicon portion on top of the gate 241 of each transistor. By comparing the second G diagram with the first B diagram, it can be seen that since the composite layer 25 can effectively play the role of a reflective layer in this method, the light-transmitting multiple interconnects 2 8y make any one doped area The probability that 23 will receive light reflected from other doped areas 23 can be minimized. In other words, the present invention can effectively prevent the phenomenon of cross-interference 'and is therefore a method suitable for the process of photodetection elements. The above descriptions are merely preferred embodiments of the present invention, and are not intended to limit the scope of patent application for the present invention; all others that do not depart from the disclosure of the present invention

V is 頁 J 451320 五、發明說明（π) 精神下所完成之等效改變或修飾，均應包含在下述之申請專利範圍内。V is page J 451320 5. The equivalent changes or modifications made under the spirit of the invention description (π) shall all be included in the scope of the patent application described below.

第14頁 ! 451320 圈式簡單說明第一A圖至第一B圊是用以解釋反反射層與自行對準矽化物阻塞二者之位置與作用的示意圖；以及第二A圖到第二G圖為一系列用以解釋本發明之一較佳實施例各基本步驟的橫截面示意圖。主要部分之代表符號： 10 底材 101 攙雜區 102 隔離 11 偵測器區域 12 電晶體區域 121 閘極 122 源極 123 汲極 124 間隙壁 125 金屬矽化物 13 介電層 14 多重内連線 15 覆蓋層 16 濾光器 20 底材 201 隔離 21 偵測器區域 1^«1 第15頁 451320 圖式簡單說明 22 電晶體區域 23 攙雜區 241 閘極 242 源極 243 汲極 244 間隙壁 25 複合層 26 金屬矽化物 27 第一介電層 28 多重内連線 29 第二介電層 295 滤光器Page 14! 451320 The circle diagrams A to B are simple diagrams explaining the positions and functions of the anti-reflective layer and self-aligned silicide block; and the second A to second G The figure is a series of schematic cross-sectional views for explaining the basic steps of a preferred embodiment of the present invention. Representative symbols of the main parts: 10 substrate 101 doped region 102 isolation 11 detector region 12 transistor region 121 gate 122 source 123 drain 124 gap wall 125 metal silicide 13 dielectric layer 14 multiple interconnects 15 overlay Layer 16 Filter 20 Substrate 201 Isolation 21 Detector area 1 ^ «1 Page 15 451320 Brief description of the diagram 22 Transistor area 23 Doped area 241 Gate 242 Source 243 Drain 244 Spacer wall 25 Composite layer 26 Metal silicide 27 First dielectric layer 28 Multiple interconnects 29 Second dielectric layer 295 Filter

第16頁Page 16

Claims

89110938 年月曰修正 1. 一種整合反反射層與自行對準矽化物阻塞的方法，至少包含：提晶體區體區域晶體，形區與該該複合以閘極的及執在該閘供一底材，該底材域，其中該偵測器至少包含由一閉極成一複合層在該底電晶體，在此該複層之光線的反射率一微影蝕刻程序移頂部、該源極與該行一自行對準矽化極的頂部、該源極至少可分為一偵測器區域與一電區域至少包含一攙雜區而該電晶、一源極與一没極所形成的一電材上，該複合層同時覆蓋該攙雜合層係用以增大自該攙雜區進入 t 除部份的該複合層，藉以使得該汲極皆未被該複合層所覆蓋；以物程序，藉以形成一金屬石夕化物與該汲極之上。 2. 如申請專利範圍第1項之方法，其中上述之偵測器區域與該電晶體區域係以一隔離所分開。 3. 如申請專利範圍第1項之方法，其中上述之閘極頂部的材料為多晶梦。 4. 如申請專利範圍第1項之方法，其中上述之複合層係由多數個基層所交錯相疊而成。89110938 Revised 1. A method for integrating anti-reflective layer and self-aligned silicide blocking, including at least: lifting the crystal of the crystal region body region, the shape region and the compound are gated and held on the gate for a bottom Material, the substrate field, wherein the detector includes at least a closed electrode into a composite layer on the bottom transistor, where the reflectivity of the light of the multiple layer is moved by a lithographic etching process to the top, the source and the A line is aligned on top of the silicide electrode, the source can be divided into at least a detector region and an electrical region including at least a doped region, and the transistor, a source and an electrode are formed on an electrical material. The composite layer simultaneously covers the dopant hybrid layer is used to increase the compound layer from the dopant region into the t-divided part, so that the drain electrode is not covered by the compound layer; a physical process is used to form a metal Shi Xihua and the drain. 2. The method according to item 1 of the patent application range, wherein the above-mentioned detector region and the transistor region are separated by an isolation. 3. The method according to item 1 of the patent application scope, wherein the material on the top of the gate is polycrystalline dream. 4. The method according to item 1 of the scope of patent application, wherein the above-mentioned composite layer is formed by staggering and overlapping of a plurality of base layers.

第17頁 451320 _案號89110938_年月日_魅_ ' 六、申請專利範圍 5. 如申請專利範圍第4項之方法，其中每一個該基層的折射率皆與相鄰的其它該些基層的折射率不同。 6. 如申請專利範圍第4項之方法，其中越靠近該攙雜區之該基層的折射率越高，越遠離該攙雜區之該基層的折射率越低。 7. 如申請專利範圍第1項之方法，其中上述之複合層的材料至少包含電漿增益四氧乙基矽以及電漿增益氮化矽。 8 .如申請專利範圍第1項之方法，其中上述之複合層係由至少一層的電漿增益四氧乙基矽層與至少一層的電漿增益氮化石夕層所交錯相疊而成。 9.如申請專利範圍第8項之方法，其中上述之電漿增益四氧乙基矽層係以電漿增益化學氣相沉積程序所形成的。 1 0 .如申請專利範圍第8項之方法，其中上述之電漿增益氮化矽層係以電漿增益化學氣相沉積程序所形成的。 11.如申請專利範圍第1項之方法，其中上述之複合層的厚度大約為5 00埃。Page 17 451320 _Case No. 89110938_Year Month_Charm_ '' VI. Application for Patent Range 5. For the method of applying for the fourth item of the patent scope, where the refractive index of each base layer is adjacent to the other other base layers The refractive index is different. 6. The method according to item 4 of the patent application scope, wherein the refractive index of the base layer closer to the doped region is higher, and the refractive index of the base layer farther from the doped region is lower. 7. The method according to item 1 of the scope of patent application, wherein the material of the composite layer mentioned above includes at least plasma gain tetraoxyethyl silicon and plasma gain silicon nitride. 8. The method according to item 1 of the patent application range, wherein the composite layer is formed by staggering at least one plasma gain tetraoxoethylsilicon layer and at least one plasma gain nitride nitride layer. 9. The method according to item 8 of the scope of patent application, wherein the above-mentioned plasma gain tetraoxyethyl silicon layer is formed by a plasma gain chemical vapor deposition process. 10. The method according to item 8 of the scope of patent application, wherein the plasma gain silicon nitride layer is formed by a plasma gain chemical vapor deposition process. 11. The method according to item 1 of the patent application range, wherein the thickness of the above-mentioned composite layer is about 500 angstroms.

451320 _案號89110938_年月曰修正__ 六、申請專利範圍 1 2. —種形成光線偵測元件的方法，至少包含：提供一底材，該底材至少包含多數個攙雜區、多數個電晶體與多數個隔離；形成一複合層在底上並覆蓋所有的該些攙雜區、該些電晶體與該些隔離，在此該複合層係用以增大自該底材進入該複合層之光線的反射率；執行一微影蝕刻程序，藉以定義隨後要形成一金屬矽化物之一區域並移除位於該區域之部份的該複合層，其中該區域至少包含多數個閘極的頂部、多數個源極與多數個汲極；執行一自行對準矽化物程序，藉以形成一金屬矽化物在該些閘極頂部、該些源極與該些汲極之上；移除該自行對準矽化物程序剩餘的反應物；形成一第一介電層在該複合層與該金屬*5夕化物上，形成多數個多重内連線該第一介電層上，該些多重内連線係為於在該些電晶體與該些隔離的上方；以一第二介電層覆蓋該第一介電層與該些多重内連線；以及形成多數個濾光器在該第二介電層上，該些濾光器係位於該些攙雜區的上方。 1 3.如申請專利範圍第1 2項之方法，其中上述之底材更包含多數個電阻器。451320 _Case No. 89110938_ Amendment __ VI. Application for Patent Scope 1 2. A method for forming a light detection element, including at least: Providing a substrate, the substrate including at least a plurality of impurity regions, a plurality of The transistor is isolated from the plurality; a composite layer is formed on the bottom and covers all the doped regions, the transistors are isolated from the plurality, and the composite layer is used to increase the penetration of the substrate from the substrate into the composite layer. Reflectance of light; performing a lithographic etching process to define a region where a metal silicide is to be formed subsequently and removing the composite layer in a portion of the region, wherein the region contains at least the tops of a plurality of gates A plurality of sources and a plurality of drains; perform a self-aligned silicide process to form a metal silicide on top of the gates, the sources and the drains; remove the self-pairing Residues remaining in the quasi-silicide process; forming a first dielectric layer on the composite layer and the metal oxide, forming a plurality of multiple interconnects on the first dielectric layer, the multiple interconnects Department is Over the transistors and the isolation; covering the first dielectric layer and the multiple interconnects with a second dielectric layer; and forming a plurality of filters on the second dielectric layer, The filters are located above the doped regions. 1 3. The method according to item 12 of the scope of patent application, wherein the above-mentioned substrate further includes a plurality of resistors.

第19頁 4 5 1 S ρ η 4 d I o乙u案號8911〇938_年月曰修正__ 六、申請專利範圍 1 4 .如申請專利範圍第1 3項之方法，其中上述之電阻器為位於該些隔離上的多晶矽結構。 1 5 .如申請專利範圍第1 4項之方法，其中上述之該些多晶矽結構係與該些電晶體之閘極頂部的多晶矽部份一起形成的。 1 6 .如申請專利範圍第1 2項之方法，其中上述之多數個電阻器係耦合到該些電晶體。 1 7.如申請專利範圍第1 2項之方法，其中上述之複合層也完全覆蓋該些電阻器。 1 8.如申請專利範圍第1 2項之方法，其中上述之複合層係由多數個基層所交錯相疊而成。 1 9.如申請專利範圍第1 8項之方法，其中每一個該基層的折射率皆與相鄰的其它該些基層的折射率不同》 2 0 .如申請專利範圍第1 8項之方法，其中越靠近該底材之該基層的折射率越高，越遠離該底材之該基層的折射率越低0P.19 4 5 1 S ρ η 4 d I o Case No. 8911〇938 _ month and year __ VI. Application for patent scope 1 4. For the method of the patent scope No. 13 application, the above-mentioned resistance The device is a polycrystalline silicon structure on the isolations. 15. The method according to item 14 of the scope of patent application, wherein the polycrystalline silicon structures described above are formed together with the polycrystalline silicon portion on top of the gates of the transistors. 16. The method of claim 12 in the scope of patent application, wherein the plurality of resistors described above are coupled to the transistors. 17. The method according to item 12 of the scope of patent application, wherein the above-mentioned composite layer also completely covers the resistors. 18. The method according to item 12 of the scope of patent application, wherein the above-mentioned composite layer is formed by staggering and overlapping of a plurality of base layers. 19. The method according to item 18 of the scope of patent application, wherein the refractive index of each of the base layers is different from the refractive index of other adjacent base layers "2 0. If the method of item 18 of the patent scope, Wherein the refractive index of the base layer closer to the substrate is higher, and the refractive index of the base layer farther from the substrate is lower.

第20頁 451320 _案號 89110938_年月日__— 六、申請專利範圍 2 1.如申請專利範圍第1 2項之方法，其中上述之複合層的材料至少包含電漿增益四氧乙基矽和電漿增益氮化矽。 2 2 .如申請專利範圍第1 2項之方法，其中上述之複合層係由至少一層的電楽·增益四氧乙基石夕層與至少一層的電腹增益氮化石夕層所交錯相疊而成。 2 3.如申請專利範圍第2 2項之方法，其中上述之電漿增益四氧乙基矽層係以電漿增益化學氣相沉積程序形成的。 24. 如申請專利範圍第2 2項之方法，其中上述之電漿增益氮化矽層係以電漿增益化學氣相沉積程序形成的。 25. 如申請專利範圍第12項之方法，其中上述之複合層的厚度大約為5 0 0埃。 26. 如申請專利範圍第12項之方法，其中上述之多數個多重内連線連接到該些電晶體。 27. 如申請專利範圍第12項之方法，其中上述之多數個多重内連線係耦合到該些攙雜區" 2 8.如申請專利範圍第1 2項之方法，其中上述之濾光器的可能種類至少包含紅光線濾光器、藍光線濾光器以及綠光Page 20 451320 _Case No. 89110938_Year_Month__ Sixth, the scope of patent application 2 1. The method according to item 12 of the scope of patent application, wherein the material of the above composite layer contains at least plasma gain tetraoxoethyl Silicon and plasma gain silicon nitride. 2 2. The method according to item 12 of the scope of patent application, wherein the above composite layer is alternately overlapped by at least one layer of galvanic acid · gaintetraoxyethyl stone layer and at least one layer of galvanic gain nitride layer. to make. 2 3. The method according to item 22 of the scope of patent application, wherein the above-mentioned plasma gain tetraoxyethyl silicon layer is formed by a plasma gain chemical vapor deposition process. 24. The method according to item 22 of the scope of patent application, wherein the above-mentioned plasma gain silicon nitride layer is formed by a plasma gain chemical vapor deposition process. 25. The method of claim 12 in which the thickness of the above-mentioned composite layer is about 500 angstroms. 26. The method of claim 12 in which the plurality of multiple interconnects described above are connected to the transistors. 27. The method according to item 12 of the patent application, wherein the plurality of multiple interconnects described above are coupled to the impurity regions " 2 8. The method according to item 12 of the patent application, wherein the above-mentioned filter Possible types include at least a red light filter, a blue light filter, and a green light

第21頁 451320 _案號89Π0938_年月曰修正__ 六、申請專利範圍線濾光器。 2 9.如申請專利範圍第1 2項之方法，其中每一個該攙雜區的上方皆有一個該遽光器。Page 21 451320 _Case No. 89Π0938_ Year Month Amendment __ VI. Patent Application Line Filter. 2 9. The method according to item 12 of the scope of patent application, wherein each of said doped regions has a said luminescent device.

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