JPS6074681A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6074681A JPS6074681A JP18270883A JP18270883A JPS6074681A JP S6074681 A JPS6074681 A JP S6074681A JP 18270883 A JP18270883 A JP 18270883A JP 18270883 A JP18270883 A JP 18270883A JP S6074681 A JPS6074681 A JP S6074681A
- Authority
- JP
- Japan
- Prior art keywords
- oxide film
- film
- entire surface
- electrode
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 239000004065 semiconductor Substances 0.000 title claims description 14
- 238000000034 method Methods 0.000 claims abstract description 32
- 150000004767 nitrides Chemical class 0.000 claims abstract description 27
- 239000012535 impurity Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 17
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 8
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 8
- 239000001301 oxygen Substances 0.000 claims abstract description 8
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000000151 deposition Methods 0.000 claims description 7
- 238000010438 heat treatment Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 abstract description 5
- 238000007254 oxidation reaction Methods 0.000 abstract description 5
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 230000005684 electric field Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 238000000206 photolithography Methods 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 241000168254 Siro Species 0.000 description 1
- NINIDFKCEFEMDL-UHFFFAOYSA-N Sulfur Chemical compound [S] NINIDFKCEFEMDL-UHFFFAOYSA-N 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- LDDQLRUQCUTJBB-UHFFFAOYSA-N ammonium fluoride Chemical compound [NH4+].[F-] LDDQLRUQCUTJBB-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052717 sulfur Inorganic materials 0.000 description 1
- 239000011593 sulfur Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特にソース、ド
レイン領域に低濃度不純物領域を有するＭＯ８半導体装
置の製造方法に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing an MO8 semiconductor device having low concentration impurity regions in source and drain regions.
従来のＭＯＳ ）ランジスタの製造方法を第１図を参照
して説明する。すなわち、Ｐ−型シリコン基板１上にノ
々ターニングによりダート酸化膜２を介してダート電極
３を形成した後、ダート電極３をマスクとして例えば八
８を高ドーズイオン注入し、つづいて熱処理を行なうこ
とによりＮ十型ソース領域４及びＮ＋型ドレイン領域５
を形成する。A method of manufacturing a conventional MOS transistor will be explained with reference to FIG. That is, after a dirt electrode 3 is formed on a P-type silicon substrate 1 through a dirt oxide film 2 by continuous turning, high-dose ions of, for example, 88 are implanted using the dirt electrode 3 as a mask, and then heat treatment is performed. Possibly an N+ type source region 4 and an N+ type drain region 5.
form.
このようにして形成されるＮ＋型ドレイン領域５は高濃
度の拡散層であるため、その近傍には電界が集中し、正
孔と電子の対が生成する。この結果、基板電位が上昇し
てバイポーラアクションをもたらしたシ、ホットエレク
トロンがダート酸化膜２中に注入をれてｖｔｈ異常を起
こす等トランジスタの不安定性が増大する。更に、高集
積ＭＯＳデバイスにおいてはチャネル長が短かくな９、
前記電界集中によシ空乏層が拡がシショートチャネル効
果が無視できなく々る。Since the N+ type drain region 5 formed in this manner is a highly doped diffusion layer, an electric field is concentrated in the vicinity thereof, and pairs of holes and electrons are generated. As a result, the substrate potential rises, resulting in bipolar action, and hot electrons are injected into the dirt oxide film 2, causing an abnormality in Vth and increasing the instability of the transistor. Furthermore, in highly integrated MOS devices, the channel length is short9,
The electric field concentration causes the depletion layer to expand, and the short channel effect cannot be ignored.
そこで、ドレイン領域をチャネル領域近傍の低濃度不純
物領域とこれに隣接する高濃度不純物領域とで構成し、
電界集中を抑制したいわゆるＬＤＤ （Ｌｉｇｈｔｌｙ
Ｄｏｐｅｄ Ｄｒａｉｎ ）構造のＭＯＳトランジス
タが提案されている。Therefore, the drain region is composed of a low concentration impurity region near the channel region and a high concentration impurity region adjacent to this,
The so-called LDD (Lightly
A MOS transistor with a doped drain structure has been proposed.
このＬＤＤ構造のＭＯＳ ）ランジスタは例えば第２′
図（、）〜（ｃ）に示す如き方法によシ製造される。For example, the MOS) transistor of this LDD structure is
It is manufactured by the method shown in Figures (,) to (c).
まず、Ｐ−型シリコン基板ｌＪ上にパターニングにより
ケ゛−ト酸化膜１２を介してケ゛−ト電極１３を形成し
た後、ダート電極１３をマスクとして例えはＡｓを低ド
ーズ量でイオン注入する（第２図（ａ）図示）。次に、
ダート電極１３を傑うようにホトレジスト・母ターン１
４を形成した後、ホトレジストノリ−ン１４をマスクと
してＡｓを高ドーズ量でイオン注入する（同図（ｂ）図
示〕。First, a gate electrode 13 is formed on a P-type silicon substrate lJ by patterning via a gate oxide film 12, and then, using the dirt electrode 13 as a mask, ions of, for example, As are implanted at a low dose (first step). Figure 2 (a) shown). next,
Photoresist/mother turn 1 to highlight dirt electrode 13
4, using the photoresist layer 14 as a mask, As is ion-implanted at a high dose (as shown in FIG. 4B).
つづいて、ホトレノストパターン１４を除去した後、熱
処理を行ない、チャネル領域近傍の低濃度（Ｎ−型）不
純物領域１５ａ、１５ｇとこれらに隣接する高濃度（Ｎ
＋型）不純物領域１５ｂ。Subsequently, after removing the photorenost pattern 14, heat treatment is performed to form low concentration (N-type) impurity regions 15a and 15g near the channel region and high concentration (N-type) impurity regions 15a and 15g adjacent to these.
+ type) impurity region 15b.
１６ｂとからなるソース、ドレイン領域１５゜１６を形
成する（同図（ｃ）図示）。Source and drain regions 15° and 16 made of 16b are formed (as shown in FIG.
しかしながら、上述した従来の方法では通常のＭＯＳ
ｆロセスに比べて不純物ドーピング工程及びホトリソグ
ラフィ工程がそれぞれ１回づつ加わることになり工程が
煩雑化するという一点がある。However, in the conventional method described above, the normal MOS
Compared to the f-process, one impurity doping step and one photolithography step are added, making the process more complicated.
９Ｎ明の目的〕
本発明は上記欠点を解消するためになされたものであシ
、簡便な工程で少なくともドレイン領域のチャネル領域
近傍の部分が低濃度不純物領域で構成されたＭＯ８半導
体装置を製造し得る方法を提供しようとするものである
。9N Ming's Purpose] The present invention has been made in order to eliminate the above-mentioned drawbacks, and is to manufacture an MO8 semiconductor device in which at least a portion of the drain region near the channel region is composed of a low concentration impurity region using a simple process. We are trying to provide a way to obtain it.
本発明の半導体装置の製造方法は第１導電型（例えばＰ
型）の半導体基板の素子領域上にダート絶縁膜を介して
ダート電極を形成し、全面に第２導篭型の不純物をドー
プした酸化膜（例えばＡｓ ドーゾト酸化膜）を堆積し
た後、該酸化膜上に部分的に（例えばダート電極側壁の
酸化膜除去後のダート電極側壁の位置あるいはダート電
極の両側方のうちいずれか一方側に）窒化膜を残存させ
、更に酸素雰囲気中で熱処理して酸化膜から基板中に不
純物を拡散させて第２導電型のソース、ドレイン領域を
形成することを特徴とするものである。The method for manufacturing a semiconductor device according to the present invention includes a method for manufacturing a semiconductor device of a first conductivity type (for example, P
A dirt electrode is formed on the element region of the semiconductor substrate (type) via a dirt insulating film, and an oxide film doped with a second conductive cage type impurity (for example, an As doped oxide film) is deposited on the entire surface, and then the oxide film is A nitride film is left partially on the film (for example, at the position of the dirt electrode side wall after the oxide film on the dart electrode side wall has been removed, or on either side of the dirt electrode), and is further heat-treated in an oxygen atmosphere. This method is characterized in that source and drain regions of the second conductivity type are formed by diffusing impurities from the oxide film into the substrate.
こうした方法によれば、ＡＩは酸素雰囲気中で５−
の熱処理の際、窒化膜の残存している箇所ではあまり拡
散しないが、窒化膜の残存していない箇所では酸化膜一
基板界面での新たな酸化膜の生成により効率よく拡散す
るので、セル７アラインでドレイン領域のチャネル領域
近傍の部分を低濃度不純物領域とすることができる。し
たがって、通常のＭＯ８プロセスに比べて少なくともイ
オン注入工程を省略した簡便な工程で、ドレイン領域近
傍のチャネル領域での電界集中を抑制してトランジスタ
の不安定性を減少することができる。According to this method, during heat treatment in an oxygen atmosphere, AI does not diffuse much in areas where the nitride film remains, but in areas where the nitride film does not remain, new AI diffuses at the oxide film-substrate interface. Since the formation of an oxide film allows efficient diffusion, the portion of the drain region near the channel region can be made into a low concentration impurity region by cell 7 alignment. Therefore, compared to the normal MO8 process, it is possible to suppress electric field concentration in the channel region near the drain region and reduce instability of the transistor with a simpler process that omits at least the ion implantation step.
以下、本発明の実施例を第３図（ａ）〜（ｆ）及び第４
図（ａ）〜（Ｃ） を参照して説明する。Examples of the present invention will be described below in Figures 3(a) to (f) and 4.
This will be explained with reference to Figures (a) to (C).
実施例１
まず、比抵抗１０〜２０Ω−鋸のＰ−型シリコン基板２
１表面に通常の選択酸化技術を用い、厚さ１．０μｍの
フィールド酸化膜２２を形成する。Example 1 First, a P-type silicon substrate 2 with a specific resistance of 10 to 20Ω-saw
A field oxide film 22 with a thickness of 1.0 μm is formed on one surface using a conventional selective oxidation technique.
次に、フィールド酸化膜２２によって囲まれた素子領域
表面に厚さ５００Ｘの熱酸化膜を形成６−
し、全面にρ８＝２００／口、厚さ０．４μｍの多結晶
シリコン膜を堆積した後、これらを反応性イオンエツチ
ング（ＲＩＥ ）法により順次・ぐターニングして素子
領域上にダート酸化膜２３を介してダート電極２４を形
成する（第３図（、）図示）。Next, a thermal oxide film with a thickness of 500× is formed on the surface of the element region surrounded by the field oxide film 22, and a polycrystalline silicon film with a thickness of 0.4 μm and ρ8=200/gate is deposited on the entire surface. These are sequentially turned by reactive ion etching (RIE) to form a dirt electrode 24 on the element region via a dirt oxide film 23 (as shown in FIG. 3).
次いで、スノヤッタ法にて全面に厚さ０．２５μｍのＡ
８ドーゾト酸化膜（Ａｓ濃度５ Ｘ １０” ｏｎ−’
）２５を堆積する。この際、ｒ−上電極２４の側壁に
おいてはＡｓドープト酸化膜２５の膜厚は約５００Ｘと
薄くなる（同図（ｂ）図示）。つづいて、ＮＨ４Ｆ’中
に１０秒間浸し、前記Ａａドープト酸化膜２５のケ゛−
ト電極２４側壁の薄い部分のみをエツチング除去する。Next, A with a thickness of 0.25 μm was applied to the entire surface using the Sunoyatta method.
8 dosed oxide film (As concentration 5 x 10"on-'
)25 is deposited. At this time, the thickness of the As-doped oxide film 25 on the side wall of the r- upper electrode 24 becomes as thin as about 500X (as shown in FIG. 2B). Subsequently, the Aa doped oxide film 25 is immersed in NH4F' for 10 seconds.
Only the thin portion of the side wall of the top electrode 24 is removed by etching.
この際、平坦面上には厚さ０．２μｍのＡｓドープト酸
化膜２５がそのまま残存する。つづいて、ＬＰＣＶＤ法
にて全面に厚さ０．２μｍの窒化膜２６を堆積する（同
図（ｃ）図示）。At this time, the As-doped oxide film 25 with a thickness of 0.2 μm remains as it is on the flat surface. Subsequently, a nitride film 26 with a thickness of 0.2 μm is deposited on the entire surface by the LPCVD method (as shown in FIG. 3(c)).
次いで、ＲＩＥ法により前記窒化膜２６をエツチングし
、ダート電極２４の側壁にのみ残存窒化膜２６’ 、
２６’ ｆ形成する。つづいて、酸素雰囲気中にて１０
００℃で３０分間熱拡散を行なう。Next, the nitride film 26 is etched by the RIE method, leaving a nitride film 26' remaining only on the side wall of the dirt electrode 24.
26' f is formed. Subsequently, in an oxygen atmosphere,
Heat diffusion is carried out at 00°C for 30 minutes.
この際、残存窒化膜２６’ 、 ２６’に覆われていな
い部分ではＡｓドープト酸化膜２５と基板２ノとの界面
に新たに酸化膜が形成されることにより、ＡｓがＡｓド
ープト酸化膜２５から基板２ノ中に効率よく拡散される
が残存窒化膜２６’ 、 ２６’に榎われている部分で
はＡｓはそれほど拡散されない。At this time, a new oxide film is formed at the interface between the As-doped oxide film 25 and the substrate 2 in the portions not covered by the remaining nitride films 26' and 26', so that As is removed from the As-doped oxide film 25. As is efficiently diffused into the substrate 2, but not so much in the portions covered by the remaining nitride films 26', 26'.
この結果、チャネル領域近傍のρ、＝７００シロ、ｘｊ
＝ ０．２ μｍのＮ″″型不純物領域２７ｍ 、２
８＊とこれらの領域に隣接するρ＝３００／口、ｘＪ＝
０．４μｍのＮ＋型不純物領域２１ｂ、２８ｂとからな
るソース、ドレイン領域２７．２８が形成される（同図
（ｄ）図示）。As a result, ρ near the channel region = 700 siro, xj
= 0.2 μm N″″ type impurity region 27m, 2
8* and ρ = 300/mouth adjacent to these regions, xJ =
Source and drain regions 27 and 28 consisting of N+ type impurity regions 21b and 28b with a thickness of 0.4 μm are formed (as shown in FIG. 4D).
次いで、前記残存嘘化膜２６’ 、 ２６’及びＡｓド
ドート酸化膜２５ｔｌ−ＲＴＥ法あるいはウェットエツ
チングにより順次エツチング除去した後、熱酸化により
ケ゛−ト電極２４表面及び露出した基板２１表面を厚さ
５００Ｘの熱酸化膜２９に変換する（同図（、）図示）
。つづいて、全面に厚さ０．５μｍのＣＶＤ酸化膜３０
を堆積した後、コンタクトホール３１，３１を開孔する
。つづいて、隼夕面に厚さ１．０μｍのＡｔ−８１膜を
堆積した後、パターニングしてソース電極３２及びドレ
イン電極３３を形成し、ＬＤＤ構造のＭＯＳトランジス
タを製造する（同図（ｆ）図示）。Next, the remaining deforming films 26', 26' and the As dot oxide film 25tl-RTE or wet etching are sequentially etched away, and then the surface of the gate electrode 24 and the exposed surface of the substrate 21 are etched to a thickness of 500× by thermal oxidation. into a thermal oxide film 29 (shown in (,) in the same figure).
. Next, a CVD oxide film 30 with a thickness of 0.5 μm is placed on the entire surface.
After depositing, contact holes 31, 31 are opened. Subsequently, after depositing an At-81 film with a thickness of 1.0 μm on the Hayabusa surface, it is patterned to form a source electrode 32 and a drain electrode 33, thereby manufacturing an LDD structure MOS transistor (FIG. 3(f)). (Illustrated).
しかして上述した方法によれば、第３図（ｂ）の工程で
ス・母ツタ法により全面にＡｓドープト酸化膜２５を堆
積した後、同図（ｃ）の工程でＡｓドープト酸化膜２５
のゲート電極２４側壁の薄い部分のみをエツチング除去
し、更に全面に窒化膜２６を堆積し、次いで同図（ｄ）
の工程で反応性イオンエツチング法によＦ）ｌ’−）電
極２４側壁に残存窒化膜２６’ 、 ２６’を形成した
後、酸素雰囲気中で熱処理することによｆｉＮ″″型不
純物領域２７＊、２８ｍ１Ｎ＋型不純物領域２７ ｂ、
２８ｂとからなるソース、ドレイン領域２７．２８を形
成することができる。すなわち、通常のＭＯＳプロセス
にホトリソグラフィ工程及びイオン注入工程を追加する
ことなく、セルファラインでＬＤＤ構造を形成すること
ができる。したがって、簡便な工程でドレイン領域２８
近傍のチャネル９−
１脩４における電界集中を抑制して、バイポーラアクシ
ョンやｖｔｈの変動を防止することによりトランジスタ
の不安定性を減少することができ、素子の微細化を達成
することができる。According to the method described above, after the As-doped oxide film 25 is deposited on the entire surface by the sulfur ivy method in the step of FIG. 3(b), the As-doped oxide film 25 is deposited in the step of FIG. 3(c).
Only the thin part of the side wall of the gate electrode 24 is removed by etching, and then a nitride film 26 is deposited on the entire surface, and then, as shown in FIG.
After forming the residual nitride films 26', 26' on the side walls of the F)l'-) electrode 24 by reactive ion etching in the step of step 1, the fiN"" type impurity region 27* is formed by heat treatment in an oxygen atmosphere. , 28m1N+ type impurity region 27b,
Source and drain regions 27 and 28 can be formed. That is, the LDD structure can be formed using self-alignment without adding a photolithography process and an ion implantation process to a normal MOS process. Therefore, the drain region 28 can be formed in a simple process.
By suppressing electric field concentration in the neighboring channels 9-1 and 4 and preventing bipolar action and vth fluctuations, instability of the transistor can be reduced and device miniaturization can be achieved.
実施例２
まず、Ｐ−型シリコン基板５１表面にフィールド酸化膜
５２を形成した後、フィールド酸化膜５２に囲まれた素
子領域上にダート酸化膜５３を介してダート電極５４を
形成する。次に、全面にＡｓドープト酸化膜５５を堆積
し、更に全面に窒化膜５６を堆積する（第４図（ａ）図
示）。次いで、ホトリソグラフィにより窒化膜５６を選
択的にエツチングし、ダート電極５４の両側方のうち一
方側に窒化膜パターン５６′を残存させる。つづいて、
酸素雰囲気中で熱処理を行ない、Ａｓドープト酸化膜５
５から基板５１中にＡｓ＋を拡散させる。この際、窒化
膜／４’ターン５６′の存在する箇所ではＡａはあまり
拡散しないが、窒化膜パターン５６′の存在しない箇所
ではＡｍは効率よく拡散する。この結果、Ｎ＋型ソース
領域５７１０−
及びＮ−型ドレイン領域５８が形成される（同図（ｂ）
図示）。次いで、前記窒化膜パターン５６′及びＡｓド
ープト酸化膜５５を順次エツチング除去した後、熱酸化
を行ない、ダート電極５４表面及び露出した基板５ノ弐
面を熱酸化膜５９に変換する。つづいて、°全面にＣＶ
Ｄ酸化ｇｔｉｅｏ＊堆積した後、コンタクトホール６１
．６１を開孔する。つづいて、全面にＡｔ−８＋膜を堆
積した後、Ａ？ターニングしてソース電極６２及びドレ
イン電極６３を形成し、ＭＯＳトランジスタを製造する
（同図（ｅ）図示）。Example 2 First, a field oxide film 52 is formed on the surface of a P-type silicon substrate 51, and then a dirt electrode 54 is formed on the element region surrounded by the field oxide film 52 via a dirt oxide film 53. Next, an As-doped oxide film 55 is deposited on the entire surface, and a nitride film 56 is further deposited on the entire surface (as shown in FIG. 4(a)). Next, the nitride film 56 is selectively etched by photolithography to leave a nitride film pattern 56' on one of both sides of the dirt electrode 54. Continuing,
Heat treatment is performed in an oxygen atmosphere to form an As-doped oxide film 5.
5, As+ is diffused into the substrate 51. At this time, Aa does not diffuse much in the area where the nitride film/4' turn 56' exists, but Am diffuses efficiently in the area where the nitride film pattern 56' does not exist. As a result, an N+ type source region 5710- and an N- type drain region 58 are formed (FIG. 5(b)).
(Illustrated). Next, after the nitride film pattern 56' and the As-doped oxide film 55 are removed by etching, thermal oxidation is performed to convert the surface of the dirt electrode 54 and the exposed second surface of the substrate 5 into a thermal oxide film 59. Next, °CV on the entire surface
Contact hole 61 after D oxidation gtieo* deposition
．． 61 is drilled. Next, after depositing an At-8+ film on the entire surface, A? Turning is performed to form a source electrode 62 and a drain electrode 63, and a MOS transistor is manufactured (as shown in FIG. 4(e)).
しかして上述した方法によれば、通常のＭＯＳプロセス
に比べてホトリソグラフィ工程は１回増えるものの、イ
オン注入工程を省略した比較的簡便な工程によりセルフ
ァラインでＮ＋型ソース領域５７及びＮ−型ドレイン領
域５８を形成することができ、ドレイン領域５８近傍の
チャネル領域における電界集中を抑制してトランジスタ
の不安定性を減少することができる。しかも、通常のＬ
ＤＤ構造のＭＯＳ ）ランジスタと異なりソース領域５
７側には低濃度不純物領域が形成されないのでソース抵
抗を無視することができ、ソース側の増幅率の向上にと
って有利となる。According to the method described above, although the number of photolithography steps is increased by one compared to the normal MOS process, the N+ type source region 57 and the N- type drain can be formed in the self-line by a relatively simple process that omits the ion implantation process. A region 58 can be formed to suppress electric field concentration in the channel region near the drain region 58 to reduce instability of the transistor. Moreover, normal L
DD structure MOS) Unlike a transistor, the source region 5
Since no low concentration impurity region is formed on the 7 side, the source resistance can be ignored, which is advantageous for improving the amplification factor on the source side.
以上詳述した如く本発明の半導体装置の製造方法によれ
ば、簡便な工程で少なくともドレイン領域のチャネル近
傍の部分が低濃度不純物領域で構成されたＭＯＳ半導体
装置を製造することができ、トランジスタの不安定性を
減少し、ひいては素子の微細化を達成し得る等顕著な効
果を奏するものである。As described in detail above, according to the method for manufacturing a semiconductor device of the present invention, it is possible to manufacture a MOS semiconductor device in which at least the portion of the drain region near the channel is formed of a low concentration impurity region through a simple process. This has remarkable effects such as reducing instability and making it possible to miniaturize elements.
の実施例１におけるＬＤＤ構造のＭＯＳ トランジスタ
の製造方法を示す断面図、第４図（、）〜（ｃ）は本発
明の実施例２におけるＭＯＳ ）ランジスタの製造方法
を示す断面図である。
２１．５１・・・Ｐ−型シリコン基板、２２ 、５２・
・・フィールド酸化膜、２３．５３・・・ダート酸化膜
、２４．５４・・・ダート電極、２５．５５・・・Ａ８
ドーゾト酸化膜、２６．５６・・・窒化膜、２６′・・
・残存窒化膜、５６′・・・窒化膜・母ターン、２７・
・・ソース領域、２８・・・ドレイン領域、２７ ａ
、 ２８ａ・・・Ｎ−型不純物領域、２７ｂ 、２８ｂ
・・・Ｎ＋型不純物領域、２９ 、５９−・・熱酸化膜
、ｇ ｏ 、 ６０ ・−・ＣＶＤ酸化膜、３ノ、６ノ
・・・コンタクトホール、３２゜６２・・・ソース電極
、３３．６３・・・ドレイン電極、５７・・・Ｎ＋型ソ
ース領域、５８・・・Ｎ−型ドレイン領域。
出願人代理人 弁理士 鈴 江 武 彦１３−
２
づ ０FIGS. 4(a) to 4(c) are cross-sectional views showing a method of manufacturing a MOS transistor having an LDD structure in Example 2 of the present invention. FIGS. 21.51...P-type silicon substrate, 22, 52.
... Field oxide film, 23.53 ... Dirt oxide film, 24.54 ... Dirt electrode, 25.55 ... A8
Dozot oxide film, 26.56...Nitride film, 26'...
・Residual nitride film, 56′...Nitride film・mother turn, 27・
... Source region, 28... Drain region, 27 a
, 28a...N-type impurity region, 27b, 28b
...N+ type impurity region, 29, 59--Thermal oxide film, go, 60...CVD oxide film, 3 no, 6 no... Contact hole, 32° 62... Source electrode, 33 .63...Drain electrode, 57...N+ type source region, 58...N- type drain region. Applicant's agent Patent attorney Takehiko Suzue 13-2 0
Claims (4)
縁膜を介してｆ−）電極を形成する工程と、全面に第２
導電型の不純物をドープした酸化膜を堆積する工程と、
該酸化膜上に部分的に窒化膜を残存させる工程と、酸素
雰囲気中で熱処理して前記酸化膜から基板中に不純物を
拡散させ、第２導電型のソース、ドレイン領域を形成す
る工程とを具備したことを特徴とする半導体装置の製造
方法。(1) Step of forming an f-) electrode on the element region of the first conductivity type semiconductor substrate via a dirt insulating film, and forming a second electrode on the entire surface.
Depositing an oxide film doped with conductivity type impurities;
a step of partially leaving a nitride film on the oxide film; and a step of performing heat treatment in an oxygen atmosphere to diffuse impurities from the oxide film into the substrate to form source and drain regions of a second conductivity type. A method for manufacturing a semiconductor device, comprising:
をドープした酸化膜を堆積し、該酸化膜のダート電極側
壁の部分をエツチング除去した後、全面に窒化膜を堆積
し、異方性エツチングにより前記ゲート′電極側壁にお
いて、前記酸化膜上に窒化膜を残存させることを特徴と
する特許請求の範囲第１項記載の半導体装置の製造方法
。(2) An oxide film doped with impurities of the second conductivity type is deposited on the entire surface using the Sono-9-Tree method, and after removing the dirt electrode sidewall portion of the oxide film by etching, a nitride film is deposited on the entire surface and anisotropically etched. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a nitride film is left on the oxide film on the side wall of the gate electrode by etching.
堆積し、更に全面に窒化膜を堆積した後、ダート電極の
両側方のうちいずれか一方側の酸化膜上に窒化膜を残存
させることを特徴とする特許請求の範囲第１項記載の半
導体装置の製造方法。(3) After depositing an oxide film containing impurities of the second conductivity type on the entire surface and further depositing a nitride film on the entire surface, a nitride film is placed on the oxide film on either side of the dirt electrode. 2. The method of manufacturing a semiconductor device according to claim 1, wherein:
ープト酸化膜であることを特徴とする特許請求の範囲第
１項乃至第３項いずれか記載の半導体装置の製造方法。(4) The method of manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the oxide film doped with an impurity of the second conductivity type is an Am-doped oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18270883A JPS6074681A (en) | 1983-09-30 | 1983-09-30 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18270883A JPS6074681A (en) | 1983-09-30 | 1983-09-30 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6074681A true JPS6074681A (en) | 1985-04-26 |
Family
ID=16123040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18270883A Pending JPS6074681A (en) | 1983-09-30 | 1983-09-30 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6074681A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0358430A (en) * | 1989-07-27 | 1991-03-13 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US5518945A (en) * | 1995-05-05 | 1996-05-21 | International Business Machines Corporation | Method of making a diffused lightly doped drain device with built in etch stop |
-
1983
- 1983-09-30 JP JP18270883A patent/JPS6074681A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0358430A (en) * | 1989-07-27 | 1991-03-13 | Toshiba Corp | Semiconductor device and manufacture thereof |
| US5518945A (en) * | 1995-05-05 | 1996-05-21 | International Business Machines Corporation | Method of making a diffused lightly doped drain device with built in etch stop |
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