JPS6072324A - Analog-to-digital converter - Google Patents
Analog-to-digital converterInfo
- Publication number
- JPS6072324A JPS6072324A JP17911783A JP17911783A JPS6072324A JP S6072324 A JPS6072324 A JP S6072324A JP 17911783 A JP17911783 A JP 17911783A JP 17911783 A JP17911783 A JP 17911783A JP S6072324 A JPS6072324 A JP S6072324A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- range
- comparator
- comparators
- analog
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
- H03M1/145—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages
- H03M1/146—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages all stages being simultaneous converters
- H03M1/147—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit the steps being performed sequentially in series-connected stages all stages being simultaneous converters at least two of which share a common reference generator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type
- H03M1/361—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type
- H03M1/362—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider
- H03M1/365—Analogue value compared with reference values simultaneously only, i.e. parallel type having a separate comparator and reference value for each quantisation level, i.e. full flash converter type the reference values being generated by a resistive voltage divider the voltage divider being a single resistor string
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はテレビ信号をディジタル変換できる高速のア
ナログディジタル変換器に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a high-speed analog-to-digital converter capable of digitally converting television signals.
従来、高速アナログディジタル変換を行うアナログ・デ
ィジタル変換方式として並列Ａ／Ｄ変換方式が知られて
いる。これは必要とするビット数分だけの比較器を並べ
て変換する方式である。しかしながら、この方式では例
えば８ビツトの場合に２５５ 個の比較１器が必要とな
り、集積化した場合にチップ面ゴが人尿〈なシ、消費電
力も増し、結果的に歩□、シが癲くなるという欠点が存
在した。 ： １
： ：
この発明の目的は素子数を□少な＋して、省電力化した
アナログディジタル□変換峠提供することにある。 １
１
Ｃ□。□、１１
この発明は予備比較器を設□けて火力信号のだいたいの
値を知ることによっ□て、某比較器の基１
準電圧位置を移動させるこ；に裏門
して素子数が少なくてすみ？ｉ４費電訊も少なくて、６
゜Ｈ７ｋＢｏ ’ １
〔８１゜実□、〕 ・ １
以下本発明を図面を参照して詳ｉに説明する。Conventionally, a parallel A/D conversion method has been known as an analog-to-digital conversion method that performs high-speed analog-to-digital conversion. This is a method of lining up as many comparators as the number of bits required for conversion. However, this method requires 255 comparators in the case of 8-bit, for example, and when integrated, the chip space is reduced to human waste, power consumption also increases, and as a result, the processing speed and performance are reduced. There was a drawback that it became : 1 : : An object of the present invention is to provide an analog-to-digital conversion which reduces the number of elements and saves power. 1
1 C□. □, 11 This invention provides a backup comparator and learns the approximate value of the firepower signal, thereby allowing the base voltage position of a certain comparator to be moved, thereby reducing the number of elements. Tesumi? I4 cost telephone number is also low, 6
゜H7kBo ' 1 [81゜Act □,] ・ 1 The present invention will be explained in detail below with reference to the drawings.
第１図は本発明の一実施楓に工賦アナログディｉンタル
変換器のブロック１であ鼠。図中１１゛〜１７は予備比
較器（３ビツト分′）であシ、そλ℃それ入力信号と、
抵抗により電圧を分圧して得られた基準電圧ＶＲ＋〜ｖ
Ｒ７が供給され、その大小を比較する。この予備比較器
１１〜１７の出力はアナログスイッチ回路Ｓ Ｗ ７〜
８ｗ７に供給される。これらアナログスイッチ回路ＳＷ
Ｉ〜ＳＷ、７は予備比較器からの出力にニジ同時に導通
する各々３個のスイッチＡ８−ｎ、ＢＳ−ｎ。FIG. 1 shows a block 1 of an analog-to-digital converter constructed in one embodiment of the present invention. In the figure, 11' to 17 are preliminary comparators (3 bits'), and the input signal is λ℃,
Reference voltage VR+~v obtained by dividing the voltage using resistors
R7 is supplied and its magnitude is compared. The outputs of the preliminary comparators 11 to 17 are analog switch circuits SW7 to
8w7 is supplied. These analog switch circuits SW
I to SW, 7 are three switches A8-n and BS-n, respectively, which simultaneously conduct to the output from the preliminary comparator.
Ｃ３−ｎ（但しｎ＝１．２−．７） を有しているＯＡ
Ｓ −ｎの一端は基準電圧ＶＲ（ｎ＋りに、Ｂ Ｓ
−ｎの一端はＶＲｎとＶｉ（ｎ＋１） の中間の電圧に
、そしてＣＢ −ｎの一端はｖＲ（ｎ−、） にそれぞ
れ接続されている。また他端はＡＳスイッチ同志、Ｂ８
スイッチ同志、ＣＳスイッチ同志でそれぞれ共通に接続
されている。共通接続されたＡｓスイッチの出力Ｖｓ、
、ＢＳスイッチの出力Ｖｓ、そしてＣＳスイッチの出力
Ｖｓｊはラダー抵抗２１の両端および中点に供給され、
ラダー抵抗の電圧範囲を決定する。なおＣＳスイッチの
各出力ｄ、〜ｄ７は図示するようなＭＳＢエンコーダ３
１に供給されＭＯＢ出力を発生する。ラダー抵抗２１の
電圧範囲は、例えば入力電圧が予備比較器の基準電圧Ｖ
ＲａとＶＲ，の間にあった場合はその１つ上と１つ下の
電圧範囲のＶＲｓとＶＲ８＋”、 ／’、１ｅ＋ ｕ
：、 、＋＋、 、、＋＋ Ｘ’ｓ 、 ｔ！ Ｖｍ＠
、’ 、・’Ｉｔ＋ Ｓ’ｓ、 ｉＪ Ｓ’ｓ、 、
ＩＶＲ６の中間電位となる。ラダー抵抗２ Ｊ ）Ｊこ
の電圧範囲をさらに細か゛く分圧、その分圧電圧を入力
電圧とともに本比較器４１に供給する０本比較器４ノは
第２図に示すように３つの比較部（４１−１） 、 （
４７−、？） 、 （４７−Ｊ）から成る。この本比較
器４１は比較部４１−２で変換を行った場合１−は何も
せずそのままラッチ回路５１を介してＬＳＢ出力をする
。また、比較部４１−１の範囲で変換を行った場合はＬ
ＳＢ出力すると同時にＭＳＢに１を加える。又、比較部
４１−３の場合は−１を加えることによって正確なアナ
ログディジタル変換を行うことができることになる０
ところでこのままでは本比較器４１にはＬＳＨのビット
数を出力する時の比較器数の３倍が必要となる。比較部
４１−１と４１−３の両端にある比較器は入力信号に高
周波成分が存在する時だけ動作し、低周波領域では動作
しない。また、高周波域では比較器の誤動作から最少ビ
ットを正確に出力することができず、また実際上必要と
しない。そこで第２図に示すように比較部４１−１の上
と４１−３の下の位置に存在する比較器を間引くことが
可能である。このようにすると比較器数が少なくなると
ともに消費電流が少なくなるのてチップ面積の減少、省
電力が図れるのでコスト低減、高分留りが期待できるこ
とになり都合が良い。さらにシダー抵抗電位に誤差を力
えるベース電流が減少するので精度も上ることになる。OA with C3-n (however, n=1.2-.7)
One end of S −n is the reference voltage VR (on the other hand, B S
One end of -n is connected to a voltage intermediate between VRn and Vi(n+1), and one end of CB -n is connected to vR(n-,). Also, the other end is the same AS switch, B8
The switches and CS switches are connected in common. The output Vs of the commonly connected As switch,
, the output Vs of the BS switch, and the output Vsj of the CS switch are supplied to both ends and the middle point of the ladder resistor 21,
Determine the voltage range of the ladder resistor. Note that each output d, ~d7 of the CS switch is an MSB encoder 3 as shown in the figure.
1 and generates MOB output. The voltage range of the ladder resistor 21 is such that, for example, the input voltage is the reference voltage V of the preliminary comparator.
If it is between Ra and VR, VRs and VR8+", /', 1e+ u in the voltage range one above and one below
:, ,++, ,,++ X's, t! Vm@
,',・'It+S's, iJ S's, ,
It becomes the intermediate potential of IVR6. Ladder resistor 2J)J divides this voltage range even more finely and supplies the divided voltage to this comparator 41 together with the input voltage.The comparator 4 has three comparators ( 41-1), (
47-,? ), (47-J). When the comparator 41-2 performs conversion, the main comparator 41 outputs the LSB directly via the latch circuit 51 without doing anything if the signal is 1-. In addition, when conversion is performed within the range of comparison section 41-1, L
Add 1 to the MSB at the same time as outputting the SB. In addition, in the case of the comparator 41-3, by adding -1, accurate analog-to-digital conversion can be performed.By the way, as it is, this comparator 41 has only the number of comparators when outputting the number of bits of LSH. Three times as much is required. The comparators at both ends of the comparators 41-1 and 41-3 operate only when a high frequency component is present in the input signal, and do not operate in a low frequency region. Furthermore, in a high frequency range, the minimum bit cannot be output accurately due to malfunction of the comparator, and is not actually necessary. Therefore, as shown in FIG. 2, it is possible to thin out the comparators located above the comparison section 41-1 and below the comparison section 41-3. This is advantageous because the number of comparators is reduced and current consumption is reduced, resulting in a reduction in chip area and power savings, resulting in cost reduction and high fractional yield. Furthermore, since the base current that causes errors in the cedar resistance potential is reduced, accuracy is also improved.
第１図は本発明のアナログディジタル変換器のブロック
図、第２図は本比較器をさらに具体的に表わしたブロッ
ク図である。
１１〜１７・・°予備比較器、８ Ｗ ７〜ＳＷ７・・
・アナログスイッチ回路、２１・・・ラダー抵抗、３１
・・・ＭＢＳエンコーダ、４ノ・・本比較器、５ノ・・
・ラッチ回路。FIG. 1 is a block diagram of an analog-to-digital converter of the present invention, and FIG. 2 is a block diagram showing the present comparator in more detail. 11~17...°Preliminary comparator, 8 W 7~SW7...
・Analog switch circuit, 21... Ladder resistor, 31
...MBS encoder, 4th one...Comparator, 5th one...
・Latch circuit.
Claims (1)
較器を多数並列に並べた比較器群の基準電圧を決定する
手段を有する変換方式において、基準電圧の両端に近い
部分の比較器をところどころなくすことによって比較器
数の減少を図ったアナログディジタル変換器。In a conversion method that uses a preliminary comparator to determine the approximate position of the analog input and determines the reference voltage of a group of comparators arranged in parallel, the comparators near both ends of the reference voltage are An analog-to-digital converter that reduces the number of comparators by eliminating them.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17911783A JPS6072324A (en) | 1983-09-29 | 1983-09-29 | Analog-to-digital converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17911783A JPS6072324A (en) | 1983-09-29 | 1983-09-29 | Analog-to-digital converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6072324A true JPS6072324A (en) | 1985-04-24 |
Family
ID=16060302
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17911783A Pending JPS6072324A (en) | 1983-09-29 | 1983-09-29 | Analog-to-digital converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6072324A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS626537A (en) * | 1985-06-28 | 1987-01-13 | アールシーエー トムソン ライセンシング コーポレイシヨン | Load limiter for flash type a/d converter |
-
1983
- 1983-09-29 JP JP17911783A patent/JPS6072324A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS626537A (en) * | 1985-06-28 | 1987-01-13 | アールシーエー トムソン ライセンシング コーポレイシヨン | Load limiter for flash type a/d converter |
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