JPS6060726A - Treating device - Google Patents

Treating device

Info

Publication number
JPS6060726A
JPS6060726A JP16819083A JP16819083A JPS6060726A JP S6060726 A JPS6060726 A JP S6060726A JP 16819083 A JP16819083 A JP 16819083A JP 16819083 A JP16819083 A JP 16819083A JP S6060726 A JPS6060726 A JP S6060726A
Authority
JP
Japan
Prior art keywords
gas
shielding member
processing
electrodes
wafer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16819083A
Other languages
Japanese (ja)
Inventor
Seiichi Kato
誠一 加藤
Tsutomu Okabe
勉 岡部
Kazuhiko Yonemitsu
米光 一彦
Yoshimune Yamamoto
山本 良宗
Toru Naito
亨 内藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Hitachi Tokyo Electronics Co Ltd
Hitachi Ltd
Hitachi Ome Electronic Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Tokyo Electronics Co Ltd, Hitachi Ltd, Hitachi Ome Electronic Co Ltd filed Critical Hitachi Tokyo Electronics Co Ltd
Priority to JP16819083A priority Critical patent/JPS6060726A/en
Publication of JPS6060726A publication Critical patent/JPS6060726A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To enable to equally feed gas to an objective material to be treated by a method wherein a shielding member having penetrated holes is provided between mutually parallel flat plate electrodes. CONSTITUTION:An objective material 19 to be treated is placed on one side of mutually parallel flat plate electrodes 12 and 13 provided in a treating chamber 11 and the objective material 19 is treated by a gas electrochemical reaction of high-frequecy voltage, which is impressed on the electrodes 12 and 13, and gas, which is fed from a gas introducing passage 14. A shielding member 16 having penetrated holes 17 is provided between the electrodes 12 and 13 in the treating chamber 11. The gas, which is fed from the gas introducing passage 14, can be equally fed to the objective material 19 to be treated by the shielding member 16. As a result, treatments such as etching, etc., are uniformly performed.

Description

【発明の詳細な説明】 [技術分野] 本発明は、処理技術、特に、プラズマ反応を利用して処
理を行う技術に関し、たとえば、半導体装置の製造にお
いて使用されるドライエツチング処理やC,VD処理等
に利用して有効な技術に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to processing technology, particularly technology that performs processing using plasma reactions, such as dry etching processing, C, VD processing, etc. used in the manufacture of semiconductor devices. Regarding effective techniques that can be used for etc.

[背景技術] 半導体装置の製造において、従来、エツチング処理を実
施する場合、プラズマ反応を利用したドライエツチング
装置が使用されている(たとえば、昭和57年10月3
0日新技術開発センター発行の半導体製造技術集成、P
、197参照)。
[Background Art] In the manufacture of semiconductor devices, dry etching equipment that utilizes plasma reaction has conventionally been used to perform etching processing (for example,
Semiconductor manufacturing technology collection published by New Technology Development Center, P.
, 197).

かかるドライエツチング装置として、ガス導入路と排気
路とを備えた処理室に平行平板電極が設けられ、その電
極の一方にウェハを載置して高周波電圧を印加し、電極
間に形成されるプラズマによる気体電気化学反応により
ウェハにエツチング処理を施すようになっている。
As such a dry etching apparatus, parallel plate electrodes are provided in a processing chamber equipped with a gas introduction path and an exhaust path, a wafer is placed on one of the electrodes, a high frequency voltage is applied, and a plasma is formed between the electrodes. The etching process is performed on the wafer through a gas electrochemical reaction.

しかし、かかるドライエツチング装置においては、ウェ
ハに処理ガスを均一に供給することが困難であるため、
ウェハの中央部では周辺部に比ベエソチング処理が遅く
なり、処理が不均一になるという問題点があることが、
本発明者によって明らかにされた。
However, in such dry etching equipment, it is difficult to uniformly supply processing gas to the wafer.
The problem is that the etching process is slower at the center of the wafer than at the periphery, resulting in uneven processing.
revealed by the inventor.

そこで、一方の電極に開口を設けて処理ガスをウェハ上
に均一に供給するようにしてなるドライエツチング装置
が考えられる。
Therefore, a dry etching apparatus can be considered in which an opening is provided in one electrode to uniformly supply processing gas onto the wafer.

しかし、かかるドライエツチング装置においては、電極
に開口が設けられるため、電界が不均一になり、処理が
不均一になるばかりでなく、一部では電界が集中するた
め、ウェハにダメージを与えるという問題点が発生する
ことが、本発明者によって明らかにされた。
However, in such dry etching equipment, since openings are provided in the electrodes, the electric field becomes non-uniform, which not only results in non-uniform processing, but also causes damage to the wafer as the electric field concentrates in some areas. The inventor has revealed that points occur.

[発明の目的] 本発明の目的は、処理を均一に行うことができる処理技
術を提供することにある。
[Object of the Invention] An object of the present invention is to provide a processing technique that allows uniform processing.

本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述および添付図面から明らかになるであろう
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[発明の概要] 本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、次の通りである。
[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

すなわち、平行平板電極間に透孔を有する遮蔽部材を設
けることにより、電界の集中を引き起こすことなくして
処理対象物にガスが均等に供給されるようにしたもので
ある。
That is, by providing a shielding member having a through hole between the parallel plate electrodes, gas is uniformly supplied to the object to be processed without causing concentration of electric field.

[実施例] 図は本発明の一実施例であるドライエツチング装置を示
す縦断面図である。
[Embodiment] The figure is a longitudinal sectional view showing a dry etching apparatus which is an embodiment of the present invention.

本実施例において、このドライエツチング装置は、石英
ベルジャ等からなる処理室11を備えており、処理室1
1は気密が保たれるように構成されている。処理室11
には一対の平行平板電極12.13が下部および上部に
それぞれ配設されている。
In this embodiment, this dry etching apparatus is equipped with a processing chamber 11 made of a quartz bell jar or the like.
1 is constructed to maintain airtightness. Processing room 11
A pair of parallel plate electrodes 12 and 13 are arranged at the bottom and top, respectively.

処理室11の天井壁には、処理ガスとしてのエツチング
ガスを導入するための導入路14が上部電極13の真上
に開設され、処理室11の底壁には排気路15が室内を
真空引きするように接続されている。処理室11の内部
には、石英等により平板形状に形成された遮蔽部材16
が両電極12.13間において室内を仕切るように架設
されており、遮蔽部材16には複数の透孔17が中央部
に開設されている。上部電極13には高周波電源18が
接続されており、アースされた下部電極12は、処理対
象物としてのウェハ19を載置して保持し得るように構
成されている6 次に作用を説明する。
An introduction path 14 for introducing an etching gas as a processing gas is provided on the ceiling wall of the processing chamber 11 directly above the upper electrode 13, and an exhaust path 15 is provided on the bottom wall of the processing chamber 11 for evacuating the chamber. connected to. Inside the processing chamber 11, a shielding member 16 formed in a flat plate shape from quartz or the like is provided.
is installed between both electrodes 12 and 13 to partition the room, and the shielding member 16 has a plurality of through holes 17 formed in the center. A high frequency power source 18 is connected to the upper electrode 13, and the grounded lower electrode 12 is configured to be able to place and hold a wafer 19 as an object to be processed.6 Next, the operation will be explained. .

ウェハ19が下部電極12上に載置され、処理室11が
排気されてエツチングガスが導入されるとともに、両電
極12.13間に高周波電圧が印加されると、プラズマ
が形成され、これによる気体電気化学反応により、ウェ
ハ19にエツチング処理が施される。
When the wafer 19 is placed on the lower electrode 12, the processing chamber 11 is evacuated and etching gas is introduced, and a high frequency voltage is applied between the two electrodes 12 and 13, plasma is formed and the resulting gas is An etching process is performed on the wafer 19 by an electrochemical reaction.

このとき、導入路14から処理室11の遮蔽部材16の
上側空間に導入されたエツチングガスは均一に拡散した
後、遮蔽部材16の透孔17を通って下側空間に流れ込
み、下部電極12上のウェハ19に対し周辺部中央部の
全体にわたって均等に供給される。このように、エツチ
ングガスが全体にわたって均等に供給されるため、ウェ
ハ19に対するエツチングガスは全体にわたって均一に
施されることになる。
At this time, the etching gas introduced from the introduction path 14 into the upper space of the shielding member 16 of the processing chamber 11 is uniformly diffused, and then flows into the lower space through the through hole 17 of the shielding member 16 and is etched onto the lower electrode 12. The wafer 19 is supplied evenly throughout the periphery and the center of the wafer 19. In this way, since the etching gas is uniformly supplied over the entire wafer 19, the etching gas is evenly applied over the entire wafer 19.

また、両電極12.13はいずれも平板形状に形成され
ているため、電界は均一に形成される。
Furthermore, since both electrodes 12 and 13 are formed in a flat plate shape, the electric field is uniformly formed.

したがって、電界集中によりウェハ19に加えられるダ
メージの発生は未然に回避され、前述したエツチングの
均一処理も確保されることになる。
Therefore, damage to the wafer 19 due to electric field concentration can be avoided, and the uniform etching process described above can be ensured.

[効果] (1)、一対の平行平板電極間に透孔を有する遮蔽部材
を介設することにより、ガスを処理対象物に均一に供給
することができるため、対象物における処理を全体にわ
たって均一に施すことができる。
[Effects] (1) By interposing a shielding member with a through hole between a pair of parallel plate electrodes, gas can be uniformly supplied to the object to be processed, so that the processing on the object can be uniformly performed over the entire object. It can be applied to

(2)、遮蔽部材に透孔を開設することにより、電極を
変形させなくて済むため、電界が均一になり、電界集中
等の悪影響が回避できる。
(2) By providing a through hole in the shielding member, the electrode does not need to be deformed, so the electric field becomes uniform and adverse effects such as electric field concentration can be avoided.

(3)、前記(2)により、ガスの均一供給による処理
の均一化が維持できる。
(3) According to (2) above, uniformity of processing can be maintained by uniform supply of gas.

(4)、遮蔽部材を石英で形成することにより、処理対
象物としてのウェハに対する悪影響が回避できる。
(4) By forming the shielding member from quartz, adverse effects on the wafer as the object to be processed can be avoided.

以上本発明者によってなされた発明を実施例に基づき具
体的に説明したが、本発明は前記実施例に附定されるも
のではなく、その要旨を逸脱しない範囲で種々変更可能
であることはいうまでもない。
Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the Examples, and it should be noted that various changes can be made without departing from the gist of the invention. Not even.

たとえば、遮蔽部材は石英に限らず、フッ素樹脂やステ
ンレス等のようなウェハ等処理対象物への悪影響を小さ
く制御できる材料を用いて形成してもよい。遮蔽部材は
平板状に限らず、膜状に形成してもよい。
For example, the shielding member is not limited to quartz, but may be formed using a material such as fluororesin or stainless steel that can control the adverse effects on the processing target such as a wafer to a small extent. The shielding member is not limited to a flat plate shape, but may be formed in a film shape.

遮蔽部材の透孔は複数に限らず、単数でもよい。The number of through holes in the shielding member is not limited to a plurality, and may be a single number.

ガスはエツチングガスに限られないし、処理もエツチン
グに限られない。
The gas is not limited to etching gas, and the processing is not limited to etching.

[利用分野] 以」二の説明では主として本発明者によってなされた発
明をその背景となった利用分野である半導体装置の製造
において使用されるドライエツチング装置に適用した場
合について説明したが、それに限定されるものではなく
、たとえば、C,VD装置やアッシャ除去装置等プラズ
マ反応を利用する処理装置に適用できる。
[Field of Application] In the following explanation, the invention made by the present inventor is mainly applied to a dry etching apparatus used in the manufacture of semiconductor devices, which is the field of application that forms the background of the invention, but the present invention is not limited thereto. For example, the present invention can be applied to processing apparatuses that utilize plasma reactions, such as C and VD apparatuses and asher removal apparatuses.

【図面の簡単な説明】[Brief explanation of the drawing]

図は本発明の一実施例を示す縦断面図である。 11・・・処理室、12.13・・・電極、】4・・・
ガス導入路、15・・・排気路、16・・・遮蔽部材、
17・・・透孔、18・・・高周波電源、19・・・ウ
ェハ(処理対象物)。 ■ l/
The figure is a longitudinal sectional view showing an embodiment of the present invention. 11...Processing chamber, 12.13...Electrode, ]4...
Gas introduction path, 15... Exhaust path, 16... Shielding member,
17... Through hole, 18... High frequency power supply, 19... Wafer (processing target). ■ l/

Claims (1)

【特許請求の範囲】 】、処理室に設けられた平行平板電極の一方に処理対象
物が配され、処理室にガスを供給されて処理が(テわれ
る処理装置において、前記平行平板電極の間に透孔を有
する遮蔽部材が介設され、前記処理室の前記対象物が配
された側で排気され、その反対側の前−記ガスが供給さ
れることを特徴とする処理装置。 2、透孔が、遮蔽部材に複数開設されていることを特徴
とする特許請求の範囲第1項記載の処理装置。 3、遮蔽部材が、石英板で形成されていることを特徴と
する特許請求の範囲第1項記載の処理装置。
[Scope of Claims] ] In a processing apparatus in which an object to be processed is disposed on one side of parallel plate electrodes provided in a processing chamber, and a gas is supplied to the processing chamber to carry out the process, there is a gap between the parallel plate electrodes. A processing apparatus characterized in that a shielding member having a through hole is interposed in the processing chamber, exhaust is exhausted from the side of the processing chamber where the object is arranged, and the gas is supplied from the opposite side.2. The processing device according to claim 1, characterized in that a plurality of through holes are formed in the shielding member. 3. The processing device according to claim 1, characterized in that the shielding member is formed of a quartz plate. The processing device according to scope 1.
JP16819083A 1983-09-14 1983-09-14 Treating device Pending JPS6060726A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16819083A JPS6060726A (en) 1983-09-14 1983-09-14 Treating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16819083A JPS6060726A (en) 1983-09-14 1983-09-14 Treating device

Publications (1)

Publication Number Publication Date
JPS6060726A true JPS6060726A (en) 1985-04-08

Family

ID=15863450

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16819083A Pending JPS6060726A (en) 1983-09-14 1983-09-14 Treating device

Country Status (1)

Country Link
JP (1) JPS6060726A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5209803A (en) * 1988-08-30 1993-05-11 Matrix Integrated Systems, Inc. Parallel plate reactor and method of use

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5209803A (en) * 1988-08-30 1993-05-11 Matrix Integrated Systems, Inc. Parallel plate reactor and method of use

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