JPS6057945A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6057945A
JPS6057945A JP58167295A JP16729583A JPS6057945A JP S6057945 A JPS6057945 A JP S6057945A JP 58167295 A JP58167295 A JP 58167295A JP 16729583 A JP16729583 A JP 16729583A JP S6057945 A JPS6057945 A JP S6057945A
Authority
JP
Japan
Prior art keywords
junction
schottky
schottky junction
region
type region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58167295A
Other languages
Japanese (ja)
Inventor
Kiyoyuki Tsurumiya
鶴宮　清行
Kazuo Yamanaka
和夫 山中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP58167295A priority Critical patent/JPS6057945A/en
Publication of JPS6057945A publication Critical patent/JPS6057945A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05005—Structure
    • H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05073—Single internal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode

Abstract

PURPOSE:To improve reliability and quality by forming a p-n juction region while being adjoined to a Schottky junction section and bonding a wire for a leading-out to the outside onto an electrode for a Schottky junction extending on the p-n junction region. CONSTITUTION:A p<+> type region 10 is formed at the center of a Schottky junction 2, and a p-n junction is shaped between the region 10 and an n-type silicon substrate 1. A Schottky junction is not formed between a Schottky metal 3 and the p<+> type region because the concentration of the p<+> type region 10, particularly, the concentration of the surface, is increased in the structure. When a bonding section 5 is formed on the p<+> type region 10 in such structure, the Schottky junction is not broken by the mechanical shock of bonding. Since the built-in potential of the p-n junction is made higher than the forward rise voltage of the Schottky junction, forward currents do not flow through the p<+> type region 10, and forward currents flow only through the Schottky junction.

Description

【発明の詳細な説明】 （ａｌ　発明の技術分野 本発明は半導体装置のうち、特にショットキーバリヤ形
半導体素子の改善された構造に関する。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to improved structures of semiconductor devices, particularly Schottky barrier type semiconductor devices.

山）従来技術と問題点 ショットキーバリヤダイオードやショットキ高形電界効
果トランジスタなどのショットキーバリヤ形半導体素子
は、スイッチング動作が高速化するため、単体として、
あるいは半導体集積回路（ＩＣ）内に組み込まれて広く
利用されている。M) Conventional technology and problems Schottky barrier type semiconductor devices such as Schottky barrier diodes and Schottky high field effect transistors have high-speed switching operations, so they cannot be used as a single unit.
Alternatively, it is widely used by being incorporated into a semiconductor integrated circuit (IC).

第１図はショットキーバリヤダイオードの一例の漸函図
を示しており、１はシリコン基板、２はショットキー接
合部、３はショットキーメタル（半導体と接合してショ
ットキーバリヤを形成する金属）、４は電極金属、５は
ボンディング部、６はワイヤーで、例えばショットキー
メタルとしてモリブデン（Ｍｏ）　、電極金属としてア
ルミニウム（ＡＩ）などが用いられる。Fig. 1 shows a progressive diagram of an example of a Schottky barrier diode, where 1 is a silicon substrate, 2 is a Schottky junction, and 3 is a Schottky metal (metal that forms a Schottky barrier by joining with a semiconductor). , 4 is an electrode metal, 5 is a bonding portion, and 6 is a wire. For example, molybdenum (Mo) is used as the Schottky metal, and aluminum (AI) is used as the electrode metal.

ところで、このような構造に形成するために、電極金属
４上にワイヤー６が熱圧着あるいは超音波圧着によって
ボンディングされるが、その場合に既に形成されている
ショットキー接合部２に機械的ｉＥ撃を与えて、ショッ
トキー接合を破壊することがある。従って、従来からボ
ンディング加重を極力小さくして衝撃を与えないように
ボンディングしたり、あるいは電極金属を他の領域に引
き出してショットキー接合部２以外の面上でボンディン
グしたりして、この衝撃を避ける方法が採られている。By the way, in order to form such a structure, the wire 6 is bonded onto the electrode metal 4 by thermocompression bonding or ultrasonic compression bonding, but in that case, the already formed Schottky joint 2 is not subjected to mechanical iE shock. may destroy the Schottky junction. Therefore, conventional methods have been used to reduce this impact by minimizing the bonding load to avoid impact, or by pulling the electrode metal to another area and performing bonding on a surface other than the Schottky joint 2. There are ways to avoid it.

しかし、前者の場合はボンディングの条件設定が難しく
、ワイヤーボンディング後の接着強度が弱くなる場合が
ある。また、後者の場合は導出配線が長くなるため基板
との寄生容量が増加する欠点があり、またＩＣの高簗積
化を阻害する問題でもある。However, in the former case, it is difficult to set bonding conditions, and the adhesive strength after wire bonding may become weak. Moreover, in the latter case, the lead-out wiring becomes long, which has the disadvantage of increasing parasitic capacitance with the substrate, which also poses a problem that inhibits the increase in the size of the IC.

ｆｃｌ　発明の目的 本発明は、このような欠点を除去したショットキーバリ
ヤ形半導体素子の改善した構造を提案するものである。fcl OBJECTS OF THE INVENTION The present invention proposes an improved structure of a Schottky barrier type semiconductor device that eliminates these drawbacks.

ｆｄ＋　発明の構成 その目的は、ショットキー接合部に隣接してｐｎ接合領
域を設け、該ｐｎ接合領域上に延在するショットキー接
合用電極上に外部導出用ワイヤーがボンディングされて
いる構造を有する半導体装置によって達成される。fd+ Structure of the Invention The object is to have a structure in which a pn junction region is provided adjacent to a Schottky junction, and an external lead wire is bonded to the Schottky junction electrode extending over the pn junction region. This is achieved by a semiconductor device.

（ｅ）　発明の実施例 以下１図面を参照して実施例によって詳細に説明する。(e) Examples of the invention An embodiment will be described in detail below with reference to one drawing.

第２図は本発明にがかる一実施例としてのショットキー
バリヤダイオードの断面図である。図示のように、ショ
ットキー接合２の中央にｐ＋型領領域１０設け、ｎ型シ
リコン基板１との間にｐｎ接合を形成させる。本構造は
ｐ＋型領領域１０高濃度、特に表面濃度が高くなるため
、ショットキーメタル３とｐ＋型領領域の間にはショッ
トキー接合が形成されることがない。このような構造に
して、ｐ＋型領領域１０上ボンディング部５を形成する
と、ボンディングの機械的（ｈ撃によりショットキー接
合が破壊されることはなくなる。FIG. 2 is a sectional view of a Schottky barrier diode as an embodiment of the present invention. As shown in the figure, a p+ type region 10 is provided at the center of the Schottky junction 2, and a pn junction is formed between it and the n type silicon substrate 1. In this structure, since the concentration of the p+ type region 10 is high, especially the surface concentration, a Schottky junction is not formed between the Schottky metal 3 and the p+ type region. If the bonding portion 5 on the p+ type region 10 is formed in such a structure, the Schottky junction will not be destroyed due to mechanical shock during bonding.

且つ、ｐｎ接合のビルトインポテンシャル（Ｂｕｉｌｔ
　−Ｉｎ　Ｐｏｔｅｎｔｉａｌ　）はショットキー接合
の順方向立上り電圧（これはショットキー接合のビルト
インポテンシャルに関係する）より高くなるために、こ
のｐ＋型領領域１０通じて順方向の電流が流れることは
なく、ショットキー接合を通じてのみ順方向の電流が流
れる。例えば、ｐｎ接合の順方向立上り電圧が０．６Ｖ
程度、ショットキー接合の順方向立上り電圧が０．３Ｖ
以下になる。また、逆方向の耐圧もショットキー接合の
方か低くて、そのためにｐ＋型領領域１０設けてもショ
ットキー動作は害されずに、正常なショットキー特性が
得られる。第３図は公知のｐｎ接合のエネルギーバンド
図で、ＣＢは伝導帯、εＦはフェルミ準位、　ＶＢは価
電子帯、　ＢＰがビルトインポテンシャルを示している
。Moreover, the built-in potential of the pn junction (Built
-In Potential) is higher than the forward rising voltage of the Schottky junction (this is related to the built-in potential of the Schottky junction), so no forward current flows through this p+ type region 10, Forward current flows only through the Schottky junction. For example, the forward rising voltage of the pn junction is 0.6V
The forward rising voltage of the Schottky junction is 0.3V.
It becomes below. Further, the breakdown voltage in the reverse direction is lower than that of the Schottky junction, so that even if the p+ type region 10 is provided, the Schottky operation is not impaired and normal Schottky characteristics can be obtained. Figure 3 is an energy band diagram of a known pn junction, where CB is the conduction band, εF is the Fermi level, VB is the valence band, and BP is the built-in potential.

従って、本発明にかかる！造のショットキーバリヤダイ
オードはボンディング部の接着強度が安定し、且つ寄生
容量の増加する心配もない。Therefore, according to the present invention! The Schottky barrier diode of this type has stable adhesive strength at the bonding part, and there is no need to worry about an increase in parasitic capacitance.

次に、第４図ないし第６図にその形成工程順断面図を示
している。第４図に示すようにｎ型シリコン基扱１上の
二酸化シリコン（Ｓｉ０２　）　ｌ１ｆｌ　１をパター
ンニングして１５０μｍφの窓１２をあけ、硼素を拡散
してｐ＋型領領域１０形成する。この時、１０００℃程
度の高温熱処理が必要である。Next, FIGS. 4 to 6 show cross-sectional views in the order of the formation process. As shown in FIG. 4, silicon dioxide (Si02) l1fl 1 on the n-type silicon substrate 1 is patterned to open a window 12 of 150 μm in diameter, and boron is diffused to form the p+ type region 10. At this time, high temperature heat treatment of about 1000°C is required.

次いで、第５図に示すようにショットキー接合を形成す
るため、上記のｐ＋型領域工０を含む平面の５ｉ０２欣
１１に７００μｍ角の窓１３を形成する。次いで、第６
図に示すように蒸着法によって膜厚１０００人のＭｏ膜
（ショットキーメタル）３を被着し、パターンニングし
た後、４００℃、１０分間熱処理してショットキー接合
部２を形成し、更に膜厚２μｍのＡＩ膜（電極金属）４
を被着し、パターンニングする。以降は、ｐ＋型領域ｌ
ｏ上に直径５０μｍφの金線（ワイヤー）６を熱圧着（
ネールヘッド）によりボンディングして、第２図に示す
ように完成させる。Next, as shown in FIG. 5, in order to form a Schottky junction, a 700 μm square window 13 is formed in the plane 5i02 11 including the p+ type region 0 described above. Then, the sixth
As shown in the figure, a Mo film (Schottky metal) 3 with a thickness of 1000 is deposited by vapor deposition, patterned, and then heat treated at 400°C for 10 minutes to form a Schottky junction 2. 2 μm thick AI film (electrode metal) 4
is applied and patterned. From then on, the p+ type region l
A gold wire (wire) 6 with a diameter of 50 μmφ is thermocompression bonded (
Bonding is performed using a nail head) to complete the process as shown in FIG.

上記はショットキーバリヤダイオードを例とした説明で
あるが、その他のショットキーバリヤ形素子にも本発明
を適用できることは勿論である。Although the above explanation takes the Schottky barrier diode as an example, it goes without saying that the present invention can be applied to other Schottky barrier type elements.

また、ショットキーメタルもＭｏに限定されるものでは
ない。Furthermore, the Schottky metal is not limited to Mo.

（ｆｌ　発明の効果 以上の説明から明らかなように、本発明によればショッ
トキー接合が破壊されて、例えば耐圧が劣化する等の障
害がなくなり、極めて高信幀化。(fl) Effects of the Invention As is clear from the above explanation, according to the present invention, problems such as breakdown of the Schottky junction and deterioration of withstand voltage, for example, are eliminated, and reliability is extremely high.

高品質化したショットキーバリヤ形素子を得られる。従
って、ＩＣや他の電子回路の信頼性向上に著しく貢献す
るものである。A high quality Schottky barrier type element can be obtained. Therefore, it significantly contributes to improving the reliability of ICs and other electronic circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のショットキーバリヤダイオードの断面図
、第２図は本発明にがかる一実施例のシヨツトキーバリ
ヤダイオードの断面図、第３図はエネルギーバンド図、
第４図〜第６図は第２図に示す実施例の形成工程順断面
図である。 図中、１はシリコン基板、２はショットキー接合、３は
ショットキーメタル、４は電極金属、５はボンディング
部、６はワイヤー、１０はｐ＋型領領域１１は５ｉ０２
膜、１２．１３は窓を示している。 第１図 第２図 第３図 ｐ　ｎFIG. 1 is a sectional view of a conventional Schottky barrier diode, FIG. 2 is a sectional view of a Schottky barrier diode according to an embodiment of the present invention, and FIG. 3 is an energy band diagram.
4 to 6 are cross-sectional views in the order of forming steps of the embodiment shown in FIG. 2. In the figure, 1 is a silicon substrate, 2 is a Schottky junction, 3 is a Schottky metal, 4 is an electrode metal, 5 is a bonding part, 6 is a wire, 10 is a p+ type region 11 is 5i02
The membrane, 12.13, indicates the window. Figure 1 Figure 2 Figure 3 p n

Claims (1)

【特許請求の範囲】[Claims] ショットキー接合部に隣接してｐｎ接合領域を設け、該
ｐｎ接合領域上に延在するショットキー接合用電極上に
外部導出用ワイヤーがボンディングされている構造を有
することを特徴とする半導体装置。1. A semiconductor device having a structure in which a pn junction region is provided adjacent to a Schottky junction, and an external lead wire is bonded to an electrode for the Schottky junction extending over the pn junction region.
JP58167295A 1983-09-09 1983-09-09 Semiconductor device Pending JPS6057945A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58167295A JPS6057945A (en) 1983-09-09 1983-09-09 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58167295A JPS6057945A (en) 1983-09-09 1983-09-09 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS6057945A true JPS6057945A (en) 1985-04-03

Family

ID=15847101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58167295A Pending JPS6057945A (en) 1983-09-09 1983-09-09 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS6057945A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63137569A (en) * 1986-11-27 1988-06-09 Tamura Seisakusho Co Ltd Jet type soldering device
KR20030035798A (en) * 2001-10-18 2003-05-09 미쓰비시덴키 가부시키가이샤 Semiconductor device and method of manufacturing the same
KR100503936B1 (en) * 2001-08-22 2005-07-27 미쓰비시덴키 가부시키가이샤 Semiconductor device
KR101003808B1 (en) 2010-04-06 2010-12-23 한국기계연구원 Multiple solar cell having p-n juction and schottky juction, and fabricating method thereof

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63137569A (en) * 1986-11-27 1988-06-09 Tamura Seisakusho Co Ltd Jet type soldering device
KR100503936B1 (en) * 2001-08-22 2005-07-27 미쓰비시덴키 가부시키가이샤 Semiconductor device
KR20030035798A (en) * 2001-10-18 2003-05-09 미쓰비시덴키 가부시키가이샤 Semiconductor device and method of manufacturing the same
KR101003808B1 (en) 2010-04-06 2010-12-23 한국기계연구원 Multiple solar cell having p-n juction and schottky juction, and fabricating method thereof

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