JPS6052754U - Frequency modulation signal generator - Google Patents
Frequency modulation signal generatorInfo
- Publication number
- JPS6052754U JPS6052754U JP14434283U JP14434283U JPS6052754U JP S6052754 U JPS6052754 U JP S6052754U JP 14434283 U JP14434283 U JP 14434283U JP 14434283 U JP14434283 U JP 14434283U JP S6052754 U JPS6052754 U JP S6052754U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- register
- frequency modulation
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は、従来技術によるディジタル周波数シンセサイ
ザ方式の周波数変調信号発生装置の一例の基本的ブロッ
ク構成を示す図である。第２図は、第１図における各部
の波形を示す図である。
第３図は、本考案による周波数変調信号発生装置の一実
施例の基本的ブロック構成を示す図゛である。第４図は
、第３図における各部の波形を示す図である。第５図は
、レジスタクロック信号の送 ・出をパラメータとして
、レジスタ回路の記憶内容と全加算回路の演算内容との
間の関係を示す図である。
１・・・全加算回路、２・・・レジスタ回路、３・・・
補数回路、４・・・Ｄ／Ａ変換回路、５・・・低域炉液
器付き増幅回路、６・・・基準発振回路、７・・・分周
回路、１４・・・計数回路、１５・・・演算制御回路、
１６・・・レジスタ制御回路、８〜１３．１７〜２２・
・・信号線。FIG. 1 is a diagram showing a basic block configuration of an example of a conventional digital frequency synthesizer type frequency modulation signal generation device. FIG. 2 is a diagram showing waveforms at various parts in FIG. 1. FIG. 3 is a diagram showing a basic block configuration of an embodiment of a frequency modulation signal generator according to the present invention. FIG. 4 is a diagram showing waveforms at various parts in FIG. 3. FIG. 5 is a diagram showing the relationship between the storage contents of the register circuit and the calculation contents of the full adder circuit, using the sending/output of the register clock signal as a parameter. 1... Full adder circuit, 2... Register circuit, 3...
Complement circuit, 4... D/A conversion circuit, 5... Amplifying circuit with low range furnace liquid container, 6... Reference oscillation circuit, 7... Frequency dividing circuit, 14... Counting circuit, 15 ... Arithmetic control circuit,
16...Register control circuit, 8-13.17-22.
··Signal line.
Claims (1)
ための全加算回路と、前記全加算回路の内容を記憶する
ためのレジスタ回路と、前記レジスタ回路の最上位ビッ
トの内容に対応して前記全加算回路の出力の補数をとる
ための補数回路と、前記補数回路の出力をアナログ化す
るためのＤ／Ａ変換回路と、前記Ｄ／Ａ変換回路の出力
を炉液して増幅するための低域ろ波器付き増幅回路と、
前記レジスタクロック信号を発生させるための基準発振
回路ならびに分周回路とにより構成されたディジダル周
波数シンセサイザ方式の周波数変調信号発生装置におい
て、入力設定信号によって外部で任意に設定された条件
信号である希望発振周波数値を設定し、計数動作信号に
より計数動作を行うための計数回路と、外部で任意に設
定された条件信号であるパルス幅信号と、周波数変調幅
信号と、発振開始信号とを受けると共に前記基準発振回
路からの基本クロック信号を受けて前記計数回路へ前記
入力設定信号と前記計数動作信号とを出力し、さらに制
御信号により前記レジスタ回路の制御を指示すると共に
前記レジスタ回路へ初期値設定の指示をするための演算
制御回路と、前記演算制御回路からの前記制御信号と前
記分周回路からのレジスタクロック信号とを受けて前記
レジスタ回路の駆動信号を発生するためのレジスタ制御
回路とを具備し、前記計数回路の計数出力信号を前記全
加算回路の入力に加え、前記基準発振回路からの基本ク
ロック信号を前記演算制御回路に加えることによって、
前記外部で任意に設定された発振周波数と周波数変調幅
とを有し、発振開始信号に同期した正弦波の周波数変調
信号を発生するように構成したことを特徴とする周波数
変調信号発生装置。a full adder circuit for performing addition in response to the period of a register clock signal; a register circuit for storing the contents of the full adder circuit; a complement circuit for taking the complement of the output of the adder circuit; a D/A conversion circuit for converting the output of the complement circuit into an analog; an amplifier circuit with a bandpass filter;
In the digital frequency synthesizer type frequency modulation signal generation device that is configured with a reference oscillation circuit and a frequency dividing circuit for generating the register clock signal, the desired oscillation signal is a condition signal arbitrarily set externally by an input setting signal. A counting circuit for setting a frequency value and performing a counting operation using a counting operation signal, a pulse width signal that is a condition signal arbitrarily set externally, a frequency modulation width signal, and an oscillation start signal, and Receiving a basic clock signal from a reference oscillation circuit, outputting the input setting signal and the counting operation signal to the counting circuit, and further instructing control of the register circuit by a control signal and setting an initial value to the register circuit. The register control circuit includes an arithmetic control circuit for issuing instructions, and a register control circuit for receiving the control signal from the arithmetic control circuit and the register clock signal from the frequency dividing circuit and generating a drive signal for the register circuit. and by adding the count output signal of the counting circuit to the input of the full adder circuit and adding the basic clock signal from the reference oscillation circuit to the arithmetic control circuit,
A frequency modulation signal generating device, characterized in that it has an oscillation frequency and a frequency modulation width arbitrarily set externally, and is configured to generate a sinusoidal frequency modulation signal synchronized with the oscillation start signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14434283U JPS6052754U (en) | 1983-09-16 | 1983-09-16 | Frequency modulation signal generator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14434283U JPS6052754U (en) | 1983-09-16 | 1983-09-16 | Frequency modulation signal generator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6052754U true JPS6052754U (en) | 1985-04-13 |
Family
ID=30321908
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14434283U Pending JPS6052754U (en) | 1983-09-16 | 1983-09-16 | Frequency modulation signal generator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6052754U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS646884A (en) * | 1987-06-30 | 1989-01-11 | Nec Corp | Variable constant type chirp signal generating circuit |
| WO2013094459A1 (en) * | 2011-12-19 | 2013-06-27 | 古野電気株式会社 | Direct digital synthesizer, reference frequency generation device, and sine wave output method |
-
1983
- 1983-09-16 JP JP14434283U patent/JPS6052754U/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS646884A (en) * | 1987-06-30 | 1989-01-11 | Nec Corp | Variable constant type chirp signal generating circuit |
| WO2013094459A1 (en) * | 2011-12-19 | 2013-06-27 | 古野電気株式会社 | Direct digital synthesizer, reference frequency generation device, and sine wave output method |
| JPWO2013094459A1 (en) * | 2011-12-19 | 2015-04-27 | 古野電気株式会社 | Direct digital synthesizer, reference frequency generator, and sine wave output method |
| US9093996B2 (en) | 2011-12-19 | 2015-07-28 | Furuno Electric Company Limited | Direct digital synthesizer, reference frequency generating device, and sine wave outputting method |
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