JPS6045494U - Hybrid integrated circuit device - Google Patents

Hybrid integrated circuit device

Info

Publication number
JPS6045494U
JPS6045494U JP1983138195U JP13819583U JPS6045494U JP S6045494 U JPS6045494 U JP S6045494U JP 1983138195 U JP1983138195 U JP 1983138195U JP 13819583 U JP13819583 U JP 13819583U JP S6045494 U JPS6045494 U JP S6045494U
Authority
JP
Japan
Prior art keywords
integrated circuit
circuit device
hybrid integrated
heat dissipation
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1983138195U
Other languages
Japanese (ja)
Inventor
田島　恒宗
冨居　壱城
Original Assignee
ソニー株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ソニー株式会社 filed Critical ソニー株式会社
Priority to JP1983138195U priority Critical patent/JPS6045494U/en
Publication of JPS6045494U publication Critical patent/JPS6045494U/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
    • H01L2224/8592—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Cooling Or The Like Of Electrical Apparatus (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の混成集積回路装置の１例を示す断面図、
第２図は本考案の１実施例を示す断面図、第３゛図及び
第４図は他の実施例を示す断面図である。 １．２１は混成集積回路装置、４，３３は配線基板、５
は半導体素子、６は電子部品、７はケース、２２は放熱
板、２３は放熱基板、２５は半導体装置である。FIG. 1 is a sectional view showing an example of a conventional hybrid integrated circuit device.
FIG. 2 is a sectional view showing one embodiment of the present invention, and FIGS. 3 and 4 are sectional views showing other embodiments. 1.21 is a hybrid integrated circuit device, 4 and 33 are wiring boards, 5
1 is a semiconductor element, 6 is an electronic component, 7 is a case, 22 is a heat sink, 23 is a heat sink, and 25 is a semiconductor device.

Claims (1)

【実用新案登録請求の範囲】 １　放熱面を一方の面に有してモールドされた半導体装
置と他の電子部品と配線基板を備え、上記半導体装置が
上記放熱面を外部に開放した状態で一体に構成されてい
ることを特徴とする混成集積回路装置。 ２　複数の半導体装置の放熱面が配線基板の面と平行で
あり、且つ同一面に配されていることを特徴とする実用
新案登録請求の範囲第１項記載の混成集積回路装置。 ３　複数の半導体装置が基板に対して左右又は上下のい
ずれかについて略対称に配されていることを特徴とする
実用新案登録請求の範囲第１項又は第２項記載の混成集
積回路装置。[Claims for Utility Model Registration] 1. A semiconductor device molded with a heat dissipation surface on one side, other electronic components, and a wiring board, the semiconductor device being integrated with the heat dissipation surface open to the outside. A hybrid integrated circuit device comprising: 2. The hybrid integrated circuit device according to claim 1, wherein the heat dissipation surfaces of the plurality of semiconductor devices are parallel to and coplanar with the surface of the wiring board. 3. The hybrid integrated circuit device according to claim 1 or 2, wherein a plurality of semiconductor devices are arranged substantially symmetrically either horizontally or vertically with respect to the substrate.
JP1983138195U 1983-09-06 1983-09-06 Hybrid integrated circuit device Pending JPS6045494U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983138195U JPS6045494U (en) 1983-09-06 1983-09-06 Hybrid integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983138195U JPS6045494U (en) 1983-09-06 1983-09-06 Hybrid integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6045494U true JPS6045494U (en) 1985-03-30

Family

ID=30310158

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983138195U Pending JPS6045494U (en) 1983-09-06 1983-09-06 Hybrid integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6045494U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017154075A1 (en) * 2016-03-07 2017-09-14 三菱電機株式会社 Electronic control device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017154075A1 (en) * 2016-03-07 2017-09-14 三菱電機株式会社 Electronic control device
JPWO2017154075A1 (en) * 2016-03-07 2018-05-24 三菱電機株式会社 Electronic control unit
US10548213B2 (en) 2016-03-07 2020-01-28 Mitsubishi Electric Corporation Electronic controlling apparatus

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