JPS58182435U - External terminal structure of semiconductor devices - Google Patents

External terminal structure of semiconductor devices

Info

Publication number
JPS58182435U
JPS58182435U JP7843082U JP7843082U JPS58182435U JP S58182435 U JPS58182435 U JP S58182435U JP 7843082 U JP7843082 U JP 7843082U JP 7843082 U JP7843082 U JP 7843082U JP S58182435 U JPS58182435 U JP S58182435U
Authority
JP
Japan
Prior art keywords
external terminal
terminal structure
semiconductor devices
semiconductor device
materials
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7843082U
Other languages
Japanese (ja)
Inventor
義光 林
Original Assignee
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by セイコーエプソン株式会社 filed Critical セイコーエプソン株式会社
Priority to JP7843082U priority Critical patent/JPS58182435U/en
Publication of JPS58182435U publication Critical patent/JPS58182435U/en
Pending legal-status Critical Current

Links

Landscapes

  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は従来の方法の断面図である。 第３図は本考案の一実施例の断面図。第４図、第５図は
、本考案の一実施例の具体的な実装方法を説明した断面
図。第６図は本考案の他の実施例。 １．６・・・・・・従来の外付は端子、２・・・・・・
半導体素子、′３・・・・・・半導体素子を実装する基
板、４．７・・・・・・基板に設けられた配線パターン
、５・・・・・・外付は端子を半田付けする半田、８，
９．１１・・・・・・本考案の外付は端子、１０・・・
・・・外付は端子半田付は用のクリーム半田。1 and 2 are cross-sectional views of the conventional method. FIG. 3 is a sectional view of one embodiment of the present invention. 4 and 5 are cross-sectional views illustrating a specific mounting method of an embodiment of the present invention. FIG. 6 shows another embodiment of the present invention. 1.6... Conventional external terminals, 2...
Semiconductor element, '3... Board on which the semiconductor element is mounted, 4.7... Wiring pattern provided on the board, 5... Soldering external terminals. Handa, 8,
9.11...The external connection of this invention is the terminal, 10...
...For external terminal soldering, use cream solder.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外付は端子を有する半導体素子に於いて、前記外付は端
子は、熱膨張係数の異なる数種類の材料の積層板である
事を特徴とする半導体素子の外付は端子構造。A semiconductor device having an external terminal structure, wherein the external terminal is a laminate made of several kinds of materials having different coefficients of thermal expansion.
JP7843082U 1982-05-28 1982-05-28 External terminal structure of semiconductor devices Pending JPS58182435U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7843082U JPS58182435U (en) 1982-05-28 1982-05-28 External terminal structure of semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7843082U JPS58182435U (en) 1982-05-28 1982-05-28 External terminal structure of semiconductor devices

Publications (1)

Publication Number Publication Date
JPS58182435U true JPS58182435U (en) 1983-12-05

Family

ID=30087637

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7843082U Pending JPS58182435U (en) 1982-05-28 1982-05-28 External terminal structure of semiconductor devices

Country Status (1)

Country Link
JP (1) JPS58182435U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60206056A (en) * 1984-03-29 1985-10-17 Fujitsu Ltd Lead terminal structure of electronic component

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5462782A (en) * 1977-10-27 1979-05-21 Sharp Corp Package method of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5462782A (en) * 1977-10-27 1979-05-21 Sharp Corp Package method of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60206056A (en) * 1984-03-29 1985-10-17 Fujitsu Ltd Lead terminal structure of electronic component

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