JPS604245A - 半導体装置 - Google Patents
半導体装置Info
- Publication number
- JPS604245A JPS604245A JP58112042A JP11204283A JPS604245A JP S604245 A JPS604245 A JP S604245A JP 58112042 A JP58112042 A JP 58112042A JP 11204283 A JP11204283 A JP 11204283A JP S604245 A JPS604245 A JP S604245A
- Authority
- JP
- Japan
- Prior art keywords
- wires
- element mounting
- excess
- connection
- gold
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
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Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
め要約のデータは記録されません。
Description
【発明の詳細な説明】
本発明は、素子搭載部と外部導出用リード線とが連結さ
れているリードフレームを使用した半導体装置の改良さ
れた構造に関するものである。
れているリードフレームを使用した半導体装置の改良さ
れた構造に関するものである。
従来この種の半導体装置において、素子を固着する場合
に2つの方法があった。1つは素子のシリコンと素子搭
載部の金メッキと金共晶合金化させる方法、他の方法は
銀ペースト等の接着材料を素子と素子搭載部との間に介
在させて接着させる方法である。このいずれの方法にお
いても次のような欠点があった。
に2つの方法があった。1つは素子のシリコンと素子搭
載部の金メッキと金共晶合金化させる方法、他の方法は
銀ペースト等の接着材料を素子と素子搭載部との間に介
在させて接着させる方法である。このいずれの方法にお
いても次のような欠点があった。
共晶合金化させる方法においては、通常素子塔載部を金
とシリコンの共晶点の温度(約490C)まで加熱して
おき、その上に素子をのせ、該素子を該搭載部の上に数
秒間こすり合わせることにより共晶合金を作るのである
。この時に共晶合金が出き過ぎると、その過剰の共晶合
金物が該塔載部と外部導出用リード線(以下リード線と
称する)との連結部を通して外へ流出していくことがあ
った。この素子固着時の余剰流出物が該リード線の金属
細線との接続部に達すると通常金又は銀メッキされた該
接続部の表面が該余剰流出物である金−シリコンの共晶
合金で覆われ、該接続部に金、又はアルミニウムの金属
細線を熱圧着することが出来なくなる結果となっていた
。
とシリコンの共晶点の温度(約490C)まで加熱して
おき、その上に素子をのせ、該素子を該搭載部の上に数
秒間こすり合わせることにより共晶合金を作るのである
。この時に共晶合金が出き過ぎると、その過剰の共晶合
金物が該塔載部と外部導出用リード線(以下リード線と
称する)との連結部を通して外へ流出していくことがあ
った。この素子固着時の余剰流出物が該リード線の金属
細線との接続部に達すると通常金又は銀メッキされた該
接続部の表面が該余剰流出物である金−シリコンの共晶
合金で覆われ、該接続部に金、又はアルミニウムの金属
細線を熱圧着することが出来なくなる結果となっていた
。
又、接着材料を用いて接着させる方法に分いては、接着
材料を素子搭載部に塗布した後その上に素子を置き、接
着材料を加熱又は紫外線により硬化処理を行ない素子を
固着していた。接着材料の主成分は樹脂であり、その中
に含まれている溶剤外が硬化するまでは、液状のままで
ある為、塔載部に塗布する量が多すぎると素子搭載に塗
布されたあと、素子搭載部とリード線の連結部を通して
外へ流出していくことがあった。特に素子搭細部、リー
ド線及び連結部上のメッキ表面が粗い場合、毛管現象に
よりその流出効果が大きかった。
材料を素子搭載部に塗布した後その上に素子を置き、接
着材料を加熱又は紫外線により硬化処理を行ない素子を
固着していた。接着材料の主成分は樹脂であり、その中
に含まれている溶剤外が硬化するまでは、液状のままで
ある為、塔載部に塗布する量が多すぎると素子搭載に塗
布されたあと、素子搭載部とリード線の連結部を通して
外へ流出していくことがあった。特に素子搭細部、リー
ド線及び連結部上のメッキ表面が粗い場合、毛管現象に
よりその流出効果が大きかった。
この素子固着時の余剰流出物が、通常金又は銀メッキさ
れたリード線の金属流出物との接続部に達すると該余剰
流出物である樹脂の薄膜で覆われ、該接続部に金又はア
ルミニウムの細線を熱圧着することが出来なくなる結果
となっていた。
れたリード線の金属流出物との接続部に達すると該余剰
流出物である樹脂の薄膜で覆われ、該接続部に金又はア
ルミニウムの細線を熱圧着することが出来なくなる結果
となっていた。
以上述べた如く、素子を素子搭載部に固着する時に発生
する余剰流出物が素子搭載部とリード線との連結部を通
してリード線の金属細線との接続部にまで達し表面を覆
ってしまう為、金属細線を該接部に接続することが出来
なくなるか、接続した如くに見えても接続強度が極めて
弱く、品質低下を招く欠点を有していた。
する余剰流出物が素子搭載部とリード線との連結部を通
してリード線の金属細線との接続部にまで達し表面を覆
ってしまう為、金属細線を該接部に接続することが出来
なくなるか、接続した如くに見えても接続強度が極めて
弱く、品質低下を招く欠点を有していた。
本発明の目的は、これらの点を解決し高信頼性で安価な
半導体装置を提供するものである。
半導体装置を提供するものである。
本発明は半導体装置の半導体素子搭載部と外部導出用リ
ード線とが連結されている部分において該搭載部と該リ
ード線の金属細線との接続部の問で突起物が連結部を横
断していることを特徴とする。
ード線とが連結されている部分において該搭載部と該リ
ード線の金属細線との接続部の問で突起物が連結部を横
断していることを特徴とする。
以下図面にもとづいて本発明の説明する。
第1(a)は従来の半導体装置を示す反面図、第1図(
b),(c)は各々第1図(a)のA−A′を切断した
段面図である。半導体素子101a、101bを素子搭
載部102a、102bに金・シリコンの提供合金又は
銀ペースト等の接着剤103bで固着した後、該素子の
電極104a、104bと金5又は銀のメッキ層105
bで覆われたリード線106a、106bとを金又はア
ルミニウムの細線107a、107bで接続する。しか
しながら、該共晶合金又は銀ペースト等の接着剤103
cはその量が過剰となった場合、素子101cと素子搭
載部102cを固着する時に該搭載部12cとリード線
106cとの間の連結部108cを通して外へ流出して
行き、リード線106cの金属細線との接続部109c
の金又は銀メッキ層105cの上を覆うことがあった。
b),(c)は各々第1図(a)のA−A′を切断した
段面図である。半導体素子101a、101bを素子搭
載部102a、102bに金・シリコンの提供合金又は
銀ペースト等の接着剤103bで固着した後、該素子の
電極104a、104bと金5又は銀のメッキ層105
bで覆われたリード線106a、106bとを金又はア
ルミニウムの細線107a、107bで接続する。しか
しながら、該共晶合金又は銀ペースト等の接着剤103
cはその量が過剰となった場合、素子101cと素子搭
載部102cを固着する時に該搭載部12cとリード線
106cとの間の連結部108cを通して外へ流出して
行き、リード線106cの金属細線との接続部109c
の金又は銀メッキ層105cの上を覆うことがあった。
この余剰流出物110cの上に金属細線107cを熱圧
着しても、接続不可となるか又は接続強度極めて弱く、
品質低下を招くという欠点を有していた。
着しても、接続不可となるか又は接続強度極めて弱く、
品質低下を招くという欠点を有していた。
第2図(a)、(b)は本発明による一実施例を示す図
である。第2図(a)は平面図、第2図(b)は(a)
図のB−B′を切断した断面図である。
である。第2図(a)は平面図、第2図(b)は(a)
図のB−B′を切断した断面図である。
半導体素子201a、201bを素子搭載部202a,
202bに、金・シリコンの共晶合金又は銀ペースト等
の接着材203bで固着した後、この余剰流出物210
bが外へ流出しようとするが突起物211a,211b
に妨げられて流出出きなくなる。この突起物は、ソルダ
ーレジスト、シリコーン樹脂、ポリイミド樹脂等、(こ
の後の工程において変化しないものが望ましいが、とく
にこだわらなくとも良い)で構成され、素子を固着する
までに素子搭載部202a、202bとリード線の金属
細線との接続に設けられる。材料は特に上述したものに
限らず、金属セラミックスガラス等何でもよく、又その
複合品でも良いことは言うまでもないことである。
202bに、金・シリコンの共晶合金又は銀ペースト等
の接着材203bで固着した後、この余剰流出物210
bが外へ流出しようとするが突起物211a,211b
に妨げられて流出出きなくなる。この突起物は、ソルダ
ーレジスト、シリコーン樹脂、ポリイミド樹脂等、(こ
の後の工程において変化しないものが望ましいが、とく
にこだわらなくとも良い)で構成され、素子を固着する
までに素子搭載部202a、202bとリード線の金属
細線との接続に設けられる。材料は特に上述したものに
限らず、金属セラミックスガラス等何でもよく、又その
複合品でも良いことは言うまでもないことである。
この突起物の存庄により、リード線206a、206b
の金属細線との接続部209a、209bにおけるその
金又は銀メッキ層205bが、汚されることなく、金又
はアルミニウムの金属線207a,207bを確実に熱
圧着でき、高品質を維持できることになった。該突起物
は該連結部を完全に横断しないでもよく、連結部の一部
分にあっても又、リード線の金属細線との接続部の周囲
をかこむような形状であっても本発明の効果は全く変わ
らないことは言うまでもないことである。
の金属細線との接続部209a、209bにおけるその
金又は銀メッキ層205bが、汚されることなく、金又
はアルミニウムの金属線207a,207bを確実に熱
圧着でき、高品質を維持できることになった。該突起物
は該連結部を完全に横断しないでもよく、連結部の一部
分にあっても又、リード線の金属細線との接続部の周囲
をかこむような形状であっても本発明の効果は全く変わ
らないことは言うまでもないことである。
以上説明したように本発明によれば素子と素子搭載部と
の固着時に発生する余剰流出物の影響をうけずに金属細
線とリード線とを接続出き、安価で信頼性の高い半導体
装置を提供するものである。
の固着時に発生する余剰流出物の影響をうけずに金属細
線とリード線とを接続出き、安価で信頼性の高い半導体
装置を提供するものである。
第1図(a)〜(c)は各々従来の半導体装置を示した
図で第1図(a)は平面図、第1図(b)、(c)は各
々第1図(a)のA−A′を切断した断面図、第2図(
a)、(b)は各々本発明の実施例を示した図で第2図
(a)は平面図、第2図(b)は第2図(a)のB−B
′を切断した断面図である。 なお図において、101a、101b、101c、20
1a、201b・・・・・・半導体素子、102a、1
02b、102c、202a、202b・・・・・・素
子搭載部、103b、103c、203b・・・・・・
金・シリコン共晶合金又は銀ペースト等の接着材、10
4a、104b、104c、204a、204b・・・
・・・素子の電極、105b、105c、205b・・
・・・・金又は銀のメッキ層、106a、106b、1
06c、206a,206b・・・・・・リード線、1
07a、107b、107c、207a,207b・・
・・・・金属細線、108a、108b、108c、2
08a、208b・・・・・・連結部、109a、10
9b、109c、209a,209c・・・・・・金属
細線の接続部、110c、21Ob・・・・・・余剰流
出物、211a、211b・・・・・・突起物、である
。
図で第1図(a)は平面図、第1図(b)、(c)は各
々第1図(a)のA−A′を切断した断面図、第2図(
a)、(b)は各々本発明の実施例を示した図で第2図
(a)は平面図、第2図(b)は第2図(a)のB−B
′を切断した断面図である。 なお図において、101a、101b、101c、20
1a、201b・・・・・・半導体素子、102a、1
02b、102c、202a、202b・・・・・・素
子搭載部、103b、103c、203b・・・・・・
金・シリコン共晶合金又は銀ペースト等の接着材、10
4a、104b、104c、204a、204b・・・
・・・素子の電極、105b、105c、205b・・
・・・・金又は銀のメッキ層、106a、106b、1
06c、206a,206b・・・・・・リード線、1
07a、107b、107c、207a,207b・・
・・・・金属細線、108a、108b、108c、2
08a、208b・・・・・・連結部、109a、10
9b、109c、209a,209c・・・・・・金属
細線の接続部、110c、21Ob・・・・・・余剰流
出物、211a、211b・・・・・・突起物、である
。
Claims (1)
- 半導体素子と、該半導体素子を固着する素子塔載部と、
該素子搭載部に連結した外部導出用リードとを有する半
導体装置において、該素子搭載部と該外部導出部リード
とが連結されている部分の近傍に突起が設けられている
ことを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58112042A JPS604245A (ja) | 1983-06-22 | 1983-06-22 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58112042A JPS604245A (ja) | 1983-06-22 | 1983-06-22 | 半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS604245A true JPS604245A (ja) | 1985-01-10 |
Family
ID=14576556
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58112042A Pending JPS604245A (ja) | 1983-06-22 | 1983-06-22 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS604245A (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991014282A1 (en) * | 1990-03-15 | 1991-09-19 | Fujitsu Limited | Semiconductor device having a plurality of chips |
US5530292A (en) * | 1990-03-15 | 1996-06-25 | Fujitsu Limited | Semiconductor device having a plurality of chips |
JP2008066553A (ja) * | 2006-09-08 | 2008-03-21 | Furukawa Electric Co Ltd:The | 半導体装置 |
-
1983
- 1983-06-22 JP JP58112042A patent/JPS604245A/ja active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1991014282A1 (en) * | 1990-03-15 | 1991-09-19 | Fujitsu Limited | Semiconductor device having a plurality of chips |
US5463253A (en) * | 1990-03-15 | 1995-10-31 | Fujitsu Limited | Semiconductor device having a plurality of chips |
US5530292A (en) * | 1990-03-15 | 1996-06-25 | Fujitsu Limited | Semiconductor device having a plurality of chips |
JP2008066553A (ja) * | 2006-09-08 | 2008-03-21 | Furukawa Electric Co Ltd:The | 半導体装置 |
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