JPS6038944A - Timing extraction circuit - Google Patents
Timing extraction circuitInfo
- Publication number
- JPS6038944A JPS6038944A JP58146954A JP14695483A JPS6038944A JP S6038944 A JPS6038944 A JP S6038944A JP 58146954 A JP58146954 A JP 58146954A JP 14695483 A JP14695483 A JP 14695483A JP S6038944 A JPS6038944 A JP S6038944A
- Authority
- JP
- Japan
- Prior art keywords
- code
- gate
- signal
- inputted
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Dc Digital Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
＋１１ 発明の技術分野
本発明は、モディファイドＤＭＩ符号（以下逼Ｍ−ＤＭ
Ｉ符号と略す）からタイミング成分を抽出するタイミン
グ抽出回路に関するものである。Detailed Description of the Invention +11 Technical Field of the Invention The present invention relates to a modified DMI code (hereinafter referred to as 〼M-DM
The present invention relates to a timing extraction circuit that extracts a timing component from an I code (abbreviated as I code).
（２）技術の背影
従来から、データを伝送する場合、同一符号が連続しな
い様にするためＤＭＩ符号が用いられている。(2) Background of the technology Conventionally, when transmitting data, DMI codes have been used to prevent the same code from appearing consecutively.
このＤＭＩ符号は、第１図（ａ）に示す様に、°１１°
１を伝送する時は°’００”、”１１°゛を交互に出力
し、０“を伝送する時は、前のビットが１′００“の時
は１０１°を、°１１１°１の時には０１’“を出力す
る機にしている。This DMI code is 11° as shown in Figure 1(a).
When transmitting 1, outputs °'00" and "11°"alternately; when transmitting 0, outputs 101° when the previous bit is 1'00", and outputs 101° when the previous bit is °111°1. The machine is designed to output 01'".
ところが、この符号では例えば、伝送信号として、ＩＩ
ＯＩ＋が連続した場合、同じ符号が連続し、°′１０
°′の連続か°°６１°゛の連続かの判定ができなくな
り°１１°゛が次に伝送された場合に復号化を誤まる欠
点がある。However, with this code, for example, II
When OI+ is consecutive, the same sign is consecutive and °'10
There is a drawback that it is impossible to determine whether it is a continuation of °' or a continuation of °61°, resulting in incorrect decoding when °11° is transmitted next.
そこで、（ｂ）図に示す様ｌこ、伝送符号１＋ ＯＩＩ
を符号化した時のタイムスロット中央部におけるｌ’を
極性変化点を＃≠中津だけ前方ヘシフトさせたＭ−ＤＭ
Ｉ符号が考えられた。Therefore, as shown in figure (b), transmission code 1 + OII
M-DM in which the polarity change point of l' at the center of the time slot is shifted forward by #≠Nakatsu when encoding
I code was considered.
ところが、第１図かられかる仔に、（ｃ）図に示す抽出
すべきタイミング成分（デジーティ比が５０チ）とＤｔ
Ｉ符号とは立上り、立下シの点の位相が一致しているが
、Ｍ−ＤＭＩ符号では位相シフトした所が一致しない。However, the timing component to be extracted (the digity ratio is 50chi) and Dt shown in FIG.
The rising and falling points of the I code match in phase, but the M-DMI code does not match at the phase shift.
従ってＭ−ＤＭＩ符号では、単に立上り、立下シを検出
しただけでは、タイミング成分が抽出できない欠点があ
る。Therefore, the M-DMI code has the drawback that timing components cannot be extracted by simply detecting rising and falling edges.
（３）発明の目的
本発明は、この様な点１こ鑑みてなされたものでＭ−Ｄ
ＭＩ祠号から、第１図（ｃ）に示す如くタイミング成分
を抽出することを目的とする。(3) Purpose of the Invention The present invention has been made in view of the above points.
The purpose is to extract the timing component from the MI shrine as shown in FIG. 1(c).
（４）発明の構成
上記目的は、本発明によれば、モディファイドＤＭＩ符
号からタイミング成分を抽出するタイミング抽出回路ζ
こおいて、該モディファイドＤＭＩ符号の正規位相部分
での立上やと立下りをおのおの検出する立上り検出部、
立下シ検出部、該立上り検出部と立下り検出部出力を合
成することにょシタイミング成分を出力する合成部とを
有することを物像とするタイミング抽出回路によって達
成される。(4) Structure of the Invention According to the present invention, the above object is a timing extraction circuit ζ that extracts a timing component from a modified DMI code.
Here, a rising edge detection unit detects each rising edge and falling edge in the normal phase portion of the modified DMI code;
This is achieved by a timing extraction circuit that essentially includes a falling edge detection section and a synthesis section that synthesizes the outputs of the rise detection section and the fall detection section and outputs a timing component.
（５）発明の実施例 以下本発明を実施例に基づいて説明する。(5) Examples of the invention The present invention will be explained below based on examples.
第２図は本発明の実施例を、第３図はそのタイムチャー
トを示す。FIG. 2 shows an embodiment of the present invention, and FIG. 3 shows its time chart.
図中、ＦＦは遅延型フリップフロップ（以下Ｄ−ＦＦと
略す）、ＩＮＶはインバータ、ＡＮＩ〜ＡＮ３はアンド
ゲート、Ｇはゲート、ＯＲはオアゲート、ＮＯｒ心はノ
アゲート、Ｃ，、Ｃ，はコンデンサ、Ｒ，、Ｒ２は抵抗
、Ｔはタンク回路である。又第３図におりる■〜０は第
２図の■〜Ｏにおける波形を示している・
以下図の動作をｒｘｓ ３図を用いて説明する。In the figure, FF is a delay type flip-flop (hereinafter abbreviated as D-FF), INV is an inverter, ANI to AN3 are AND gates, G is a gate, OR is an OR gate, NOr is a NOR gate, C, , C are capacitors, R, , R2 are resistors, and T is a tank circuit. Also, ■~0 in FIG. 3 shows the waveforms at ■~O in FIG. 2. The operation shown in the figure will be explained below using the rxs diagram 3.
入力端子１１こ、Ｍ −Ｄ Ｍ Ｉ符号■（第３図■）
が入力すると、このＭ−ＤＭＩ符号のはインバータＩＮ
ＶＩこより反転されて、抵抗Ｒ，、コンデンサＣＩ よ
り成る積分回路により積分されて（第３図■）アンドゲ
ートＡＮ１の一方に入力する。Input terminal 11, M-DM I code (Fig. 3)
is input, this M-DMI code is inverter IN
It is inverted from VI, integrated by an integrating circuit consisting of resistors R and capacitor CI (FIG. 3), and inputted to one side of AND gate AN1.
アンドゲートＡＮ１の他方にはＭ−ＤＭＩ符号が直接入
力するので、アンドゲートＡＮ１からは両者の論理積出
力■が得られる。Since the M-DMI code is directly inputted to the other side of the AND gate AN1, the AND gate AN1 obtains the AND output of the two.
この論理積出力■はアンドゲートＡ Ｎ’ ２の一方に
入力し、他方に（ｊインバータＩＮＶ出力■を、抵抗Ｒ
７、コンデンサＣ７ｌこより積分した信号■′をしきい
値ＴＨでスライスした信号が入力される。This AND output ■ is input to one side of the AND gate A N' 2, and the other side (j inverter INV output ■ is input to the resistor R
7. A signal obtained by slicing the integrated signal ``■'' by the threshold value TH from the capacitor C7l is input.
従ってアンドゲートＡＮ２からは、Ｍ−ＤＭＩ符号の位
相シフトしていない正規位相部（Ｏ印を付与した部分）
の立上シを示す（ｍ号■が出方される。Therefore, from the AND gate AN2, the normal phase part of the M-DMI code that is not phase-shifted (the part marked with O)
Indicates the start-up of (m number ■ is displayed).
一方正規位相部の立下９（０印を＋ｔ−Ｉ：ｊ、した部
分）の検出のために以下の動作が行なわれる。On the other hand, the following operation is performed to detect the falling edge 9 of the normal phase portion (the portion where the 0 mark is +t-I:j).
Ｍ−ＤＭＩ省ｆ号のとＭ分信号■がノアゲートＮ０ＲＪ
こ入力し、ノアゲートからＭ−ＤＭＩイ、１号■の立下
りを示す信号■が出力される。M-DMI Ministry f and M minute signal ■ are Noah Gate N0RJ
When this is input, a signal (2) indicating the fall of M-DMI (1) and (1) is output from the NOR gate.
更にこの信号■と、ゲートＧからの情−杉のの論理積が
アンドゲートＡＮ３でとられ、正Ｍｍ相部の立下シを示
す４バ号■が得られる。Furthermore, the AND gate AN3 performs a logical product of this signal (2) and the signal (2) from the gate G to obtain a 4-bar signal (2) indicating the falling edge of the positive Mm phase.
そして信号■と信号■をオアゲートＯＲを通した出力■
をタンク回路Ｔｌこ入力し、このタンク回路Ｔからタイ
ミング成分■を出方する。Then output the signal ■ and signal ■ through the OR gate OR.
is input to the tank circuit Tl, and the timing component (2) is output from this tank circuit T.
（６）発明の効果
以上の如く、本発明によればＭ−ＤＭＩ符月において、
デユーティ比が一定なタイミング成分を抽出することが
できる。(6) Effects of the invention As described above, according to the present invention, in the M-DMI sign month,
Timing components with a constant duty ratio can be extracted.
第１図はＤＭＩ符号、Ｍ−ＤＭＩ符号の説、明及びタイ
ミング成分との関係を示す図、第２図は本発明の実施例
を示す図、第３図はその動作タイムチャートである。
図中ＩＮＶはインバータ、Ｒｔ 、’ Ｒｔは抵抗、Ｃ
，、Ｃ，はコンデンサ、ＡＮＩ〜ＡＮ３はアンドゲート
、Ｇはゲート、ＯＲゲート、ＮＯＲはノアゲート、Ｔは
タンク回路である。
”／” ”０” ” ０ ” ” ／ ” ”０“第２
図FIG. 1 is a diagram showing an explanation of the DMI code and M-DMI code and their relationship with timing components, FIG. 2 is a diagram showing an embodiment of the present invention, and FIG. 3 is an operation time chart thereof. In the figure, INV is an inverter, Rt is a resistance, C
,,C, are capacitors, ANI to AN3 are AND gates, G is a gate, OR gate, NOR is a NOR gate, and T is a tank circuit. ”/” “0” “0” “/” “0” 2nd
figure
Claims (1)
るタイミング抽出回路において、該モディファイドＤＭ
Ｉ符号の正規位相部分での立上りと立下りをおのおの検
出する立上り検出部、立下り検出部、該立上シ検出部と
立下り検出部出力を合成することによシタイミング成分
を出力する合成部とを有することを特徴とするタイミン
グ抽出回路。In a timing extraction circuit that extracts a timing component from a modified DMI code, the modified DM
A rising detection section and a falling detection section that respectively detect the rising and falling edges in the normal phase portion of the I code, and a synthesis section that outputs a timing component by combining the outputs of the rising and falling detecting sections. A timing extraction circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58146954A JPS6038944A (en) | 1983-08-11 | 1983-08-11 | Timing extraction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58146954A JPS6038944A (en) | 1983-08-11 | 1983-08-11 | Timing extraction circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6038944A true JPS6038944A (en) | 1985-02-28 |
Family
ID=15419330
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58146954A Pending JPS6038944A (en) | 1983-08-11 | 1983-08-11 | Timing extraction circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6038944A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02209035A (en) * | 1989-02-09 | 1990-08-20 | Nec Corp | Clock extraction circuit |
-
1983
- 1983-08-11 JP JP58146954A patent/JPS6038944A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02209035A (en) * | 1989-02-09 | 1990-08-20 | Nec Corp | Clock extraction circuit |
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