JPS6037784A - Field effect transistor - Google Patents
Field effect transistorInfo
- Publication number
- JPS6037784A JPS6037784A JP14720583A JP14720583A JPS6037784A JP S6037784 A JPS6037784 A JP S6037784A JP 14720583 A JP14720583 A JP 14720583A JP 14720583 A JP14720583 A JP 14720583A JP S6037784 A JPS6037784 A JP S6037784A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- gate
- electrode
- source
- active layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 15
- 150000001875 compounds Chemical class 0.000 claims abstract description 14
- 238000005530 etching Methods 0.000 abstract description 4
- 239000000758 substrate Substances 0.000 abstract description 4
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 3
- 125000006850 spacer group Chemical group 0.000 abstract description 3
- 238000005275 alloying Methods 0.000 abstract description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 abstract 1
- 230000004888 barrier function Effects 0.000 abstract 1
- 238000002347 injection Methods 0.000 abstract 1
- 239000007924 injection Substances 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 241000251468 Actinopterygii Species 0.000 description 1
- -1 GaSb Chemical class 0.000 description 1
- 229910005542 GaSb Inorganic materials 0.000 description 1
- 241000234435 Lilium Species 0.000 description 1
- MMOXZBCLCQITDF-UHFFFAOYSA-N N,N-diethyl-m-toluamide Chemical compound CCN(CC)C(=O)C1=CC=CC(C)=C1 MMOXZBCLCQITDF-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 description 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000004401 flow injection analysis Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/812—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a Schottky gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
- H01L29/201—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys
- H01L29/205—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds including two or more compounds, e.g. alloys in different semiconductor regions, e.g. heterojunctions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
Description
【発明の詳細な説明】 産業ヒのy、1川分野 本発明は1稚界グj1果型トうフジスタに関する。[Detailed description of the invention] Industry Hi, 1 river field TECHNICAL FIELD The present invention relates to a fruit type Tofujista.
従来例の構成とその問題点
III −V族化合物半2n体は、SlやCyeなどの
■旌単体元素の半導体に比べで高い移動度を有し、また
材木St的には容易にシヨ・リド牛−バリアゲート構造
が得られるため、(・7れ1こ高周波特性を持つNET
材料として研究開発が進められている。更に、111−
V族化合物半導体てはSiやGeてイアにくかつ1こ半
絶縁性の結晶が容易に得られるため、集積苧バイスの材
料として注目を集めている・−
第1図はIII −V族化合物半導体に」こる従来のシ
ョ・ソト士−パリアゲート型FETの(’i+71′、
□1tを示す。′″1′約1′基板(])にに無添加の
i型バ・ソファ層(2)を介して活性n(3)を裁置し
、その−ににFETを構成するドレイン電極(4)、グ
ー1〜鋸極(5)、ソース電極(ハの各種電極が形成さ
れている。(6)はスペーサSi3N4である。図中の
ゲート、ソース直列抵抗R8の存在はFETのチセネル
コンタクタンスy271を’ 14− Rs 、ym”
ymと低下さぜる。まtこゲート容fi ccs と共
に偵う−(回路を形成して伝達速度も低下させる。1<
5を小さくするtこめには、活性層(3)の抵抗率が低
いものを使用すれば良いか、FTL1’を動作させる場
合に必要なショ・リド士−バリアノf−ト〔以下、 M
ESと称す〕の逆耐圧が抵抗率に比例するfコめ、いず
れかが!、1性になる。従来では、n = I X 1
017cm ”のn型GaAsを活性層としt、:場合
、ゲート耐圧は15ボルトとなりFET動作域としては
満足できる値きなるが、抵統率はρ5= 0.02Ω−
cmとなりブセネルコンタクタンスは本来の14程度に
なってしまうことが計算によりイ)かる・活性11?l
の士Pリア濃度が一定で、Rsが低減する試みとしては
リセス構造がよく用いられる。第1図もその例である。Structure of the conventional example and its problems III-V group compound semi-2n semiconductors have higher mobility than semiconductors of single element elements such as Sl and Cye, and are easily used for lumber storage. Because a cow-barrier gate structure is obtained, (7 and 1 are NETs with high frequency characteristics
Research and development is underway as a material. Furthermore, 111-
Group V compound semiconductors are attracting attention as materials for integrated vices because they are resistant to Si and Ge and semi-insulating crystals can be easily obtained. Figure 1 shows III-V compound semiconductors. ('i+71',
□Indicates 1t. An active n(3) is placed on a substrate (]) through an additive-free i-type bath layer (2), and a drain electrode (4) constituting an FET is placed on the substrate (2). ), saw electrodes (5), and source electrodes (various electrodes (C) are formed. (6) is a spacer Si3N4. The presence of gate and source series resistance R8 in the figure indicates the FET's chisenel contactor. '14-Rs, ym''
It decreases with ym. - (form a circuit and also reduce the transmission speed. 1 <
In order to reduce the value of 5, it would be better to use an active layer (3) with a low resistivity.
The reverse breakdown voltage of ES (referred to as ES) is proportional to resistivity. , becomes monosexual. Conventionally, n = I x 1
017 cm'' with n-type GaAs as the active layer, the gate breakdown voltage is 15 volts, which is a value that is satisfactory for the FET operating range, but the resistivity is ρ5 = 0.02 Ω-
cm, and the Busenel contactance is calculated to be about 14, which is the original value.A) Karu・Activity 11? l
A recessed structure is often used as an attempt to reduce Rs while keeping the P rear concentration constant. FIG. 1 is also an example.
しかし、この構造はノf−ト111下の半導体層の工・
リチシクが不可欠でチ1フネル厚さ[の制御かう!IC
シい。特にノーマリオフ型MES−FETは活性層(3
)が前記n=lX1017cm−3の+セリア濃度の場
合、t−800λではノーマリオフ型となるが、900
Aを越えるとノーマリオン型となる。リセス構造を採用
する限り、このような微少量の工・リチシタ11・制御
はプロセス上灯しく、再現性よくノーマリオフ特性を得
ることは、θツト間は言うに及ばず、Dット内、1ウ工
ハ面内でも困Iず゛「な問題であった。However, this structure is not suitable for the semiconductor layer under the note 111.
It is essential to control the thickness of the film! IC
Yes. In particular, the normally-off MES-FET has an active layer (3
) is the + ceria concentration of n=lX1017cm-3, it becomes normally off type at t-800λ, but
If it exceeds A, it becomes normally on type. As long as a recessed structure is adopted, such small amounts of processing, reticulation, and control are useful in the process, and it is possible to obtain normally-off characteristics with good reproducibility not only between θ but also within D and 1. This was a very difficult problem within the U.S. engineering field.
発明の目的
本発明は再現性よ< MES・FET特性を実現し、か
つ1セ、をほとんど零にし、従って9m が高く、高速
動作が可能な’r7を界効果型トラスジスタを提供する
ことを目的とする。Purpose of the Invention The purpose of the present invention is to provide a field-effect transistor which achieves reproducibility and MES/FET characteristics, reduces 1s to almost zero, and therefore has a high 9m range and is capable of high-speed operation. shall be.
発明の構成
本発明の可算効果型トランジスタは、第1の11(−V
族化合物半導体からFV、る活性層と、この活性層とシ
ヨ・シト+−バリア接合を形成するゲート電極と、前記
活性層上に削設されると共に第1のlr[−V族化合物
半導体とは異なる第2のIII −V族化合物半導体か
ら成るソースおよびドしイン電極とを設けtこことを特
徴とする。Structure of the Invention The countable effect transistor of the present invention has a first 11(-V
an active layer made of a FV group compound semiconductor; a gate electrode forming a side-to-barrier junction with the active layer; and a first lr[-V group compound semiconductor and is characterized by providing source and drain electrodes made of a different second group III-V compound semiconductor.
実施例の説明 以下、本発明の一実施例を第2図に基づいて説明する。Description of examples Hereinafter, one embodiment of the present invention will be described based on FIG. 2.
第2図は本発明によるFiζTの慴造図七分府層を示す
。半絶縁性1nP lr(:板θ()上にi型1nPバ
・ソファ層Onを1.07/7+1の厚さに設け、その
」二にnfi、1JIn O,53GaO,47AS活
性F1(+2を800λ、n生型I nP n’l f
E T’l (11を2000Aそれぞれ成長する。成
長は膜1−(制御の容易なMBE法、NtocvD法な
どを用いるが、本実施例ではMBE法により成長を行な
った。]、(仮温度は500℃Gaセル温度1100”
C,Inセル温度1200℃、As t IL+温度2
50°c、p、cル潟度250 ”Cとし、n型不に、
−ロ物。FIG. 2 shows the seven-layer structure of FiζT according to the present invention. An i-type 1nP bath layer On with a thickness of 1.07/7+1 is provided on the semi-insulating 1nP lr(: plate θ(), and then nfi, 1JInO, 53GaO, 47AS active F1(+2) 800λ, n live type I nP n'l f
E T'l (11 is grown at 2000A each. The growth is performed using the MBE method, NtocvD method, etc., which are easy to control. In this example, the growth was performed by the MBE method.), (The temporary temperature was 500℃Ga cell temperature 1100''
C, In cell temperature 1200℃, As t IL + temperature 2
50°c, p, c 250"C, non-n type,
-Ro things.
としてはSnを使い、セル温度は780℃としtこ。パ
・ソファ層θυ、活性JrR(ハ)、電極層09の各層
の成長時間はそれぞれ1時間、6分、5分であった。ド
レイン・ソースへの哄#襖赤なヌtf!、流注入用]ン
タクトとじてはそれぞれAuGeNi/Au膜+1/l
) a6を蒸着し−c tu 極層((艷と1−ミ・ツ
ク接触を吉るtこめに合金化熱処理を行なう。グーr−
rrr<分はスペーサSi3N4膜O乃に形成した開孔
部を力6して電極層(13の工・ソチンクを行なう。エ
ツチング液としてはIC7/H20液を用いtこ。この
工・リチンジ液によりIno。sa Ga O,47A
sとInPとの選択工tリチシクが可能であるので、■
・リチンクは活性層(1′2とn工極盾(1ニルとの界
面で停止する。Sn was used as the material, and the cell temperature was set to 780°C. The growth times for each layer, ie, the Pa-sofa layer θυ, the active JrR (c), and the electrode layer 09, were 1 hour, 6 minutes, and 5 minutes, respectively. A song to the drain source #fusuma red Nutf! , for flow injection] AuGeNi/Au film + 1/l for each contact
) A6 is vapor deposited and alloying heat treatment is carried out to ensure good contact with the pole layer.
For rrr< minutes, apply force to the opening formed in the spacer Si3N4 film O to perform etching and etching of the electrode layer (step 13).Use IC7/H20 solution as the etching solution. Ino.saGaO,47A
Since it is possible to selectively combine S and InP, ■
・Litink stops at the interface between the active layer (1'2) and the n-electrode shield (1-nil).
従ってゲートQ(極(19の直下のチセシネルJ9さt
′はちょうど活性jM(J乃の膜厚に等しい。結晶成長
は膜厚の面内均一性および制御性に優れているMBE成
長でなされているためt’= 800Aが常にウェハー
のどの場所でも成りたち、そのtこめ非常に再現性よく
ノーマリオフ特性が得られる。シヨ・シト+−ゲート電
極00はAe魚着およびフトオフ技術により形成する。Therefore, the gate Q (pole (19)
' is exactly equal to the film thickness of the active jM (J). Because the crystal growth is done by MBE growth, which has excellent in-plane film thickness uniformity and controllability, t' = 800A is always achieved at any location on the wafer. As a result, normally-off characteristics can be obtained with very good reproducibility.The top and bottom gate electrodes 00 are formed by the Ae fish and foot-off techniques.
以上のようにして第2図のMES−FETが得られる。In the manner described above, the MES-FET shown in FIG. 2 is obtained.
であり・比抵抗は5 X 10−’Ω−Cnl と低く
、従一つで、ゲート・ソース間の抵抗は電イ1ζIiへ
1 t13の+1イド]−゛ソチンジによって生じtこ
距1’j:l lの能fij!+ lri n型InO
,53Ga O,47As JfJ Q2の抵抗分だ6
すとなり敬Ωの低]Lll、抗で11f来の第1図の例
に比べ2桁の改善がなされfコ。The specific resistance is as low as 5 x 10-'Ω-Cnl, and the resistance between the gate and the source is 1ζIi to 1t13 +1 id]-゛Sochinji, which is caused by the distance 1'j: l l's Noh fij! + lri n-type InO
,53Ga O,47As JfJ It is the resistance of Q26
A two-digit improvement has been made in the resistance of 11 f compared to the example shown in Fig. 1.
得られたMES−FETの静持性として、しきい値ケ−
l−tff圧V丁= 0.1ポル1−(ド1ノイーJ電
流20 //A) ]?/タクタンスF?m= 150
m5/m+yx、 ;t y抵抗R□N=150Ω伝播
遅延速度201)s、’:従)1コより10倍高速な;
Lモ子が?“7られた。As the static stability of the obtained MES-FET, the threshold value
l-tff pressure V = 0.1 por 1-(d 1 noi J current 20 //A) ]? /Tactance F? m=150
m5/m+yx, ;t y resistance R□N=150Ω Propagation delay speed 201) s,': slave) 10 times faster than 1;
L Moko? “I got 7.
なお、」二記実1’f+j例において活性層Uツ市5(
弛L゛j(1月11 n o、sa Ga o、4゜Δ
s、InPとして説明したが、これはGaAs。In addition, in the example of "2 Notes 1'f+j", the active layer Utsuichi 5 (
Relaxation L゛j (January 11 no, sa Ga o, 4゜Δ
s, InP, but this is GaAs.
(ya 1 xAlXAe、 Ill 1−XGaXA
Si −y Py 、 I n )−x、G(I XA
hP 。(ya 1 xAlXAe, Ill 1-XGaXA
Si-y Py, I n )-x, G(I XA
hP.
GaSbなど、どのようプλlll −V /へ化合物
半尊付\でも可能である。まr、:I;I;、rの子ト
ネII/ 21IL!もn l’ ?ネルに限定される
ものではない。43’ −1−IY、、f!〕;もAl
に限らずCr−Pt、金屑シリリイドなどこの他のもの
でも可能である。FET特性もノーマリオフ!リリにl
;−1*らずノーマリオン型でもよい。Any compound, such as GaSb, can be added to λllll -V /. Mar, :I;I;, r's son Tone II/21IL! Mo n l'? It is not limited to flannel. 43'-1-IY,, f! ];MoAl
However, other materials such as Cr--Pt and gold scrap silylide are also possible. FET characteristics are also normally off! Lily to l
;-1*Normally-on type may be used.
発明の効集
以−ヒ説明の、I′うに本発明の1a界効果型トランジ
スタによる2−5活性J1”りよ、ソース7fて極とド
レイ7ン″11にlj−とを異なるIll −V fr
’j:化合物半専体で形成し1こ1こめ、高いイ[1,
l:I’、 ]ヲタクタンスを有し、高77動作の可能
なItJ界効果1−うシジスタを再現性よ< i’、’
fることかできるものである。In the summary of the invention, the 2-5 active J1 by the 1a field effect transistor of the present invention is different from the source 7f and the drain 7'11 by Ill -V fr.
'j: Formed with compound semi-exclusively, with high i[1,
l: I', ] reproducible ItJ field effect 1-effect resistor with high tactance and capable of high 77 operation <i','
It is possible to do something like f.
第1図は従)14の電ル゛2効果トラyジスタの断面図
、第2図は本発明の一実施例の電界効果1−5二ノジス
タの断面図でΔ′、る。
(1(N 半T:Q !l!f1.T nP基板、(I
II −i型1nPバ・ソファhニア、’J’A −n
2GQ In6.53Gn6,47AS活性11el
[’第1の川−V族化合物半導体から成る活訃Jri
) 、 o:i・n型1nP’jri極層(’、第2
(7) 川−V族化合物21″導体7J1ら成ロソー
ス 及 乙〆 ト1ノ イ I ’f(−f !j’
RJ 、 (14) (lfQ −ΔuGeN i /
Au 114J 、(In) −’j’ −) Wi、
t;tji代理人 合 本 、%6 弘
第1図
第2図FIG. 1 is a sectional view of a field effect transistor 1-5 according to an embodiment of the present invention, and FIG. 2 is a sectional view of a field effect transistor 1-5 according to an embodiment of the present invention. (1(N half T:Q !l!f1.T nP substrate, (I
II -i type 1nP Ba Sofa hnia, 'J'A -n
2GQ In6.53Gn6,47AS activity 11el
['The first river - an active semiconductor composed of a group V compound semiconductor]
), o: i/n type 1nP'jri polar layer (', second
(7) I'f(-f!j'
RJ, (14) (lfQ −ΔuGeN i /
Au 114J, (In)-'j'-) Wi,
t; tji agent combined copy, %6 Hiro 1, 2
Claims (1)
、この活性層とシヨ・リド士−バリ?接合を形成するゲ
ート鍵、(完と、前記活性層」二に配設される表共に第
1 (7) III −V族化合物半導体とは異なる第
2のIII −V If、(化合物半導体からなるソー
スおよびドしイン電fltとを設けtこ電、界効眼型ト
ランジスタ。1. An active layer made of a 1st σ group 11-v compound semiconductor, and the relationship between this active layer and the 11-v group compound semiconductor. A gate key for forming a junction, (7) a second III-V If, which is different from a III-V compound semiconductor, (made of a compound semiconductor); A field effect type transistor is provided with a source and a drain voltage flt.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14720583A JPS6037784A (en) | 1983-08-10 | 1983-08-10 | Field effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14720583A JPS6037784A (en) | 1983-08-10 | 1983-08-10 | Field effect transistor |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6037784A true JPS6037784A (en) | 1985-02-27 |
Family
ID=15424935
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14720583A Pending JPS6037784A (en) | 1983-08-10 | 1983-08-10 | Field effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6037784A (en) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6254967A (en) * | 1985-09-04 | 1987-03-10 | Sumitomo Electric Ind Ltd | Field effect transistor |
JPS63188973A (en) * | 1987-01-30 | 1988-08-04 | Nec Corp | Semiconductor device |
JPH04202205A (en) * | 1990-11-29 | 1992-07-23 | Chisso Corp | Matted vinyl chloride resin composition |
US5170230A (en) * | 1989-05-10 | 1992-12-08 | Fujitsu Limited | Semiconductor device and production method thereof |
EP0551110A2 (en) * | 1992-01-09 | 1993-07-14 | Mitsubishi Denki Kabushiki Kaisha | Compound semiconductor devices |
WO2011155571A1 (en) | 2010-06-09 | 2011-12-15 | 旭化成ケミカルズ株式会社 | Thermoplastic elastomer composition and molded articles thereof |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5661169A (en) * | 1979-10-25 | 1981-05-26 | Oki Electric Ind Co Ltd | Preparation of compound semiconductor device |
JPS5768073A (en) * | 1980-10-14 | 1982-04-26 | Nec Corp | Field effect transistor |
JPS57112079A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Field-effect semiconductor device |
-
1983
- 1983-08-10 JP JP14720583A patent/JPS6037784A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5661169A (en) * | 1979-10-25 | 1981-05-26 | Oki Electric Ind Co Ltd | Preparation of compound semiconductor device |
JPS5768073A (en) * | 1980-10-14 | 1982-04-26 | Nec Corp | Field effect transistor |
JPS57112079A (en) * | 1980-12-29 | 1982-07-12 | Fujitsu Ltd | Field-effect semiconductor device |
Cited By (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6254967A (en) * | 1985-09-04 | 1987-03-10 | Sumitomo Electric Ind Ltd | Field effect transistor |
JPS63188973A (en) * | 1987-01-30 | 1988-08-04 | Nec Corp | Semiconductor device |
US5170230A (en) * | 1989-05-10 | 1992-12-08 | Fujitsu Limited | Semiconductor device and production method thereof |
JPH04202205A (en) * | 1990-11-29 | 1992-07-23 | Chisso Corp | Matted vinyl chloride resin composition |
EP0551110A2 (en) * | 1992-01-09 | 1993-07-14 | Mitsubishi Denki Kabushiki Kaisha | Compound semiconductor devices |
EP0551110A3 (en) * | 1992-01-09 | 1994-09-07 | Mitsubishi Electric Corp | Compound semiconductor devices |
US5477066A (en) * | 1992-01-09 | 1995-12-19 | Mitsubishi Denki Kabushiki Kaisha | Heterojunction bipolar transistor |
US5508535A (en) * | 1992-01-09 | 1996-04-16 | Mitsubishi Denki Kabushiki Kaisha | Compound semiconductor devices |
WO2011155571A1 (en) | 2010-06-09 | 2011-12-15 | 旭化成ケミカルズ株式会社 | Thermoplastic elastomer composition and molded articles thereof |
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