JPS6037778A - Mos non-volatile memory cell - Google Patents
Mos non-volatile memory cellInfo
- Publication number
- JPS6037778A JPS6037778A JP14703183A JP14703183A JPS6037778A JP S6037778 A JPS6037778 A JP S6037778A JP 14703183 A JP14703183 A JP 14703183A JP 14703183 A JP14703183 A JP 14703183A JP S6037778 A JPS6037778 A JP S6037778A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- insulation film
- gate insulation
- injection
- immediately under
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000009413 insulation Methods 0.000 claims abstract 9
- 238000002347 injection Methods 0.000 abstract description 13
- 239000007924 injection Substances 0.000 abstract description 13
- 238000000206 photolithography Methods 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 230000004913 activation Effects 0.000 abstract description 2
- 238000010438 heat treatment Methods 0.000 abstract description 2
- 239000012535 impurity Substances 0.000 abstract description 2
- 238000005468 ion implantation Methods 0.000 abstract description 2
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 241001137307 Cyprinodon variegatus Species 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は不揮発性メモリに関し、特に、低電圧かつ短時
間での書き込みを可能にしたメモリセルのイ１１１７造
に係る。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a nonvolatile memory, and in particular to a structure of a memory cell that enables writing at low voltage and in a short time.
ＰチャンネルＭＯ８不揮発性メモリセル（以下ＦＲＯＭ
セルという）は、通常２トランジスタで１メモリセルを
構成する。これを第１図に示す。P-channel MO8 non-volatile memory cell (FROM
One memory cell (referred to as a memory cell) is usually composed of two transistors. This is shown in FIG.
同図において、１はＮ型シリコン基板であり、該シリコ
ン基板には、Ｐ型の拡散Ｊｊ・′１領域２，３１４が形
成され、ゲート絶縁膜５，６を介して、セルを選択する
だめのコントロールゲート７、電荷を蓄積するだめのフ
ローティングゲート８が形成される。この場合、フロー
ティングゲートへの電荷の注入はドレイン領域４へ負の
電圧パルスを加えて、ドレイン４と基板１との間にアバ
ランシェブレークダウンを起こすことによって行われる
。ブレークダウンによって発生した′［ニ子はゲート絶
縁膜６を１１０ってフローティングゲートへ注入される
が、このゲート絶縁膜は膜厚が薄いほど１：ｊ：子の注
入効率は高くなる。しかし、従）にのＦ ＲＯＭセルは
、５と６のゲート絶縁膜を同一工程で形成しているため
、かかるゲート絶ｌｆ膜厚で決定される注入効率しか得
られなかった。In the figure, reference numeral 1 denotes an N-type silicon substrate, on which a P-type diffusion Jj. A control gate 7 and a floating gate 8 for storing charge are formed. In this case, charge injection into the floating gate is performed by applying a negative voltage pulse to the drain region 4 to cause avalanche breakdown between the drain 4 and the substrate 1. The electrons generated by the breakdown are injected into the floating gate through the gate insulating film 6, and the thinner the gate insulating film is, the higher the injection efficiency of the 1:j: electrons becomes. However, in the F ROM cell of the previous example, the gate insulating films 5 and 6 were formed in the same process, so that only the injection efficiency determined by the gate insulating film thickness could be obtained.
本発明によるメモリセルはかかる欠点を改善した構造を
有している。以下図面を参照し、咽Ｊ造方法の一例を併
記して、本発明の詳細な説明する。The memory cell according to the present invention has a structure that improves this drawback. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings and an example of a method for constructing a throat.
第２図はＮ型シリコン基板を酸化してゲート絶ｈｎ’ｊ
’：９を形成し、フォトリングラフィによりバターニン
グしたレジストマスク１０で７０−ティングゲート直下
のゲート絶縁膜の一部分を除去した直後の断面図である
。該レジストマスクを除去後、再度熱酸化を行うことに
よって第６図に示すような、膜厚の一部ｆｔ＋ｊ ＜な
ったゲート絶縁膜１１が形成される。その後デー１〜電
極となるボリンリコン１２．７３をフォトリソグラフィ
により形成し、イオン打ち込みとそれに続く不純物活性
化のための熱処理によりＰ型の拡散Ｊ？７ｉ領域２，３
．４を形成する。（第４］Ａ）第４図の１３が電荷のｉ
−Ｌ人されるフローディングゲートであり、かかるフロ
ーティングゲート直下のゲート絶縁膜は−ｆ５（≦薄く
なっている。この薄いゲート絶縁膜を通って′ｊＬ子が
法人されるため注入効率は上がり、その結果、注入のた
めの電圧を下げることが可能になる。さらに、注入効率
がｊ二がることによって注入時間の短縮化がＪ能となる
。Figure 2 shows gate termination by oxidizing an N-type silicon substrate.
9 is a cross-sectional view immediately after a portion of the gate insulating film directly under the gate 70 is removed using a resist mask 10 patterned by photolithography. After removing the resist mask, thermal oxidation is performed again to form a gate insulating film 11 whose thickness is partially ft+j as shown in FIG. Thereafter, a bolin silicon 12.73 which will become an electrode is formed by photolithography, and P-type diffusion J? is performed by ion implantation and subsequent heat treatment for impurity activation. 7i area 2, 3
．． form 4. (4th) A) 13 in Figure 4 is the charge i
-L is a floating gate, and the gate insulating film directly under the floating gate is -f5 (≦ thinner. Since 'jL is incorporated through this thin gate insulating film, the injection efficiency increases, As a result, it becomes possible to lower the voltage for injection.Furthermore, the injection efficiency is reduced by J2, thereby making it possible to shorten the injection time.
また、第３図において薄いゲートを邑縁月（，３をフロ
ーテインクゲート１５直下の全領域にわたって形成する
ことも可能である。（第５ ｒｉ ）この場合は、第２
図でレジストによってバターニングする領域を広くとる
ことができ、フローティングゲートとの重なりを考慮し
なくて良いため、製造方法が１ｉｉｉ単になるという利
点をイｆする。It is also possible to form a thin gate in FIG. 3 over the entire area directly under the floating ink gate 15.
As shown in the figure, the area to be patterned using the resist can be widened, and there is no need to consider the overlap with the floating gate, which has the advantage that the manufacturing method is extremely simple.
以上、本発明によれば、単純な構造により注入効率が高
く、低電圧、短詩１７Ｕでの書き込みを可能とした不揮
発性メモリセルを提供できるものである。As described above, according to the present invention, it is possible to provide a nonvolatile memory cell that has a simple structure, has high injection efficiency, and is capable of writing at a low voltage and short length of 17U.
第１図は従来のＦ ＲＯＭセルの一例を示す図である。
第２図〜第４図は不発”）ＪによるＦ ＲＯＭセルの一
製造方法を示す図である。第５図はその応用例を示す図
である。それぞれの図は、シリコン基板の断面の概略を
表わしている。
１・・・・・・Ｎ型シリコン基４反
２．３，４，５．６ ・・・ ・・・ ゲ − ト 絶
ｔ３西Ｈ次７・・・・・・コントロールゲート
８・・・・・・フローティングケート
９・・・・・・一部を除去したゲート絶縁膜１０・・・
レジスト
１１・・・膜厚の一部が薄いゲート絶縁膜１２・・・コ
ントロールゲート
１３・・・フローティングゲート
１４・・・フローティングゲート直下の膜厚の全部分が
薄いゲート純緑膜
以 」−FIG. 1 is a diagram showing an example of a conventional FROM cell. Figures 2 to 4 are diagrams showing a method of manufacturing an FROM cell by J. 1... N-type silicon base 4 anti-2.3, 4, 5.6... Gate off t3 West H order 7... Control gate 8... Floating cage 9... Gate insulating film 10 with a part removed...
Resist 11...Gate insulating film 12...Control gate 13...Floating gate 14...Gate pure green film where the entire film thickness directly under the floating gate is thin.
Claims (1)
スタと、かかるトランジスタを選択するためのコントロ
ールゲートを持つトランジスタとの２つのトランジスタ
からなるＰチャンネルＭＯ８不揮発性メモリセルにおい
て、浮遊ゲート直下のゲート絶縁ｊ漠を一部分もしくは
全部分、コントロールゲート直下のゲート絶縁ｊＱより
も薄ぐすることを特徴とするＭＯ８不揮発性メモリセル
。In a P-channel MO8 nonvolatile memory cell consisting of two transistors: a memory transistor with a floating gate for storing charge and a transistor with a control gate for selecting such a transistor, the gate insulation immediately below the floating gate is An MO8 nonvolatile memory cell characterized in that part or all of the gate insulation jQ is made thinner than the gate insulation jQ directly under the control gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14703183A JPS6037778A (en) | 1983-08-10 | 1983-08-10 | Mos non-volatile memory cell |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14703183A JPS6037778A (en) | 1983-08-10 | 1983-08-10 | Mos non-volatile memory cell |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6037778A true JPS6037778A (en) | 1985-02-27 |
Family
ID=15420968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14703183A Pending JPS6037778A (en) | 1983-08-10 | 1983-08-10 | Mos non-volatile memory cell |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6037778A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5359573A (en) * | 1992-06-19 | 1994-10-25 | Lattice Semiconductor Corporation | Flash E2 PROM array with mingle polysilicon layer memory cell |
| US5418390A (en) * | 1993-03-19 | 1995-05-23 | Lattice Semiconductor Corporation | Single polysilicon layer E2 PROM cell |
| US5886378A (en) * | 1992-06-19 | 1999-03-23 | Lattice Semiconductor Corporation | Single polysilicon layer flash E2 PROM cell |
| JP2007024401A (en) * | 2005-07-15 | 2007-02-01 | Tokyo Gas Co Ltd | Sealed container type heat exchanger |
-
1983
- 1983-08-10 JP JP14703183A patent/JPS6037778A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5359573A (en) * | 1992-06-19 | 1994-10-25 | Lattice Semiconductor Corporation | Flash E2 PROM array with mingle polysilicon layer memory cell |
| US5886378A (en) * | 1992-06-19 | 1999-03-23 | Lattice Semiconductor Corporation | Single polysilicon layer flash E2 PROM cell |
| US5418390A (en) * | 1993-03-19 | 1995-05-23 | Lattice Semiconductor Corporation | Single polysilicon layer E2 PROM cell |
| JP2007024401A (en) * | 2005-07-15 | 2007-02-01 | Tokyo Gas Co Ltd | Sealed container type heat exchanger |
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