JPS6035636U - Flip-flop circuit with inversion inhibit mode - Google Patents

Flip-flop circuit with inversion inhibit mode

Info

Publication number
JPS6035636U
JPS6035636U JP12667483U JP12667483U JPS6035636U JP S6035636 U JPS6035636 U JP S6035636U JP 12667483 U JP12667483 U JP 12667483U JP 12667483 U JP12667483 U JP 12667483U JP S6035636 U JPS6035636 U JP S6035636U
Authority
JP
Japan
Prior art keywords
flip
flop circuit
inversion
output
inhibit mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12667483U
Other languages
Japanese (ja)
Inventor
小俣　弘行
Original Assignee
パイオニア株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パイオニア株式会社 filed Critical パイオニア株式会社
Priority to JP12667483U priority Critical patent/JPS6035636U/en
Publication of JPS6035636U publication Critical patent/JPS6035636U/en
Pending legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、従来のフリップフロップ回路を示す回路図、
第２図は、本考案の一実施例を示す回路図である。 主要部分の符号の説明、２・・・Ｒ−Ｓフリップフロッ
プ、Ｇ５．　Ｇ６・・・ＮＯＲゲート、ＤＩ、Ｄ２・・
・ダイオード。FIG. 1 is a circuit diagram showing a conventional flip-flop circuit,
FIG. 2 is a circuit diagram showing an embodiment of the present invention. Explanation of symbols of main parts, 2...R-S flip-flop, G5. G6...NOR gate, DI, D2...
·diode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] Ｑ出力及びＱ出力が同一の所定状態となりかつセット信
号及びリセット信号のいずれが入力されても反転しない
反転禁止モードを有するフリップフロップ回路であって
、ダイオードを介して前記Ｑ出力及びＱ出力をリセット
入力端子及びセット入力端子にそれぞれ帰還する帰還手
段を備えたことを特徴とする反転禁止モードを有するフ
リップフロップ回路。A flip-flop circuit having an inversion prohibition mode in which the Q output and the Q output are in the same predetermined state and are not inverted even if either a set signal or a reset signal is input, and the Q output and the Q output are reset via a diode. 1. A flip-flop circuit having an inversion prohibition mode, characterized in that the flip-flop circuit is provided with feedback means for feeding back to an input terminal and a set input terminal, respectively.
JP12667483U 1983-08-15 1983-08-15 Flip-flop circuit with inversion inhibit mode Pending JPS6035636U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12667483U JPS6035636U (en) 1983-08-15 1983-08-15 Flip-flop circuit with inversion inhibit mode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12667483U JPS6035636U (en) 1983-08-15 1983-08-15 Flip-flop circuit with inversion inhibit mode

Publications (1)

Publication Number Publication Date
JPS6035636U true JPS6035636U (en) 1985-03-12

Family

ID=30287955

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12667483U Pending JPS6035636U (en) 1983-08-15 1983-08-15 Flip-flop circuit with inversion inhibit mode

Country Status (1)

Country Link
JP (1) JPS6035636U (en)

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