JPS6032348A - Semiconductor device having cooling structure - Google Patents
Semiconductor device having cooling structureInfo
- Publication number
- JPS6032348A JPS6032348A JP14103183A JP14103183A JPS6032348A JP S6032348 A JPS6032348 A JP S6032348A JP 14103183 A JP14103183 A JP 14103183A JP 14103183 A JP14103183 A JP 14103183A JP S6032348 A JPS6032348 A JP S6032348A
- Authority
- JP
- Japan
- Prior art keywords
- fluid
- housing
- chips
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は、冷却構造を備えた半導体装置に係シ、特に超
大形コンピュータ等に高密度に実装される大規模集積回
路チップ等から発生する熱を除去するのに好適の冷却構
造を備えた半導体装置に関するものである。[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor device equipped with a cooling structure, and particularly to heat generated from large-scale integrated circuit chips etc. that are densely packed in ultra-large computers etc. This invention relates to a semiconductor device equipped with a cooling structure suitable for removing.
従来の半導体累子あるいは集積回路チップを備えた半導
体装置の冷却構造の各側を、各図を参照して説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS Each side of a conventional cooling structure for a semiconductor device having a semiconductor component or an integrated circuit chip will be described with reference to the respective figures.
第１図は、従来例の冷却構造を備えた半導体装置の断面
図、第２図、第３図は、いずれも他の従来例の冷却構造
を備えた半導体装置の断面図で、第１図と同一符号のも
のは同等部分を示している。FIG. 1 is a cross-sectional view of a semiconductor device equipped with a conventional cooling structure, and FIGS. 2 and 3 are cross-sectional views of semiconductor devices equipped with other conventional cooling structures. Items with the same reference numerals indicate equivalent parts.
第１図において、多層配線された基板１の上に多数の大
規模集積回路（以下ＬＳＩという）チップ２がフェース
ダン接合によって実装されている。In FIG. 1, a large number of large scale integrated circuit (hereinafter referred to as LSI) chips 2 are mounted on a substrate 1 having multilayer wiring by face-to-face bonding.
多数のＬＳＩテップ２を覆うようにハウジング３Ａが基
板１に装着されている。各ＬＳＩテップ２の裏面に接触
するようハウジング３Ａ面に多数の可撓性の袋４が取付
けられ、袋４の内には、流動性に富み高熱伝導性の液体
５が封入されている。A housing 3A is attached to the board 1 so as to cover a large number of LSI chips 2. A large number of flexible bags 4 are attached to the surface of the housing 3A so as to be in contact with the back surface of each LSI chip 2, and a highly fluid and highly thermally conductive liquid 5 is sealed inside the bags 4.
袋４はハウジング３Ａを基板１に装着する際、各ＬＳＩ
テップ２に、おる圧力をもって密着するように押し付け
られる。ＬＳＩテップ２は、基板１と半田ボール７とで
フェースダン接合され、基板工の裏面のビン８と電気的
に接続されている。半田ポーノビ７は非常に小さいため
、ＬＳＩチップ２０発熱は、半田ボール７を通して基板
にほとんど伝えることができない。したがって大部分の
熱はＬＳＩチップ２の裏面から高熱伝導性の液体５が封
入された袋４を経て、ハウジング３Ａに伝えられ、ハウ
ジング３Ａに設けられた冷却水流路９を流れる冷却水に
よシ除去される。The bag 4 is used to hold each LSI when mounting the housing 3A on the board 1.
It is pressed against Step 2 with a certain amount of pressure. The LSI chip 2 is face-down bonded between the board 1 and the solder balls 7, and is electrically connected to the pin 8 on the back side of the board. Since the solder balls 7 are very small, almost no heat generated by the LSI chip 20 can be transmitted to the board through the solder balls 7. Therefore, most of the heat is transferred from the back surface of the LSI chip 2 to the housing 3A via the bag 4 filled with a highly thermally conductive liquid 5, and is transferred to the cooling water flowing through the cooling water flow path 9 provided in the housing 3A. removed.
基板１は、多層配線構造のため一般に変形しゃすぐ製造
的に反シが発生する。また、半田ボール７による接合方
法は一度にＬＳＩチップ２の多数の電気配線を行う特徴
がちシ、各ＬＳＩチップ２の実装高さをそろえることが
困難である。したがって、ハウジング３ＡとＬＳＩチッ
プ２との熱的結合を図る可撓性の熱伝導縦路が必要とな
る。この点、第１図の冷却構造は袋４内に封入された高
熱伝導性液体５が非圧縮性流体であるため、袋４は非常
に可撓性に冨んだ材料で形成されなければならない。し
かも、封止液体５に対し耐蝕性があジ、熱伝導率ができ
るだけ大きな、耐熱性に富んだ膜でなければならず、袋
材料の選定が非常に難かしい。筐た、第１図の袋構造で
は、ＬＳ、Ｉテップ２の変形性が大きくなると、袋４内
の液体５の内圧力が大きくなる。そのため、ＬＳＩチッ
プ２に加わる荷重も大きくなるので、形状寸法が非常に
小さい半田ボールは塑性変形する。このような状態で、
ＬＳＩテップ２に長期間、通電、停止のサイクルを続け
れば、クリープ現象によシ半田ポール７は破断してしま
い、電気接続が断線する。Since the substrate 1 has a multilayer wiring structure, it generally does not deform and cracks occur during manufacturing. Further, the bonding method using the solder balls 7 has the characteristic that a large number of electrical wirings of the LSI chips 2 are connected at once, and it is difficult to make the mounting heights of each LSI chip 2 the same. Therefore, a flexible heat conduction path for thermally coupling the housing 3A and the LSI chip 2 is required. In this regard, in the cooling structure shown in FIG. 1, since the highly thermally conductive liquid 5 sealed in the bag 4 is an incompressible fluid, the bag 4 must be made of a highly flexible material. . In addition, the membrane must be highly heat resistant, having high corrosion resistance to the sealing liquid 5 and as high a thermal conductivity as possible, making selection of the bag material extremely difficult. In the bag structure shown in FIG. 1, as the deformability of the LS and I tips 2 increases, the internal pressure of the liquid 5 in the bag 4 increases. Therefore, the load applied to the LSI chip 2 also increases, and the solder balls, which have very small dimensions, are plastically deformed. In this situation,
If the LSI step 2 continues to be energized and de-energized for a long period of time, the solder pole 7 will break due to the creep phenomenon, and the electrical connection will be broken.
一方、袋４の薄膜にも大きな張力が加わシ、膜の寿命を
低下させる。On the other hand, a large tension is also applied to the thin film of the bag 4, reducing the life of the film.
そこで上記の欠点を改善するため、第２図の冷却構造が
提朶されている。In order to improve the above-mentioned drawbacks, the cooling structure shown in FIG. 2 has been proposed.
第２図の冷却構造は、第１図と同様に基板１上に半田ボ
ール７によってフェースダン接合されたＬＳＩチップ２
と基板１の上面から全体に薄膜１０がコーティングされ
、コーティング薄膜１０の上のハウジング３Ｂ内面間の
空間領域１１に、流動性に富み高熱伝導率の液体１２を
充填されたものである。ＬＳＩチップ２０発熱は上部の
液体１２からハウジング３Ｂを経て、ハウジング３Ｂ内
に設けられた冷却水流路９を流れる冷却水により排除さ
れる。The cooling structure in FIG. 2 consists of an LSI chip 2 face-down bonded onto a substrate 1 by solder balls 7, as in FIG.
A thin film 10 is coated over the entire upper surface of the substrate 1, and a space 11 between the inner surface of the housing 3B above the coating thin film 10 is filled with a fluid 12 having high fluidity and high thermal conductivity. The heat generated by the LSI chip 20 is removed by the cooling water flowing from the upper liquid 12 through the housing 3B and through the cooling water passage 9 provided in the housing 3B.
しかし、このような第２図の冷却構造では新たな問題が
生じる。基板１上に多数実装されたＬＳＩチップのうち
１部分のチップが不良になった場合、不良チップの交換
が要求される。マルチ・チップ・モジュールは１チツプ
・モジュールに比べ高価であるため、モジュール全体を
廃棄することはできない。しかし、ＬＳＩチップ背面に
薄膜が施されているので、薄膜の補修が非常に困難であ
る。However, a new problem arises in the cooling structure shown in FIG. 2. If one of the many LSI chips mounted on the substrate 1 becomes defective, the defective chip is required to be replaced. Since multi-chip modules are more expensive than single-chip modules, the entire module cannot be discarded. However, since a thin film is applied to the back surface of the LSI chip, it is very difficult to repair the thin film.
たとえ一部分補修が行われても、薄膜１ｏは継ぎ目が生
じる。また、薄膜全体を剥離させれば、良品のチップの
半田ボールに影響を及ぼし、モジュールの信頼性を低下
させる。Even if a partial repair is performed, seams will occur in the thin film 1o. Moreover, if the entire thin film is peeled off, it will affect the solder balls of good chips, reducing the reliability of the module.
そこで、更に上記の欠点を解決するため、第３図の冷却
構造が提案されている。第１図および第２図と同等部分
は、同一番号を付は説明を省略する。Therefore, in order to further solve the above-mentioned drawbacks, the cooling structure shown in FIG. 3 has been proposed. Components equivalent to those in FIG. 1 and FIG. 2 are designated by the same reference numerals, and explanation thereof will be omitted.
多数のＬＳＩチップ２とハウジング３Ｃの内面間に流動
性に富んだ高熱伝導性の流体１３を充填させた袋１４が
挿入されている。各ＬＳＩテップ２はこの袋１４に接触
することによシ冷却される。A bag 14 filled with a highly fluid and highly thermally conductive fluid 13 is inserted between a large number of LSI chips 2 and the inner surface of the housing 3C. Each LSI chip 2 is cooled by contacting this bag 14.
しかし第３図の冷却構造においては下記の問題が生ずる
。すなわち、ＬＳＩチップ２の冷却性能を高めようとす
ると、袋１４との密着性を良くしなければならない。そ
のため袋１４の膜は第１図の場合と同様に薄くて柔軟性
のある膜が要求される。However, the following problem occurs in the cooling structure shown in FIG. That is, in order to improve the cooling performance of the LSI chip 2, the adhesion with the bag 14 must be improved. Therefore, the membrane of the bag 14 is required to be thin and flexible as in the case of FIG.
また、第１図と異なシ、袋１４はＬＳＩチップ２の端が
接触するため、袋１４が破断する恐れがあシ、長期使用
に対する信頼性に問題がある。Furthermore, since the bag 14, which is different from that shown in FIG. 1, comes into contact with the end of the LSI chip 2, there is a risk that the bag 14 will break, which poses a problem in reliability for long-term use.
本発明は、以上述べた従来技術の問題点を解決するため
になされたもので、基板の反シ、半導体チップの接続変
位、冷却構造部の組立時の変形や熱変形などさまざまの
変位を吸収する機能を備え、かつ、冷却性能のすぐれた
冷却構造を備えた半導体装置を提供することを、その目
的としている。The present invention has been made in order to solve the problems of the prior art described above, and absorbs various displacements such as substrate warping, semiconductor chip connection displacement, cooling structure deformation during assembly, and thermal deformation. It is an object of the present invention to provide a semiconductor device having a cooling structure with excellent cooling performance.
本発明に係る半導体装置の構成は、基板と、この基板に
実装される複数の半導体チップと、この半導体チップを
覆うように基板に装着されているハウジングとからなる
半導体装置において、前記基板と前記ハウジングとで形
成される空間領域を仕切るように、かつ、・前記半導体
テップの上部を覆うように可撓性のある仕切シ膜を設け
、当該仕切り膜と前記ハウジングとで形成される空間領
域に、流動性のある高熱伝導性流体を充填し、さらに、
前記仕切シ膜と前記半導体チップの背面との間に、流動
性のある高熱伝導性流体を充填した複数の枕を、前記複
数の半導体チップとおのおの独立に接触するように配設
したものである。A semiconductor device according to the present invention includes a substrate, a plurality of semiconductor chips mounted on the substrate, and a housing attached to the substrate so as to cover the semiconductor chips. A flexible partition film is provided to partition a spatial region formed by the housing, and to cover an upper part of the semiconductor tip, and a flexible partition film is provided to partition a spatial region formed by the partition film and the housing. , filled with a fluid and highly thermally conductive fluid, and
A plurality of pillows filled with a fluid and highly thermally conductive fluid are arranged between the partition membrane and the back surface of the semiconductor chip so as to contact each of the plurality of semiconductor chips independently. .
なお付記すれば、本発明は、半導体装置のさまざまの変
位を吸収するため、多数の半導体チップの上面とハウジ
ング内面との間に２重の可撓性冷却構造を設けたことが
特徴点でおる。すなわち、基板の反見冷却構造全体の変
形など、各々の半導体チップに共通する大きな変位を吸
収する機構と、各々の半導体チップの接続バラツキを吸
収する機構とを別々に分離させたものである。Additionally, the present invention is characterized in that a double flexible cooling structure is provided between the top surface of a large number of semiconductor chips and the inner surface of the housing in order to absorb various displacements of the semiconductor device. . In other words, a mechanism for absorbing large displacements common to each semiconductor chip, such as deformation of the entire counterclockwise cooling structure of the substrate, and a mechanism for absorbing connection variations of each semiconductor chip are separated.
以下、本発明の各実施例を各図を参照して説明する。 Hereinafter, each embodiment of the present invention will be described with reference to each figure.
第４図は、本発明の一実施例に係る冷却構造を備えた半
導体装置の断面図、第５図、第６図、第７図はいずれも
本発明の他の実施例に係る冷却構造を備えた半導体装置
の断面図であシ、これら各図において、先の第１図と同
一符号のものは、従来技術と同等部分を示している。FIG. 4 is a cross-sectional view of a semiconductor device equipped with a cooling structure according to one embodiment of the present invention, and FIGS. 5, 6, and 7 all show cooling structures according to other embodiments of the present invention. In each of these figures, the same reference numerals as in FIG. 1 indicate the same parts as in the prior art.
まず、本発明の一実施例を第４図を参照して説明する。First, one embodiment of the present invention will be described with reference to FIG.
多数のＬＳＩテップ２は多層配線基板１と微小な半田ボ
ール７を介してフェースダン接合によって電気的な接続
とチップの固定とが行われている。A large number of LSI chips 2 are electrically connected and chips are fixed by face-down bonding via a multilayer wiring board 1 and minute solder balls 7.
多数のＬＳＩチップ２を覆９ようにハウジング３が基板
１に装着されている。多数のＬＳＩチップ２の上面とハ
ウジング３の内面との間に可撓性のよい変形可能な仕切
り膜１５が設けられ、この仕切シ膜１５とハウジング３
内面とで形成される空間領域に流動性に富んだ高熱伝導
性の流体１６が充填されている。一方、仕切り膜１５の
反対側の表面には、各複数のＬＳＩテップ２と相対応す
るおのおの独立した複数の枕１７が設けられている。A housing 3 is attached to a substrate 1 so as to cover a large number of LSI chips 2. A flexible and deformable partition film 15 is provided between the upper surface of the large number of LSI chips 2 and the inner surface of the housing 3.
A highly fluid and highly thermally conductive fluid 16 is filled in the space formed by the inner surface. On the other hand, on the opposite surface of the partition film 15, a plurality of independent pillows 17 are provided, each corresponding to a plurality of LSI tips 2.
これら枕１７は、各ＬＳＩテップ２の背面とおのおの独
立に良好に接触しうるように、流動性で高熱伝導性の流
体１６′が薄い被覆膜１８によって覆われている。These pillows 17 are covered with a fluid and highly thermally conductive fluid 16' by a thin coating film 18 so as to be able to come into good contact with the back surface of each LSI chip 2 independently.
なお、仕切シ膜１５は薄い金属箔あるいは合成樹脂など
で良い。Note that the partition film 15 may be made of thin metal foil, synthetic resin, or the like.
また、流動性で高熱伝導性の流体１６．１６’は液体金
属あるいは熱伝導性グリースなどがよい。Further, the fluid 16, 16' which is fluid and has high thermal conductivity is preferably a liquid metal or thermally conductive grease.
さらに、薄い被覆膜１８は、内部の流体１６′に対し耐
食性があシ、熱伝導率ができるだけ大きい耐熱性のもの
が良く、たとえば、パリレン膜（商品名）などが好適で
ある。その他の構造は従来例と同一であるので、説明を
省略する。Further, the thin coating film 18 is preferably a heat-resistant film that has corrosion resistance against the internal fluid 16' and has as high a thermal conductivity as possible, such as Parylene film (trade name). The rest of the structure is the same as the conventional example, so the explanation will be omitted.
次に上記のように構成された本実施例の作用について説
明する。Next, the operation of this embodiment configured as described above will be explained.
仕切シ膜１５には予じめ複数、９枕１７が設けられてい
るが、上記構造を備えたハウジング３を基板１の上にか
ぶせたのち、ノ・ウジフグ３内の流体封入孔１９から流
体１６を仕切シ膜１５とハウジング３内面との間にし封
入すると、基板１の反シ、冷却構造全体の変形及び組立
時の寸法誤差は、仕切シ膜１５と流体１６との変形によ
って、各ＬＳＩチップ２の共通変位を吸収することがで
きる。また、流体１６の封入圧力をわずかに高めること
によｐ１各ＬＳＩチップ２と接する枕１７も少しづつ変
形し、各ＬＳＩチップ２の接続時のバラツキを吸収する
ことができる。このような状態に冷却構造が組み立てら
れると、ＬＳＩチップ２から発生する熱は複数の枕１７
を経て、仕切シ膜１５、流体１６、ハウジング３、冷却
水流路９と次々に伝わシ冷却される。各複数のＬＳＩチ
ップ２に複数の枕１７がおのおの独立に接触することが
できるため、冷却性能を著しく高めることができる。A plurality of nine pillows 17 are provided in advance on the partition membrane 15. After the housing 3 having the above structure is placed over the substrate 1, fluid is supplied from the fluid sealing hole 19 in the No-Uji puffer 3. 16 is sealed between the partition film 15 and the inner surface of the housing 3, deformation of the substrate 1, deformation of the entire cooling structure, and dimensional errors during assembly are caused by the deformation of the partition film 15 and the fluid 16, and each LSI A common displacement of the tip 2 can be absorbed. Furthermore, by slightly increasing the sealing pressure of the fluid 16, the pillow 17 in contact with each LSI chip 2 of p1 is also deformed little by little, making it possible to absorb variations in the connection of each LSI chip 2. When the cooling structure is assembled in such a state, the heat generated from the LSI chip 2 is transferred to the plurality of pillows 17.
The water is then transmitted to the partition membrane 15, the fluid 16, the housing 3, and the cooling water channel 9 in order to be cooled. Since the plurality of pillows 17 can contact each of the plurality of LSI chips 2 independently, the cooling performance can be significantly improved.
さらに、仕切り膜１５と基板１とで形成される空間領域
に、高熱伝導性の気体、たとえばヘリウムなどを充満さ
せると、枕１７とＬＳＩチップ２との接触熱抵抗を小さ
く抑えることができる。Furthermore, if the spatial region formed by the partition film 15 and the substrate 1 is filled with a highly thermally conductive gas such as helium, the contact thermal resistance between the pillow 17 and the LSI chip 2 can be kept small.
次に、本発明の他の実施例を第５図を参照して説明する
。第５図の例は、第４図の例の一変形であ乞第４図と同
一符号は同等部分を示している。Next, another embodiment of the present invention will be described with reference to FIG. The example shown in FIG. 5 is a modification of the example shown in FIG. 4, and the same reference numerals as in FIG. 4 indicate equivalent parts.
本例では、仕切シ膜２０は、枕１７をかこむように外周
部に蛇腹構造部２０ａを備えている。先の第４図の例で
、仕切り腹が金属箔としても、箔の可撓性は必ずしも大
きくないので、第５図の例では蛇腹構造部２０ａを設け
ることによって仕切り膜２０の変形能力を高めたもので
ある。In this example, the partition membrane 20 is provided with a bellows structure 20a on the outer periphery so as to surround the pillow 17. In the example shown in FIG. 4, even if the partition belly is made of metal foil, the flexibility of the foil is not necessarily large, so in the example shown in FIG. It is something that
次に、本発明のさらに他の実施例を第６図を参照して説
明する。第６図の例は、第４図または第５図の例の枕７
に対し工夫を加えたものであり、第４図と同一符号のも
のは同一部分を示している。Next, still another embodiment of the present invention will be described with reference to FIG. The example of FIG. 6 is the pillow 7 of the example of FIG. 4 or 5.
4, and the same reference numerals as in FIG. 4 indicate the same parts.
本例では、複数の枕１７内に流体１６′を充填しやすく
するため、仕切！１！１５を枕内封止流体１６′との接
触部に、介在部材に係る受け台２１を設けている。In this example, in order to make it easier to fill the plurality of pillows 17 with the fluid 16', partitions are used! 1!15 is provided with a pedestal 21 for an intervening member at the portion that comes into contact with the intra-pillow sealing fluid 16'.
次に、本発明のさらに他の実施例を第７図を参照して説
明する。第７図の例は、第６図の例と同−効果を期待す
る応用例であシ、第４図と同一符号のものは同一部分を
示している。Next, still another embodiment of the present invention will be described with reference to FIG. The example in FIG. 7 is an application example in which the same effect as the example in FIG. 6 is expected, and the same reference numerals as in FIG. 4 indicate the same parts.
本例では、複数の枕１７内に流体１６′を充填しやすく
するため、仕切シ膜１５／と枕内封止流体１６′との接
触部に、介在部材に係る凸部１５′ａを設けたもので、
凸部１５′ａは、仕切シ膜１５′にわずかな凹凸を形成
したものである。In this example, in order to easily fill the plurality of pillows 17 with the fluid 16', a convex portion 15'a related to the intervening member is provided at the contact portion between the partition membrane 15/ and the in-pillow sealing fluid 16'. With something that
The convex portion 15'a is formed by forming slight irregularities on the partition film 15'.
このような本発明の各実施例によれば、各ＬＳＩチップ
の変位を、基板全体の大きな変位と、各ＬＳＩチップ相
互の小さなバラツキとに分離して吸収することができる
。このため、各ＬＳＩチップとハウジング間の熱抵抗を
小さく抑えることができる。したがって、ＬＳＩチップ
の熱的信頼性が高められ、結局、半導体装置を用いる電
子機器全体の信頼性を上げることができる。According to each of the embodiments of the present invention, the displacement of each LSI chip can be absorbed by separating it into a large displacement of the entire substrate and a small variation among each LSI chip. Therefore, the thermal resistance between each LSI chip and the housing can be kept low. Therefore, the thermal reliability of the LSI chip is improved, and as a result, the reliability of the entire electronic device using the semiconductor device can be improved.
なお、前記の各実施例では、超大形コンピュータ等に用
いられるＬＳＩチップを備えた半導体装置の例を説明し
たが、本発明はＬＳＩチップのみに限らず、同等の効果
が期待できる半導体チップを備えた半導体装置の冷却構
造の範囲で汎用的なものである。In each of the above embodiments, an example of a semiconductor device equipped with an LSI chip used in a super-large computer etc. was explained, but the present invention is not limited to LSI chips only, but can also be applied to a semiconductor device equipped with a semiconductor chip that can be expected to have the same effect. This is a general-purpose cooling structure for semiconductor devices.
以上説明したように、本発明によれば、半導体装置の基
板の反シ、半導体チップの接続変位、冷却構造部の組立
時の変形や熱変形などさまざまの変位を吸収する機能を
備え、かつ、冷却性能のすぐれた冷却構造を備えた半導
体装置を提供することができる。As explained above, according to the present invention, the present invention has a function of absorbing various displacements such as warpage of a substrate of a semiconductor device, connection displacement of a semiconductor chip, deformation during assembly of a cooling structure, and thermal deformation, and A semiconductor device having a cooling structure with excellent cooling performance can be provided.
第１図は、従来例の冷却構造を備えた半導体装置の断面
図、第２図は、他の従来例の冷却構造を備えた半導体装
置の断面図、第３図は、さらに他の従来例の冷却構造を
備えた半導体装置の断面図、第４図は、本発明の一実施
例の冷却構造を備えた半導体装置の断面図、第５図は、
本発明の他の実施例の冷却構造を備えた半導体装置の断
面図、第６図、第７図は、いずれも本発明のさらに他の
実施例の冷却構造を備えた半導体装置の部分断面図であ
る。
１・・・基板、２・・・ＬＳＩテップ、３・・・ハウジ
ング、１５．１５’・・・仕切り膜、１５′ａ・・・凸
部、１６゜１６７、、・高熱伝導性流体、１７・・・枕
、２ｏ・・・仕切、！ｌｌｌ膜、２０ａ・・・蛇腹構造
部。
第 １ 図
万 Ｚ ロ
篤６（２］
￥５７ 口FIG. 1 is a cross-sectional view of a semiconductor device equipped with a conventional cooling structure, FIG. 2 is a cross-sectional view of a semiconductor device equipped with another conventional cooling structure, and FIG. 3 is still another conventional example. FIG. 4 is a cross-sectional view of a semiconductor device equipped with a cooling structure according to an embodiment of the present invention, and FIG.
A cross-sectional view of a semiconductor device equipped with a cooling structure according to another embodiment of the present invention, FIG. 6, and FIG. 7 are both partial cross-sectional views of a semiconductor device equipped with a cooling structure according to still another embodiment of the present invention. It is. DESCRIPTION OF SYMBOLS 1...Substrate, 2...LSI tip, 3...Housing, 15.15'...Partition film, 15'a...Protrusion, 16°167,...High thermal conductivity fluid, 17 ...Pillow, 2o...Partition,! lll membrane, 20a... bellows structure part. Figure 1 Man Z Ro Atsushi 6 (2) ¥57 Mouth
Claims (1)
と、この半導体チップを覆うように基板に装着されてい
るハウジングとからなる半導体装置において、前記基板
と前記ハウジングとで形成される空間領域を仕切るよう
に、かつ、前記半導体チップの上部を覆うように可撓性
のある仕切シ膜を設け、当該仕切シ膜と前記ハウジング
とで形成される空間領域に、流動性のある高熱伝導性流
体を充填し、さらに、前記仕切シ膜と前記半導体チップ
の背面との間に、流動性のある高熱伝導性流体を充填し
た複数の枕を、前記複数の半導体チップとおのおの独立
に接触するように配設したことを特徴とする冷却構造を
備えた半導体装置。 ２、特許請求の範囲第１項記載のものにおいて、仕切り
膜に蛇腹構造部を設けたものである冷却構造を備えた半
導体装置。 ３、特許請求の範囲第１項または第２項記載のもののい
ずれかにおいて、流動性のある高熱伝導性流体として、
低融点の液体金属を用いたものである冷却構造を備えた
半導体装置。 ４、％許請求の範囲第１項ないし第３項記載のもののい
ずれかにおいて、仕切り膜と基板とで形成される空間領
域に、高熱伝導性の気体を充満させたものである冷却構
造を備えた半導体装置。 ５、％許請求の範囲第１項ないし第４項記載のもののい
ずれかにおいて、仕切り膜と枕内封止流体との接触部に
、流体の充填を扶ける介在部材を設けたものである冷却
構造を備えた半導体装置。[Claims] 1. A semiconductor device comprising a substrate, a plurality of semiconductor chips mounted on the substrate, and a housing attached to the substrate so as to cover the semiconductor chips, wherein the substrate and the housing A flexible partition film is provided so as to partition a spatial region formed by the housing and to cover the upper part of the semiconductor chip, and a flexible partition film is provided so as to partition a spatial region formed by the housing. further, a plurality of pillows filled with a fluid and highly thermally conductive fluid are provided between the partition membrane and the back surface of the semiconductor chip, and the plurality of pillows are filled with a fluidly and highly thermally conductive fluid between the plurality of semiconductor chips; A semiconductor device equipped with a cooling structure characterized in that each semiconductor device is arranged so as to be in contact with each other independently. 2. A semiconductor device according to claim 1, which includes a cooling structure in which a bellows structure is provided on a partition film. 3. In either of claims 1 or 2, as a fluid and highly thermally conductive fluid,
A semiconductor device with a cooling structure that uses a liquid metal with a low melting point. 4.% In any one of claims 1 to 3, the space region formed by the partition film and the substrate is provided with a cooling structure that is filled with a highly thermally conductive gas. semiconductor device. 5.% Allowable Cooling device according to any one of claims 1 to 4, in which an intervening member is provided at the contact portion between the partition membrane and the sealing fluid in the pillow to assist in filling the fluid. A semiconductor device with a structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14103183A JPS6032348A (en) | 1983-08-03 | 1983-08-03 | Semiconductor device having cooling structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14103183A JPS6032348A (en) | 1983-08-03 | 1983-08-03 | Semiconductor device having cooling structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6032348A true JPS6032348A (en) | 1985-02-19 |
| JPH0342510B2 JPH0342510B2 (en) | 1991-06-27 |
Family
ID=15282604
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14103183A Granted JPS6032348A (en) | 1983-08-03 | 1983-08-03 | Semiconductor device having cooling structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6032348A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012256792A (en) * | 2011-06-10 | 2012-12-27 | Toshiba Corp | Heat dissipation structure |
| WO2014122875A1 (en) * | 2013-02-05 | 2014-08-14 | 株式会社デンソー | Method for manufacturing heat-dissipating structure |
-
1983
- 1983-08-03 JP JP14103183A patent/JPS6032348A/en active Granted
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012256792A (en) * | 2011-06-10 | 2012-12-27 | Toshiba Corp | Heat dissipation structure |
| WO2014122875A1 (en) * | 2013-02-05 | 2014-08-14 | 株式会社デンソー | Method for manufacturing heat-dissipating structure |
| JP2014170918A (en) * | 2013-02-05 | 2014-09-18 | Denso Corp | Method for manufacturing heat dissipation structure |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0342510B2 (en) | 1991-06-27 |
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