JPS6028223A - Manufacture of semiconductor crystal thin film - Google Patents
Manufacture of semiconductor crystal thin filmInfo
- Publication number
- JPS6028223A JPS6028223A JP13590683A JP13590683A JPS6028223A JP S6028223 A JPS6028223 A JP S6028223A JP 13590683 A JP13590683 A JP 13590683A JP 13590683 A JP13590683 A JP 13590683A JP S6028223 A JPS6028223 A JP S6028223A
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor
- thin film
- implanted
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/0242—Crystalline insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02694—Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
この発明は、ＳＯ８等絶縁性基板上の半導体結晶薄膜の
製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method for manufacturing a semiconductor crystal thin film on an insulating substrate such as SO8.
絶縁性基板、特に絶縁性単結晶基板上のシリコン膜を用
いた集積回路は、その構造上、高密度化、高速度化の点
において半導体基板を用いたものよりも有利である。反
面、基板上に異種の単結晶膜を成長させるためシリコン
膜には高密度の格子欠陥が存在するという欠点をもつ。Integrated circuits using a silicon film on an insulating substrate, particularly an insulating single crystal substrate, are structurally more advantageous than those using a semiconductor substrate in terms of higher density and higher speed. On the other hand, since a single crystal film of a different type is grown on a substrate, the silicon film has the disadvantage of having a high density of lattice defects.
例えばＳＯＳ （サファイア単結晶基板上のシリコン膜
）を用いてＭＯＳデバイスを製作しその基本特性を調べ
てみるとバルクシリコンのＭＯＳデバイスと比べ、ドレ
ーンリーク電流の増加、反転層移動度の低下が見られる
。前者はドレーン側近傍における生成再結合電流による
ものであシ、後者はシリコン膜に散乱中心が多いため、
キャリア担体が散乱することによって起こる。そして、
これらは共に格子欠陥に基因しているものであるためそ
の大幅な減少及び格子欠陥によってつくられる深い準位
を電気的に不活性化することが要求されている。For example, when we fabricated a MOS device using SOS (silicon film on a sapphire single crystal substrate) and investigated its basic characteristics, we found an increase in drain leakage current and a decrease in inversion layer mobility compared to bulk silicon MOS devices. It will be done. The former is due to recombination current generated near the drain side, and the latter is due to the large number of scattering centers in the silicon film.
This occurs due to scattering of the carrier. and,
Since these are both caused by lattice defects, it is required to significantly reduce them and to electrically inactivate the deep levels created by lattice defects.
本発明の目的は、半導体薄膜に存在する格子欠陥を減少
させると共に格子欠陥に基因する深い準位を電気的に不
活性化せしめる効果を与えることよシ、すぐれた特性を
もつ半導体装置用の絶縁性基板上の半導体結晶薄膜を得
ることにある。An object of the present invention is to reduce lattice defects existing in a semiconductor thin film and to provide an effect of electrically inactivating deep levels caused by lattice defects. The purpose of this invention is to obtain a semiconductor crystal thin film on a transparent substrate.
本発明は絶縁性基板上に形成した半導体結晶薄膜に該半
導体のハロゲン化合物をイオン注入し半導体膜の一部を
非晶質化した後、熱処理によシ該非晶質層を再結晶化さ
せ半導体膜に含まれていた格子欠陥を除去すると共に、
イオン注入されたハロゲン原子によシ格子欠陥における
不対電子を不活性化させることによシ半導体薄膜の電気
的特性を向上せしめるものである。In the present invention, a halogen compound of the semiconductor is ion-implanted into a semiconductor crystal thin film formed on an insulating substrate to make a part of the semiconductor film amorphous, and then the amorphous layer is recrystallized by heat treatment. In addition to removing lattice defects contained in the film,
The electrical characteristics of the semiconductor thin film are improved by inactivating unpaired electrons in the lattice defects by the ion-implanted halogen atoms.
本発明によれば、イオン注入による非晶質化とその後の
熱処理によって半導体膜中の格子欠陥密度が大巾に減少
すると共に未だ存在する格子欠陥によって形成される不
対電子はハロゲン原子によって不活性化され、この結果
、半導体薄膜の電気的特性はバルク半導体のそれとほぼ
同等のものになる。According to the present invention, the lattice defect density in the semiconductor film is greatly reduced by making it amorphous by ion implantation and subsequent heat treatment, and the unpaired electrons formed by the still existing lattice defects are inactivated by halogen atoms. As a result, the electrical properties of the semiconductor thin film become almost equivalent to those of the bulk semiconductor.
本発明の実施例について図面を参照して詳述する。第１
図に於いて絶縁性基板（１１）として（１１０，２）面
を有するサファイア単結晶基板を用いた。Embodiments of the present invention will be described in detail with reference to the drawings. 1st
In the figure, a sapphire single crystal substrate having a (110,2) plane was used as the insulating substrate (11).
その上にシリコン（Ｓｉ）膜（１２）を０．３μｍ堆積
した。成長方法は化学気相成長法（ＣＶＤ法）であり、
その条件を成長温度９５０℃、成長速度２μｍ ／ ｍ
ｉｎとすることによ、ｂ、（ｏｏｉ）シリコン単結晶膜
が形成される（第１図（ａ））。次にイオン種としてシ
リコンフッ素化合物（ＳｉＦ）を選び射影飛程（Ｒｐ）
がシリコン膜のほぼ中央部になるよう加速電圧を１７０
ｋＶに設定し、ドーズ量２×１０ｃｍ の条件において
シリコン膜（１２）へイオン注入し、シリコン表面側を
非晶質化（１３）する。A 0.3 μm thick silicon (Si) film (12) was deposited thereon. The growth method is chemical vapor deposition method (CVD method),
The conditions were a growth temperature of 950℃ and a growth rate of 2μm/m.
By setting in, a (ooi) silicon single crystal film is formed (FIG. 1(a)). Next, select silicon fluorine compound (SiF) as the ion species and calculate the projected range (Rp).
The acceleration voltage was set to 170° so that the
kV, and ions are implanted into the silicon film (12) at a dose of 2×10 cm 2 to make the silicon surface side amorphous (13).
（第１図（ｂ））。次に１０００℃、Ｎ２ガス雰囲気中
ニオいて２０分間熱処理を行い、非晶質シリコン層（１
３）ｆ：固相エピタキシャル的に再結晶化せしめる（第
１図（Ｃ））。(Figure 1(b)). Next, heat treatment was performed for 20 minutes at 1000°C in an N2 gas atmosphere, and the amorphous silicon layer (1
3) f: Recrystallize in a solid phase epitaxial manner (FIG. 1(C)).
このようにして得られた試料を用い、次にＭＯ８累子金
製作しその特性を評価した。試作方法はよく用いられて
いる多結晶シリコンゲート工程によった。Ｎチャ坏ル及
びＰチャネルＭＯ８）ランジスタにつき評価を行った結
果、キャリア移動度はＮチャネルトランジスタでは８０
０ ｃｍ２／ Ｖ−ｓｅｃ。Using the sample thus obtained, MO8 graded gold was then manufactured and its properties were evaluated. The prototype was manufactured using a commonly used polycrystalline silicon gate process. As a result of evaluating N-channel transistors and P-channel MO8) transistors, carrier mobility is 80 for N-channel transistors.
0 cm2/V-sec.
Ｐチャネルトランジスタでは２２０ ｃｍ” ／Ｖ・ｓ
ｅｃが得られ、従来の８０５Ｍ０８）ランジスタにおけ
るキャリア移動度４５０ ｃｍ２／Ｖ −５ｅｃ （Ｎ
テヤネ／ｌ／）、及び１８０ ｃｍ” ／Ｖ・ｓｅｃ
（Ｐチャネル）を大幅に上回ることが判明した。また、
ドレーンリーク電流も従来の５０８ＭＯ８）ランジスタ
における値１×１０ Ａ／μｍ１１から大幅に改善され
１×１２
１０ Ａ／μｍになった。このようにキャリア移動度及
びドレーンリーク電流が大幅に改良された理由として、
再結晶化したシリコン層における格子欠陥密度が減少す
ること及びフッ素が格子欠陥による不対電子を電気的に
不活性化することが考えられる。220 cm”/V・s for P-channel transistor
ec is obtained, and the carrier mobility in the conventional 805M08) transistor is 450 cm2/V -5ec (N
Teyane/l/), and 180 cm”/V・sec
(P channel). Also,
The drain leakage current was also significantly improved from the value of 1×10 A/μm11 in the conventional 508MO8) transistor to 1×1210 A/μm. The reason for the significant improvement in carrier mobility and drain leakage current is as follows.
It is thought that the lattice defect density in the recrystallized silicon layer decreases and that fluorine electrically inactivates unpaired electrons due to lattice defects.
上述した工程を経て得られたＳＯ８膜に対し、さらにシ
リコン界面側の結晶性をも改良するだめ第２図に示す工
程をとることができる。すなわち、ＳｉＦを加速エネル
ギー３５０ＫｅＶ１ ドーズ量１５ −２
Ｘ１０ｃｍ の条件でシリコン膜（２２）へイオン注入
する（第２図（ａ））。これによシリコン界面側が非晶
質（２３）される（第２図（ｂ））。次に１０００°Ｃ
Ｎ２ガス雰囲気中で２０分間熱処理を行ないシリコン表
面側から非晶質層（２３）を再結晶化する。この工程を
経た後、作られたＭＯ８素子特性ではドレーンリーク電
流が畜らに１桁低下する効果が得られた。In order to further improve the crystallinity of the silicon interface side of the SO8 film obtained through the steps described above, the steps shown in FIG. 2 can be performed. That is, SiF ions are implanted into the silicon film (22) at an acceleration energy of 350 KeV1 and a dose of 15 -2 x 10 cm (FIG. 2(a)). This makes the silicon interface side amorphous (23) (FIG. 2(b)). Then 1000°C
Heat treatment is performed for 20 minutes in an N2 gas atmosphere to recrystallize the amorphous layer (23) from the silicon surface side. After going through this process, the characteristics of the MO8 element produced had the effect of significantly reducing the drain leakage current by one order of magnitude.
この例においては、界面側、表面側それぞれ一回ずつイ
オン注入を行ったが、さらに同様な菌性でイオン注入、
熱処理工程を交互にくり返すことによって、よシ一層の
結晶性改善がなされる。In this example, ion implantation was performed once each on the interface side and the surface side.
Crystallinity can be further improved by repeating the heat treatment process alternately.
また、本発明実施後のシリコン単結晶膜上にさらにシリ
コン膜をエピタキシャル成長させることによって所望の
膜厚のシリコン単結晶膜を得ることもできる。Furthermore, a silicon single crystal film having a desired thickness can be obtained by further epitaxially growing a silicon film on the silicon single crystal film after implementing the present invention.
基板としては絶縁性単結晶基板であればよく、サファイ
ア（α−Ａｄｚｅｓ）以外にはスピネル（Ｍ、！９０
・Ａ／ｚＯｓ） 、酸化ベリリウム（ＢｅＯ）、シリカ
（α−８ｉ０２） 、二酸化トリウム（ＴｈＯｚ）など
が挙げられる。The substrate may be any insulating single crystal substrate, and in addition to sapphire (α-Adzes), spinel (M, !90
-A/zOs), beryllium oxide (BeO), silica (α-8i02), thorium dioxide (ThOz), and the like.
半導体薄膜としてはシリコンの他にジルマニウム、スズ
等があげられる。イオン注入条件は所望の非晶質層を形
成できる条件であればよく、イオン種はＳｉＦの他に５
ｉＦｚ、５ｉＦａ等の５ｉ−Ｆ系。Examples of the semiconductor thin film include zirmanium, tin, and the like in addition to silicon. The ion implantation conditions may be any conditions as long as they can form the desired amorphous layer, and the ion species may be 5 in addition to SiF.
5i-F series such as iFz and 5iFa.
８ｉ（４，ＳｉＣ］ｚの５ｉ−Ｃ１系及び、５ｉ−Ｉ系
化合物を用いてもよいことはもちろんである。また他の
半導体に対してもそのハロゲン系化合物を用いればよい
。熱処理温度は再結晶化が起こる温度であればよく５０
０℃以上での炉処理、あるいはレーザ、電子線等の工坏
ルギービーム照射であってもよい。また熱処理雰凹気は
Ｎ２ガス、０２ガス、Ａｒガス等の不活性ガスそれぞれ
において同様な効果が認められた。シリコン膜形成法は
ＣＶＤ法に限らず、真空蒸着法、分子線エピタキシャル
法などがある。Of course, the 5i-C1 and 5i-I compounds of 8i(4,SiC]z may be used.The halogen compounds may also be used for other semiconductors.The heat treatment temperature is 50 as long as the temperature at which recrystallization occurs
Furnace treatment at 0° C. or higher, or irradiation with a mechanical energy beam such as a laser or an electron beam may be used. Furthermore, similar effects were observed in the heat treatment atmosphere using inert gases such as N2 gas, 02 gas, and Ar gas. The silicon film forming method is not limited to the CVD method, but includes a vacuum evaporation method, a molecular beam epitaxial method, and the like.
第１図（ａ）〜（Ｃ）は本発明の一実施例を説明するた
めの工程断面図、第２図（ａ）〜（Ｃ）は本発明の他の
実施例を説明するための工程断面図である。
図において、
１１．２１・・・サファイア基板、１２．２２・・・シ
リコン単結晶膜、１３．２３・・・非晶質シリコン層、
１４．２４・・・再結晶化シリコン層。
代理人 弁理士 則 近 憲 佑 （ほか１名）第１図
第 ２ 図FIGS. 1(a) to (C) are process sectional views for explaining one embodiment of the present invention, and FIGS. 2(a) to (C) are process sectional views for explaining another embodiment of the present invention. FIG. In the figure, 11.21... Sapphire substrate, 12.22... Silicon single crystal film, 13.23... Amorphous silicon layer,
14.24... Recrystallized silicon layer. Agent Patent Attorney Kensuke Chika (and 1 other person) Figure 1 Figure 2
Claims (1)
晶質化する工程と、その後熱処理によシ該非晶質領域を
再結晶化せしめる工程とを含んでおシ、かつ該イオン注
入におけるイオン種として該半導体の構成元素のハロゲ
ン化合物を用いることを特徴とする半導体結晶薄膜の製
造方法。(1) The method includes a step of making a semiconductor thin film on an insulating substrate amorphous by ion implantation, and a step of recrystallizing the amorphous region by subsequent heat treatment, and ions in the ion implantation. A method for producing a semiconductor crystal thin film, characterized in that a halogen compound of a constituent element of the semiconductor is used as a seed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13590683A JPS6028223A (en) | 1983-07-27 | 1983-07-27 | Manufacture of semiconductor crystal thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13590683A JPS6028223A (en) | 1983-07-27 | 1983-07-27 | Manufacture of semiconductor crystal thin film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6028223A true JPS6028223A (en) | 1985-02-13 |
| JPH0570928B2 JPH0570928B2 (en) | 1993-10-06 |
Family
ID=15162589
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13590683A Granted JPS6028223A (en) | 1983-07-27 | 1983-07-27 | Manufacture of semiconductor crystal thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6028223A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6693324B2 (en) * | 1996-04-26 | 2004-02-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a thin film transistor and manufacturing method thereof |
| KR100843741B1 (en) | 2007-03-31 | 2008-07-04 | 동국대학교 산학협력단 | Method for preparing a silicon on sapphire thin film |
-
1983
- 1983-07-27 JP JP13590683A patent/JPS6028223A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6693324B2 (en) * | 1996-04-26 | 2004-02-17 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having a thin film transistor and manufacturing method thereof |
| KR100843741B1 (en) | 2007-03-31 | 2008-07-04 | 동국대학교 산학협력단 | Method for preparing a silicon on sapphire thin film |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0570928B2 (en) | 1993-10-06 |
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