JPS59155121A - Manufacture of semiconductor thin film - Google Patents

Manufacture of semiconductor thin film

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Publication number
JPS59155121A
JPS59155121A JP58030077A JP3007783A JPS59155121A JP S59155121 A JPS59155121 A JP S59155121A JP 58030077 A JP58030077 A JP 58030077A JP 3007783 A JP3007783 A JP 3007783A JP S59155121 A JPS59155121 A JP S59155121A
Authority
JP
Japan
Prior art keywords
silicon layer
layer
silicon
annealing
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58030077A
Other languages
Japanese (ja)
Inventor
Hiroshi Kobayashi
博 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP58030077A priority Critical patent/JPS59155121A/en
Publication of JPS59155121A publication Critical patent/JPS59155121A/en
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02598—Microstructure monocrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02675—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using laser beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain the single crystal of excellent crystallizing property by a method wherein an energy beam is made to irradiate after polycrystalline silicon layer has been made amorphous by implanting a silicon ion. CONSTITUTION:An SiO2 film 12 is deposited on the surface of an N type (100) plane direction single crystal silicon substrate 11, and a polycrystalline silicon film 13 is deposited thereon. Then, a silicon ion 14 is implanted in the polycrystalline silicon film 13, and the polycrystalline silicon film 13 is made amorphous. An energy beam 15 such as an electron beam, a laser beam, a xenon lamp light and the like is made to irradiate on said silicon film 13 which is made amorphous, an annealing is performed thereon, and the silicon film 13 is single-crystallized.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明は、半導体薄膜の製造方法に係り、特に絶縁性基
体上に粗大粒化または単結晶化したシリコン薄膜を形成
する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor thin film, and particularly to a method for forming a coarse-grained or single-crystal silicon thin film on an insulating substrate.

〔発明の技術的背景およびその問題点〕近年、半導体装
置の高密度化、高集積化の要請から、半導体素子を多層
化するいわゆる三次元ＩＣが注目されている。[Technical Background of the Invention and Problems Therewith] In recent years, due to the demand for higher density and higher integration of semiconductor devices, so-called three-dimensional ICs in which semiconductor elements are multilayered have been attracting attention.

一般に、単結晶シリコン層の形成法としては、エピタキ
シャル法やＳＯ８などの気相法が広く用いられており、
また、単結晶シリコン基板上にまず多結晶シリコン層を
形成した後にこの層にアニーリングを施すことによシ単
結晶化する方法、あるいは、上記多結晶シリコン層をイ
オン注入によりアモルファス化した後に加熱アニーリン
グによりこれを単結晶化する方法（たとえば、特開昭５
２−１３６５６８号公報に記載のもの）が提案されてい
る。In general, epitaxial methods and gas phase methods such as SO8 are widely used as methods for forming single crystal silicon layers.
Alternatively, a method of first forming a polycrystalline silicon layer on a single crystal silicon substrate and then annealing this layer to form a single crystal, or a method of making the polycrystalline silicon layer amorphous by ion implantation and then heating annealing. A method of making it into a single crystal by using
2-136568) has been proposed.

しかしながら、半導体素子を多層化する工程における単
結晶シリコン薄膜の形成法として、上記公知の方法は必
ずしも満足のいくものではない。However, the above-mentioned known methods are not necessarily satisfactory as methods for forming single-crystal silicon thin films in the process of multilayering semiconductor devices.

通常、半導体素子を三次元化するためには、既に形成さ
れている半導体素子上にｓｉｏ□やＳＩＮなどからなる
絶縁層を形成し、この絶縁層上にさらに単結晶シリコン
層を形成する必要がある。ところが、上記従来の方法で
は、絶縁層上に形成された多結晶シリコン層が単結晶化
する確率は小さく、また単結晶化されたシリコン層中に
は多数の転位、双晶あるいは積層欠陥などが含まれてお
り、結晶性の良好なシリコン層を得ることは困難であっ
た。Normally, in order to make a semiconductor device three-dimensional, it is necessary to form an insulating layer made of sio□ or SIN on the already formed semiconductor device, and then to form a single crystal silicon layer on top of this insulating layer. be. However, in the conventional method described above, the probability that the polycrystalline silicon layer formed on the insulating layer becomes single crystal is small, and the single crystal silicon layer has many dislocations, twins, stacking faults, etc. It was difficult to obtain a silicon layer with good crystallinity.

さらにまた、従来法で形成されたシリコン層は、その表
面に比較的大きな凹凸が生じ、そのため素子のパターニ
ング精度が大きく制限されるという欠点を有する。Furthermore, silicon layers formed by conventional methods have the disadvantage that relatively large irregularities occur on their surfaces, which greatly limits the patterning accuracy of devices.

〔発明の目的〕[Purpose of the invention]

本発明は、上記欠点に鑑みてなされたものであり、絶縁
性基体上に、結晶性の良好な単結晶あるいは粗大粒化し
たシリコン薄膜を形成する方法を提供することを目的と
し、特に、素子の三次元的集積化に好適な単結晶シリコ
ン薄膜の製造法を提供することを目的とする。The present invention has been made in view of the above-mentioned drawbacks, and an object of the present invention is to provide a method for forming a single crystalline or coarse-grained silicon thin film with good crystallinity on an insulating substrate. An object of the present invention is to provide a method for manufacturing a single crystal silicon thin film suitable for three-dimensional integration.

〔発明の概要〕[Summary of the invention]

本発明者は、絶縁層上に形成された多結晶シリコン層を
同相法によシ単結晶シリコン層に変換するに際し、良好
な結晶性を持つシリコン層を得るための条件を研究して
いった結果、次のような知見を見出した。The present inventor studied the conditions for obtaining a silicon layer with good crystallinity when converting a polycrystalline silicon layer formed on an insulating layer into a single-crystalline silicon layer using the in-phase method. As a result, the following findings were discovered.

まず第一に、多結晶シリコン層にシリコンイオンを注入
して該層をアモルファス化し、さらにこれを再結晶化す
るためのアニーリング法としてエネルギービーム照射を
用いることが特に有効であること、第二に、イオン注入
とアニーリングとをシリコン層の下層と上層の２段に分
けて行うことにより結晶性が著しく向上し、この場合の
アニーリング法は比較的低温の加熱によるアニールが特
に好適であること、さらに上記イオン注入とアニーリン
グ工程とを繰り返して行なうか、あるいは、アニーリン
グ法としてエネルギービーム照射を組み合わせて用いる
ことが特に有効であること、である。Firstly, it is particularly effective to use energy beam irradiation as an annealing method for implanting silicon ions into a polycrystalline silicon layer to make the layer amorphous and then recrystallizing it.Secondly, , crystallinity is significantly improved by performing ion implantation and annealing in two stages, the lower layer and the upper layer of the silicon layer, and in this case, annealing by heating at a relatively low temperature is particularly suitable; It is particularly effective to repeat the ion implantation and annealing steps, or to use a combination of energy beam irradiation as an annealing method.

すなわち、本発明の半導体薄膜の製造方法の第一の好ま
しい態様は、絶縁層上に多結晶シリコン層を形成し、次
いで上記多結晶シリコン層にシリコンイオンをイオン注
入することによシ該多結晶シリコン層を−Ｈアモルファ
ス化し、次いで上記アモルファス化したシリコン層にエ
ネルギービーム照射によるアニーリングを施すことによ
って該シリコン層を単結晶シリコン層に変換すること、
を特徴とするものであり、第二の好ましい態様は、絶縁
層上に多結晶シリコン層を形成し、このシリコン層の下
層部に不純物プロファイルのピークをもつように該シリ
コン層にシリコンイオンをイオン注入し、このシリコン
イオンの注入されたシリコン層に比較的低温度の加熱に
よるアニーリングを施し、次いで上記アニーリングの施
されたシリコン層の上層部に不純物プロファイルのピー
クをもつように該シリコン層にシリコンイオン このシリコンイオンの注入されたシリコン層に比較的低
温度の加熱によるアニーリングを施すこと、を特徴とす
るものであり、本発明の第三の好ましい態様は、絶縁層
上に多結晶シリコン層を形成し、このシリコン層の下層
部に不純物プロフッイルのピークをもつように該シリコ
ン層にシリコンイオンをイオン注入し、このシリコンイ
オンの注入されたシリコン層に比較的低温度の加熱によ
るアニーリングを施し、次いで上記アニーリングの施さ
れたシリコン層の上層部に不純物プロファイルのピーク
をもつように該シリコン層にシリコンイオンをイオン注
入し、このシリコンイオンの注入されたシリコン層に比
較的低温度の加熱による熱アニーリングを施し、さらに
このシリコン層にエネルギービーム照射によるアニーリ
ングを施すこと、を特徴とするものである。That is, the first preferred embodiment of the method for manufacturing a semiconductor thin film of the present invention is to form a polycrystalline silicon layer on an insulating layer, and then implant silicon ions into the polycrystalline silicon layer to form a polycrystalline silicon layer. converting the silicon layer into a single crystal silicon layer by making the silicon layer -H amorphous and then annealing the amorphous silicon layer by energy beam irradiation;
In a second preferred embodiment, a polycrystalline silicon layer is formed on the insulating layer, and silicon ions are ionized into the silicon layer so that the impurity profile has a peak in the lower layer of the silicon layer. The silicon layer into which the silicon ions have been implanted is annealed by heating at a relatively low temperature, and then silicon is added to the silicon layer so that the impurity profile has a peak in the upper layer of the annealed silicon layer. A third preferred embodiment of the present invention is characterized in that the silicon layer into which the silicon ions are implanted is annealed by heating at a relatively low temperature. forming a silicon layer, implanting silicon ions into the silicon layer so that the impurity profile has a peak in the lower layer of the silicon layer, and annealing the silicon layer into which the silicon ions have been implanted by heating at a relatively low temperature, Next, silicon ions are implanted into the silicon layer so that the impurity profile has a peak in the upper layer of the annealed silicon layer, and the silicon layer into which the silicon ions are implanted is heated at a relatively low temperature. This method is characterized by performing annealing and further performing annealing by irradiating the silicon layer with an energy beam.

〔発明の実施例〕[Embodiments of the invention]

以下、添付図面を参照して本発明の実施例について説明
する。Embodiments of the present invention will be described below with reference to the accompanying drawings.

実施例１ 第１図に、本発明の第１の好ましい実施例とし・て、製
造工程の断面図を示す。Embodiment 1 FIG. 1 shows a cross-sectional view of the manufacturing process as a first preferred embodiment of the present invention.

まず、第１図（、）で示すように、たとえばＮ型（１０
０）面方位の単結晶シリコン基板１１の表面に、絶縁膜
として膜厚約０．８μｍのＳｔＯ□膜１２全１２する。First, as shown in Fig. 1(, ), for example, N type (10
0) A StO□ film 12 having a thickness of approximately 0.8 μm is formed as an insulating film on the surface of a single crystal silicon substrate 11 having a plane orientation.

ここで、シリコン基板１１には、既に所望の素子が公知
の工程を経て形成されていてもよい。次いで、第１図（
ｂ）で示すように、多結晶シリコン膜１３をＣＶＤ法等
により、たとえば４００ＯＡの膜厚に堆積する。次いで
、第１図（ｃ）に示すように、多結晶シリコン膜１３に
、加速電圧１００Ｋｖ１Ｐ−ス量Ｉ　Ｘ　１０１６１　
ｏｎｓ　／ａｍ２　　の条件でシリコンイオン（、Ｓｉ
＋）１４のイオン注入を行う。このイオン注入によって
多結晶シリコン膜１３はアモルファス化する。Here, desired elements may already be formed on the silicon substrate 11 through a known process. Next, Figure 1 (
As shown in b), a polycrystalline silicon film 13 is deposited to a thickness of, for example, 400 OA by CVD or the like. Next, as shown in FIG. 1(c), the polycrystalline silicon film 13 is applied with an accelerating voltage of 100 Kv1P-amount of space I x 10161
silicon ions (, Si
+) Perform 14 ion implantations. By this ion implantation, the polycrystalline silicon film 13 becomes amorphous.

次いで、第１図（ｄ）に示すように、アモルファス化し
たシリコン膜１３にエネルギービーム照射によるアニー
リングを行う。エネルギービーム１５としては、たとえ
ば電子ビーム、レーザ光、キセノンランプ光などが用い
られ得る。電子ビームを用いた場合のアニーリング条件
は、加速電圧１０　ＫＶ、電子銃フィラメントの電流１
　、０ｍＡとし、またビームスポット径は７０−（資）
μｍであり、ビーム走査速度は、４０　ａｍ／ｓｅｅ　
、　　ビームの送シピツチは６μｍであった。Next, as shown in FIG. 1(d), the amorphous silicon film 13 is annealed by energy beam irradiation. As the energy beam 15, for example, an electron beam, laser light, xenon lamp light, etc. can be used. When using an electron beam, the annealing conditions are: acceleration voltage 10 KV, electron gun filament current 1
, 0mA, and the beam spot diameter is 70-(capital)
μm, and the beam scanning speed is 40 am/see
The beam transmission pitch was 6 μm.

このようにして、単結晶化されたシリコン薄膜１３ａが
得られる。得られたシリコン薄膜の結晶性は良好であっ
た。In this way, a single crystal silicon thin film 13a is obtained. The obtained silicon thin film had good crystallinity.

実施例２ 第２図に、本発明の第２の好ましい態様に係る製造工程
の断面図を示す。Example 2 FIG. 2 shows a cross-sectional view of a manufacturing process according to a second preferred embodiment of the present invention.

まず、上記実施例１と同様にして、単結晶シリコン基板
２１の表面に膜厚約０．８μｍの絶縁膜（ＳｔＯ□膜）
２２および膜厚４０００Ａの多結晶シリコン膜ｎを積層
する（第２図（、）および（ｂ））。次に、第２図（Ｃ
）に示すように、多結晶シリコン全回の下層部に不純物
プロファイルをもつように、たとえばＳｌ＋イオンを、
加速電圧１８０ＫＶ、ｒ−ス量ｌＸｌ０１ｏｎｓ／　ｃ
ｍ　２の条件でイオン注入する。このイオン注入によっ
て多結晶シリコン全回の主として下層部がアモルファス
化する。First, in the same manner as in Example 1, an insulating film (StO□ film) having a thickness of about 0.8 μm is formed on the surface of a single crystal silicon substrate 21.
22 and a polycrystalline silicon film n having a film thickness of 4000 Å are laminated (FIGS. 2(a) and (b)). Next, Figure 2 (C
), for example, by adding Sl+ ions to have an impurity profile in the lower layer of polycrystalline silicon.
Acceleration voltage 180KV, r-surge amount lXl01ons/c
Ion implantation is performed under the condition of m2. By this ion implantation, mainly the lower layer portion of the entire polycrystalline silicon becomes amorphous.

次いで、第２図（ｄ）に示すように、比較的低温度の熱
アニーリングを行うことによ５、ｓｔ　　イオンが注入
されたシリコン層の下層部２３ａの結晶粒径の粗大化が
起こる。この熱アニーリングは、５００〜１０００℃の
温度範囲で行うと左が好ましく、よシ好ましくは、７０
０℃、数時間、Ｎ２雰囲気中で行われる。Next, as shown in FIG. 2(d), by performing thermal annealing at a relatively low temperature, the crystal grain size of the lower layer portion 23a of the silicon layer into which the 5.st 2 ions have been implanted is coarsened. This thermal annealing is preferably carried out at a temperature range of 500 to 1000°C, more preferably 70°C.
The test is carried out at 0° C. for several hours in a N2 atmosphere.

次いで、第２図（、）に示すように、今度は多結晶シリ
コン膜乙の上層部にプロファイルビークをもつようにｓ
ｔ”イオンの注入を行う。注大東件としては、イオン加
速電圧５０　ＫＶ、　　ドーズ量ｌＸｌ０”ｌｏｎｇ／
ａｍが好ましい。Next, as shown in FIG.
t'' ion implantation is performed.As a precaution, the ion acceleration voltage is 50 KV, and the dose is lXl0''long/
am is preferred.

次いで、上記イオン注入終了後、熱アニーリングを行う
。この場合の温度も５００〜１０００℃の範囲が好まし
く、さらに好ましくは、７００℃の温度で数時間、Ｎ２
雰囲気中で行われる。この熱アニーリングによシ、Ｓ１
＋イオンが注入された上層部を中心とした結晶粒径の粗
大化が起こるが、この時、下層部の粗大化された結晶粒
径はさらに粗大化し、またこれによシ上層部の結晶粒の
粗大化が促進される。Next, after the ion implantation is completed, thermal annealing is performed. The temperature in this case is also preferably in the range of 500 to 1000°C, and more preferably, the temperature is 700°C for several hours.
It takes place in an atmosphere. Through this thermal annealing, S1
The crystal grain size becomes coarser mainly in the upper layer where + ions are implanted, but at this time, the coarsened crystal grain size in the lower layer becomes even coarser, and as a result, the crystal grain in the upper layer becomes coarser. coarsening is promoted.

このようにして、粗大粒化あるいは単結晶化したシリコ
ン層２３ｂが得られた。In this way, a coarse-grained or single-crystal silicon layer 23b was obtained.

結晶粒径は、堆積した当初が数百へであり、上記イオン
注入および熱アニーリング処理後に数千Ａに変化してい
ることから、約１０倍の大きさになることが確認された
。The crystal grain size was several hundred when deposited, and changed to several thousand amps after the ion implantation and thermal annealing treatment, so it was confirmed that the crystal grain size was about 10 times larger.

さらに上記第２図（Ｃ）〜（ｆ）の工程をくり返して行
うと結晶粒径は約１．５〜２μｍとなり、上述したイオ
ン注入と熱アニーリング工程をくシ返すことは結晶粒径
を粗大化する上で好ましいことが認められた。また、シ
リコン層の上層部の粗大化を行った後に下層部の処理を
行なっても同様の効果を得ることができるが、本実施例
のように下層部の処理を最初に行った方が結晶性の良好
なものが得られた。Furthermore, if the steps shown in FIG. 2 (C) to (f) are repeated, the crystal grain size will be approximately 1.5 to 2 μm, and repeating the ion implantation and thermal annealing steps described above will coarsen the crystal grain size. It was recognized that this is preferable in terms of Although the same effect can be obtained by processing the lower layer after coarsening the upper layer of the silicon layer, it is better to process the lower layer first as in this example. A product with good properties was obtained.

本実施例では、上記第２図（Ｃ）、（ｄ）、（、）およ
び（ｆ）の工程を各々−回のみ行うことによって、従来
法によるものより結晶性の改善されたシリコン膜を得る
ことができた。たとえば、多結晶シリコン層が粗大化あ
るいは単結晶化されるウエノ・面内の確率は、（資）〜
９０％と増大し、また転位、双晶、積層欠陥などが減少
し、さらにパターニング精度も向上した。In this example, by performing the steps in FIGS. 2(C), (d), (, ), and (f) only one time each, a silicon film with improved crystallinity than that obtained by the conventional method is obtained. I was able to do that. For example, the in-plane probability that a polycrystalline silicon layer will become coarse or single crystal is
90%, dislocations, twins, stacking faults, etc. were reduced, and patterning accuracy was also improved.

実施例３ 第３図に、本発明の第３の好ましい態様に係る製造工程
の断面図を示す。Example 3 FIG. 3 shows a cross-sectional view of a manufacturing process according to a third preferred embodiment of the present invention.

前記実施例２と同様にして、単結晶シリコン基板３１の
表面に膜厚約０．８μｍのＳｔＯ□膜３２膜上２膜厚４
００ＯＡの多結晶シリコン膜おを積層する（第３図（、
）および（ｂ））。次いで、前記実施例２と同様の条件
で、シリコン膜３３の下層部にＳｔ　　イオ／を注入し
く第３図（ｃ）　）　、さらに熱アニーリングを行うこ
とによりシリコン膜下層部の結晶粒径を粗大化する（第
３図（ｄ））。次いで、今度はシリコン層おの上層部に
Ｓｔ＋イオンを注入しく第３図（ｅ））、さらに熱アニ
ーリングによりシリコン層上層部と下層部の結晶粒径の
粗大化を行う（第３図（ｆ））。In the same manner as in Example 2, a StO□ film 32 with a thickness of about 0.8 μm was deposited on the surface of the single crystal silicon substrate 31.
A polycrystalline silicon film of 00 OA is laminated (see Figure 3).
) and (b)). Next, under the same conditions as in Example 2, St ions were implanted into the lower layer of the silicon film 33 (Fig. 3(c)), and further thermal annealing was performed to coarsen the crystal grain size of the lower layer of the silicon film. (Fig. 3(d)). Next, St+ ions are implanted into the upper part of the silicon layer (Fig. 3(e)), and the crystal grain size of the upper and lower parts of the silicon layer is coarsened by thermal annealing (Fig. 3(f)). )).

次いで、第３図（ｇ）に示すように、結晶粒径の粗大化
したシリコン膜３３にエネルギービーム３５を照射する
ことによシアニーリングを行う。エネルギービームとし
ては、電子ピーみ、レーザー光、キセノンランプ光など
が用いられ得る。電子ビームを用いた場合のアニーリン
グ条件は、加速電圧１ＯＫＶ　、電子銃フィラメントの
電流１　、０ｍＡとし、またビームスポット径は７０〜
８０μｍであり、ビーム走査速度は４００ｍ　／１ｓｅ
ｃ、　　ビームの送りピッチは６μｍであった。Next, as shown in FIG. 3(g), cyannealing is performed by irradiating the silicon film 33 with the coarsened crystal grain size with an energy beam 35. As the energy beam, electron beam, laser light, xenon lamp light, etc. can be used. When using an electron beam, the annealing conditions are an accelerating voltage of 1 OKV, an electron gun filament current of 1, 0 mA, and a beam spot diameter of 70 ~
80μm, beam scanning speed 400m/1se
c. The beam sending pitch was 6 μm.

このようにして単結晶化されたシリコン薄膜３３ａが得
られ、その結晶性は良好であった。従来法によるものと
比較し、多結晶シリコン層が粗大化あるいは単結晶化さ
れるウエノ・面内の確率は、（資）〜９０％と増大し、
また転位、双晶、積層欠陥などが減少し、さらにノリー
二ング精度も向上した。A single-crystal silicon thin film 33a was thus obtained, and its crystallinity was good. Compared to conventional methods, the probability that the polycrystalline silicon layer will become coarse or monocrystalline is increased to ~90%.
In addition, dislocations, twins, stacking faults, etc. have been reduced, and nodding accuracy has also been improved.

実施例４ 第４図に、本発明を積層型ＣＭＯＳインバータに適用し
た場合の断面図を示し、その製造′／Ｊ礎について説明
する。Embodiment 4 FIG. 4 shows a cross-sectional view of the case where the present invention is applied to a stacked CMOS inverter, and its manufacturing basis will be explained.

まずＰ型Ｓ％基板４１上の素子として用いる部分以外の
部分（すなわちフィールド部分）を常法に従い酸化し、
酸化膜４２を形成する。次いで、この酸化膜４２によっ
て囲まれた８１基板表面を１０００°Ｃの酸化雰囲気中
で酸化し、膜厚２５０Ａのゲート酸化膜４３を成長させ
る。この状態で必要に応じて、トランジスタのしきい値
電圧コントロールのためのイオン注入を行う。First, a portion of the P-type S% substrate 41 other than the portion used as an element (ie, a field portion) is oxidized according to a conventional method.
An oxide film 42 is formed. Next, the surface of the substrate 81 surrounded by this oxide film 42 is oxidized in an oxidizing atmosphere at 1000° C. to grow a gate oxide film 43 with a thickness of 250 Å. In this state, if necessary, ion implantation is performed to control the threshold voltage of the transistor.

次いで、全面に３００ＯＡ厚のｐｔｓｉ膜をス、ｅツタ
法によシ被着し、写真蝕刻法によシ／ソターニングを行
ってゲート電極４４を形成する。その後、１×１０１５
ｔｏｎｓ、／Ｃｍ２のＡ８イオンを４０　ＫＶの条件で
イオン注入し、８１基板中にＮ型領域４５ａおよび４５
ｂを形成する。次に、既に形成したゲート電極４４をマ
スクとして苧化膜４３を所望形状にエツチングする。Next, a PTSI film with a thickness of 300 OA is deposited on the entire surface by a sputtering method, and a gate electrode 44 is formed by photolithography and soturning. Then 1×1015
tons, /Cm2 of A8 ions were implanted under 40 KV conditions to form N-type regions 45a and 45 into the 81 substrate.
form b. Next, using the already formed gate electrode 44 as a mask, the mulch film 43 is etched into a desired shape.

次いで、全面にｐｔ膜をスパッタ法により被着し、写真
蝕刻法によりＡｆｉ−ニングしてｐｔ膜４６ａおよび４
６ｂを形成する。さらにＣＶＤ法により、全面に２５Ｏ
Ａ厚のＳｔＯ□膜４７全４７させ、その所望部分゛に、
写真蝕刻法によりスルーホール４８を形成する。次いで
再びＣＶＤ法によ！ｌ）　４０００Ａ厚の多結晶シリコ
ン膜４９を堆積し、前記実施何重ないし実施例３と同様
の方法で該多結晶シリコン膜４９を単結晶化する。この
単結晶化の過程におけるアニールによって、既に被着さ
れているｐｔ膜４６ａおよび４６ｂはＮ型領域４５ａお
よび４５　ｂと反応し、ＰｔＳｉ層となる。Next, a PT film is deposited on the entire surface by sputtering, and Afi-etching is performed by photolithography to form the PT films 46a and 4.
Form 6b. Furthermore, by CVD method, 25O
A StO□ film 47 with a thickness of
A through hole 48 is formed by photolithography. Next, use the CVD method again! l) A polycrystalline silicon film 49 having a thickness of 4000 Å is deposited, and the polycrystalline silicon film 49 is made into a single crystal by the same method as in the above-mentioned embodiments or in Example 3. By annealing during this single crystallization process, the already deposited PT films 46a and 46b react with the N-type regions 45a and 45b, forming a PtSi layer.

次いで、写真蝕刻法により不用部分を除去し、シリコン
膜４９と８１基板中のＮ型領域４５とはスルーホール４
８およびＰｔ５１層４６を介して接触することとなる。Next, unnecessary portions are removed by photolithography, and the silicon film 49 and the N-type region 45 in the substrate 81 are formed into through holes 4.
8 and Pt51 layer 46.

この状態で、必要に応じてイオン注入を行い、単結晶化
されたシリコン膜によって形成されるトランジスタのし
きい値コントロールを行う。In this state, ion implantation is performed as necessary to control the threshold value of the transistor formed of the single crystal silicon film.

次に、フォトレジスト膜を選択的に形成してＩＸＩＯ１
５１ｏｎｇ／ａｍ２のポロンを４０　ＫＶの注入エネル
ギーでイオン注入する。イオン注入されたボロンイオン
は、その際、熱処理により活性化され、Ｐ型頭域５０ｇ
、５０ｂが形成される。Next, a photoresist film is selectively formed to
51 ng/am2 of poron is ion-implanted with an implant energy of 40 KV. At that time, the implanted boron ions are activated by heat treatment, resulting in a P-type head area of 50 g.
, 50b are formed.

次いで、ＣＶＤ法により全面に８００ＯＡ厚のＳｉＯ２
膜５１全５１し、さらにコンタクトホールを開孔してＡ
Ｉ配線部５２を形成することによシ積層形ＣＭＯＳイン
バータが完成する。Next, SiO2 with a thickness of 800 OA is deposited on the entire surface by CVD method.
The entire film 51 is removed, and a contact hole is further opened to form A.
By forming the I wiring section 52, a stacked CMOS inverter is completed.

このようにして得られた積層形ＣＭＯ８インノ々−タの
リーク電流特性は極めて良好であった。第５図は、従来
法で製造されたもののリーク電流特性図であり、第６図
は、本発明のリーク電流特性図である。これらの図から
明らかなように、本発明を用いた場合リーク電流はきれ
いなパルス状となり、従来法によるものより良好な特性
を示した。The leakage current characteristics of the laminated CMO8 inverter thus obtained were extremely good. FIG. 5 is a leakage current characteristic diagram of a product manufactured by a conventional method, and FIG. 6 is a leakage current characteristic diagram of the present invention. As is clear from these figures, when the present invention was used, the leakage current had a neat pulse shape, showing better characteristics than those using the conventional method.

さらに、本発明によって製造されたＰチャネルＭＯ８Ｆ
ＥＴと従来法によるＰチャネルＭＯ８ＦＩＴとの移動度
μｐを比較すると、従来法によるものがｐｐ　＝　４０
．５０　ａｍ２／　ｆ８であり、本発明によるものがＪ
ＩＩＰ　＝　１３０〜１４０　ａｍ２／Ｖ−８であシ、
本発明によれば移動度が大巾に向上することが認められ
、さらに再現性も従来のＥＦＴ　より良好であった。Furthermore, P-channel MO8F manufactured according to the present invention
Comparing the mobility μp between ET and the conventional P-channel MO8FIT, the conventional method has pp = 40.
．． 50 am2/f8, and the one according to the present invention is J
IIP = 130-140 am2/V-8,
According to the present invention, it was recognized that the mobility was greatly improved, and the reproducibility was also better than that of the conventional EFT.

さらに本発明は、上記のような三次元ＩＣのみならず、
６トランジスタのメモリーセル構造におけるゲートコン
トロールのトランジスタ等にも適用し得る。Furthermore, the present invention is not limited to the above-mentioned three-dimensional IC.
It can also be applied to gate control transistors in a 6-transistor memory cell structure.

〔発明の効果〕〔Effect of the invention〕

本発明は、５ｉｎ２等の絶縁性基体上に単結晶性シリコ
ン膜を形成するに際し、まず基体上に多結晶シリコン膜
を形成した後にこれを特定の条件下で固相法により単結
晶化あるいは粗大粒化するようにしたので結晶性の良好
なシリコン膜が得られ、またパターニング精度も大巾に
向上する。When forming a single-crystalline silicon film on an insulating substrate such as 5in2, the present invention first forms a polycrystalline silicon film on the substrate, and then converts it into single crystals or coarse grains by a solid-phase method under specific conditions. Since it is made into grains, a silicon film with good crystallinity can be obtained, and the patterning accuracy is also greatly improved.

したがって、本発明は、三次元化ＩＣ等の積層型半導体
素子の製造に特に有用である。Therefore, the present invention is particularly useful for manufacturing stacked semiconductor devices such as three-dimensional ICs.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図および第３図は本発明の牛導体薄膜の製
造工程を示す断面図であり、第４図は本発明の実施例に
係る積層型ＣＭＯＳインバータの断面図であり、第５図
および第６図はリーク電流特性図である。 １１　、２１　、３１・・・Ｎ型シリコン基板、１２　
、２２　、３２・・！５ＩＯ２膜、１３　、２３　、３
３−・・多結晶シリコン膜、Ｌ３ａ−単結晶化されたシ
リコン膜、ｔ４，２４ｔ３４−・・Ｓ１＋イオン注入、
１５．３５・・・エネルギービーム、２３ａ・・・粗粒
化した層、２３ｂ、３３ａ・・・単結晶化あるいは粗粒
化したシリコン層、４１・・・Ｐ型シリコン基板、４２
・・・酸化膜、４３・・・ゲート酸化膜、４４・・・ゲ
ー、ト電極、４５　ａ　、　４５　ｂ　−Ｎ型領域、４
６ａ、４６ｂ・・・Ｐｔ膜、４７　・・・Ｓ１０□ｌ［
，４８・・・スルーホール、４９・・・シリコン膜、５
０ａ、５０ｂ＝Ｐ型領域、５１−８１０□膜、５２・Ａ
Ｉ配線部。 出願人代理人　　猪　　股　　　　清 ５１　図 １１　　Ｊ　　Ｉ　　Ｉ　　Ｉ　ト１４邪２1, 2, and 3 are cross-sectional views showing the manufacturing process of the conductor thin film of the present invention, and FIG. 4 is a cross-sectional view of a stacked CMOS inverter according to an embodiment of the present invention. 5 and 6 are leakage current characteristic diagrams. 11, 21, 31... N-type silicon substrate, 12
, 22 , 32...! 5IO2 membrane, 13, 23, 3
3-...polycrystalline silicon film, L3a-single crystal silicon film, t4,24t34-...S1+ ion implantation,
15.35... Energy beam, 23a... Coarse grained layer, 23b, 33a... Single crystallized or coarse grained silicon layer, 41... P-type silicon substrate, 42
... Oxide film, 43... Gate oxide film, 44... Gate electrode, 45 a, 45 b - N type region, 4
6a, 46b...Pt film, 47...S10□l[
, 48... Through hole, 49... Silicon film, 5
0a, 50b=P type region, 51-810□ film, 52・A
I wiring section. Applicant's agent Kiyoshi Inomata 51 Figure 11 J I I I To 14 Ja 2

Claims (1)

【特許請求の範囲】 １、絶縁層上に多結晶シリコン層を形成し、次いで上記
多結晶シリコン層にシリコンイオンをイオン注入するこ
とＫより該多結晶シリ゛コン層を−Ｈアモルファス化し
、次いで上記アモルファス化したシリコン層にエネルギ
ービーム照射によるアニーリングを施すことによって該
シリコン層を単結晶シリコン層に変換することを特徴と
する、半導体薄膜の製造方法。 ２、前記絶縁ノーが既に形成された半導体装置上に積層
されている、特許請求の範囲第１項記載の方法。 ３、前記絶縁層がＳｔＯ□またはＳｉＮである、特許請
求の範囲第１項記載の方法。 ４、前記半導体薄膜を用いて半導体装置を製造する工程
を含む、特許請求の範囲第１項または第２項記載の方法
。 ５、前記アニーリングを電子ビーム照射により行なう、
特許請求の範囲第１項記載の方法。 ６、絶縁層上に多結晶シリコン層を形成し、このシリコ
ン層の下層部に不純物プロファイルのピークをもつよう
に該シリコン層にシリコンイオンをイオン注入し、この
シリコンイオンの注入遅れたシリコン層に比較的低温度
の加熱によるアニーリングを施し、次いで上記アニーリ
ングの施されたシリコン層の上層部に不純物ゾロファイ
ルのピークをもつように該シリコン層にシリコンイオン
をイオン注入し、このシリコンイオンの注入されたシリ
コン層に比較的低温度の加熱によるアニーリングを施す
ことを特徴とする、半導体薄膜の製造方法。 ７、前記絶縁層が既に形成された半導体装置上に積層さ
れている、特許請求の範囲第６項に記載の方法。 ８、前記半導体薄膜を用いて半導体装置を製造する工程
を含む、特許請求の範囲第６７項または第１７項記載の
方法。 ９．前記アニーリングを５００〜１０００℃の温度で行
う、特許請求の範囲第６項記載の方法。 １０、前記イオン注入工程およびアニーリング工程をく
り返して行う、特許請求の範囲第６項ないし第９項のい
ずれかに記載の方法。 １１、絶縁層上に多結晶シリコン層を形成し、このシリ
コン層の下層部に不純物プロファイルのピークをもつよ
うに該シリコン層にシリコンイオンをイオン注入し、こ
のシリコンイオンの注入されたシリコン層に比較的低温
度の加熱による熱アニーリングを施し、次いで上記アニ
ーリングの施されたシリコン層の上層部に不純物プロフ
ァイルのピークをもつように該シリコン層にシリコンイ
オンをイオン注入し、このシリコンイオンの注入された
シリコン層に比較的低温度の加熱による熱アニーリング
を施し、さらにこのシリコン層にエネルギービーム照射
によるアニーリングを施すことを特徴とする１半導体薄
膜の製造方法。 １２、前記絶縁層が既に形成された半導体装置上に積層
されている、特許請求の範囲第１・１項記載の方法。 １３、前記半導体薄膜を用いて半導体装置を製造する工
程を含む、特許請求の範囲第１・１項または第１２項に
記載の方法。 １４、前記熱アニーリングを５００〜１０００℃の温度
で行う、特許請求の範囲第１１・項記載の方法。 １５、前記エネルギービームが電子ビームである、特許
請求の範囲第１１項ないし第１４項のいずれかに記載の
方法。[Claims] 1. Forming a polycrystalline silicon layer on the insulating layer, then implanting silicon ions into the polycrystalline silicon layer to make the polycrystalline silicon layer -H amorphous, and then A method for manufacturing a semiconductor thin film, characterized in that the amorphous silicon layer is annealed by energy beam irradiation to convert the silicon layer into a single crystal silicon layer. 2. The method according to claim 1, wherein the insulating layer is laminated on an already formed semiconductor device. 3. The method according to claim 1, wherein the insulating layer is StO□ or SiN. 4. The method according to claim 1 or 2, which includes the step of manufacturing a semiconductor device using the semiconductor thin film. 5. Performing the annealing by electron beam irradiation,
A method according to claim 1. 6. Form a polycrystalline silicon layer on the insulating layer, implant silicon ions into the silicon layer so that the peak of the impurity profile is at the bottom of this silicon layer, and implant the silicon ions into the silicon layer where the implantation is delayed. Annealing is performed by heating at a relatively low temperature, and then silicon ions are ion-implanted into the silicon layer so that the impurity Zorophile has a peak in the upper layer of the annealed silicon layer. 1. A method for producing a semiconductor thin film, comprising annealing a silicon layer by heating at a relatively low temperature. 7. The method according to claim 6, wherein the insulating layer is stacked on an already formed semiconductor device. 8. The method according to claim 67 or 17, which includes the step of manufacturing a semiconductor device using the semiconductor thin film. 9. 7. The method of claim 6, wherein said annealing is carried out at a temperature of 500 to 1000<0>C. 10. The method according to any one of claims 6 to 9, wherein the ion implantation step and the annealing step are performed repeatedly. 11. Form a polycrystalline silicon layer on the insulating layer, implant silicon ions into the silicon layer so that the impurity profile has a peak in the lower layer, and then Thermal annealing is performed by heating at a relatively low temperature, and then silicon ions are implanted into the silicon layer so that the impurity profile has a peak in the upper layer of the annealed silicon layer. 1. A method for manufacturing a semiconductor thin film, which comprises: thermally annealing the silicon layer by heating at a relatively low temperature; and further annealing the silicon layer by irradiating the silicon layer with an energy beam. 12. The method according to claim 1, wherein the insulating layer is laminated on an already formed semiconductor device. 13. The method according to claim 1.1 or 12, which includes the step of manufacturing a semiconductor device using the semiconductor thin film. 14. The method according to claim 11, wherein the thermal annealing is performed at a temperature of 500 to 1000°C. 15. The method according to any one of claims 11 to 14, wherein the energy beam is an electron beam.
JP58030077A 1983-02-24 1983-02-24 Manufacture of semiconductor thin film Pending JPS59155121A (en)

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62104021A (en) * 1985-10-30 1987-05-14 Sony Corp Formation of silicon semiconductor layer
JPS62108516A (en) * 1985-11-06 1987-05-19 Sony Corp Solid growth method for polycrystalline semiconductor film
JPS6360518A (en) * 1986-08-30 1988-03-16 Sony Corp Growing method for crystal of semiconductor layer
US4762801A (en) * 1987-02-20 1988-08-09 National Semiconductor Corporation Method of fabricating polycrystalline silicon resistors having desired temperature coefficients
US5064779A (en) * 1989-02-08 1991-11-12 President Of Kanazawa University Method of manufacturing polycrystalline silicon film
US5240511A (en) * 1987-02-20 1993-08-31 National Semiconductor Corporation Lightly doped polycrystalline silicon resistor having a non-negative temperature coefficient
NL9301811A (en) * 1992-10-28 1994-05-16 Ryoden Semiconductor Syst Eng Thin film field effect transistor and method of manufacturing it, as well as a semiconductor element provided therewith.
US5382537A (en) * 1992-07-10 1995-01-17 Sony Corporation Method of making thin film transistors
US6165875A (en) * 1996-04-10 2000-12-26 The Penn State Research Foundation Methods for modifying solid phase crystallization kinetics for A-Si films
US6383899B1 (en) * 1996-04-05 2002-05-07 Sharp Laboratories Of America, Inc. Method of forming polycrystalline semiconductor film from amorphous deposit by modulating crystallization with a combination of pre-annealing and ion implantation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5676522A (en) * 1979-11-29 1981-06-24 Toshiba Corp Formation of semiconductor thin film

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5676522A (en) * 1979-11-29 1981-06-24 Toshiba Corp Formation of semiconductor thin film

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62104021A (en) * 1985-10-30 1987-05-14 Sony Corp Formation of silicon semiconductor layer
JP2536472B2 (en) * 1985-11-06 1996-09-18 ソニー株式会社 Solid phase growth method for polycrystalline semiconductor film
JPS62108516A (en) * 1985-11-06 1987-05-19 Sony Corp Solid growth method for polycrystalline semiconductor film
JPS6360518A (en) * 1986-08-30 1988-03-16 Sony Corp Growing method for crystal of semiconductor layer
US4762801A (en) * 1987-02-20 1988-08-09 National Semiconductor Corporation Method of fabricating polycrystalline silicon resistors having desired temperature coefficients
US5240511A (en) * 1987-02-20 1993-08-31 National Semiconductor Corporation Lightly doped polycrystalline silicon resistor having a non-negative temperature coefficient
US5064779A (en) * 1989-02-08 1991-11-12 President Of Kanazawa University Method of manufacturing polycrystalline silicon film
US5382537A (en) * 1992-07-10 1995-01-17 Sony Corporation Method of making thin film transistors
NL9301811A (en) * 1992-10-28 1994-05-16 Ryoden Semiconductor Syst Eng Thin film field effect transistor and method of manufacturing it, as well as a semiconductor element provided therewith.
US5514880A (en) * 1992-10-28 1996-05-07 Mitsubishi Denki Kabushiki Kaisha Field effect thin-film transistor for an SRAM with reduced standby current
US5736438A (en) * 1992-10-28 1998-04-07 Mitsubishi Denki Kabushiki Kaisha Field effect thin-film transistor and method of manufacturing the same as well as semiconductor device provided with the same
US6383899B1 (en) * 1996-04-05 2002-05-07 Sharp Laboratories Of America, Inc. Method of forming polycrystalline semiconductor film from amorphous deposit by modulating crystallization with a combination of pre-annealing and ion implantation
US6165875A (en) * 1996-04-10 2000-12-26 The Penn State Research Foundation Methods for modifying solid phase crystallization kinetics for A-Si films

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