JPS60254755A - Package for mounting semiconductor - Google Patents

Package for mounting semiconductor

Info

Publication number
JPS60254755A
JPS60254755A JP59111395A JP11139584A JPS60254755A JP S60254755 A JPS60254755 A JP S60254755A JP 59111395 A JP59111395 A JP 59111395A JP 11139584 A JP11139584 A JP 11139584A JP S60254755 A JPS60254755 A JP S60254755A
Authority
JP
Japan
Prior art keywords
semiconductor chip
package
bonding
cavity
octagonal shape
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59111395A
Other languages
Japanese (ja)
Inventor
Kiyoshi Muratake
村竹　清
Kenichi Yazaki
健一 矢崎
Masahiro Sugimoto
杉本　正浩
Tomoji Hirayama
平山　友治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59111395A priority Critical patent/JPS60254755A/en
Publication of JPS60254755A publication Critical patent/JPS60254755A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49177—Combinations of different arrangements
    • H01L2224/49179—Corner adaptations, i.e. disposition of the wire connectors at the corners of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To mount a semiconductor chip with many bonding pads and to make the lengths of bonding wires uniform, by arranging the respective ends of a plurality of leads in an approximately octagonal shape so as to surround the mounting position of the semiconductor chip. CONSTITUTION:A cavity 9 has an octagonal shape. A semiconductor chip 3 is provided in the cavity 9. The bonding wire connecting ends of a conducting layers 10 are arranged in an approximately octagonal shape so as to surround the mounting position of the semiconductor chip 3. All the lengths of bonding wires 6, which are connected to bonding pads, can be made approximately uniform, even if the numbers of the bonding pads 7 and the conducting layers 10 are many. The surfaces of the corner parts of a bottom part 11 can be effectively utilized. Thus the more conducting layers can be arranged.

Description

【発明の詳細な説明】 （１）発明の技術分野 本発明は、半導体装置用パッケージの改良に関する。特
に、その中に搭載される半導体チップの電極パッドが多
い場合でも、ポンディングワイヤの長さを短くシ、かつ
、ポンディングワイヤの長さをお−むね均一になしうる
ようになす半導体装置用パッケージの改良に関する。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to improvements in packages for semiconductor devices. In particular, for semiconductor devices that can shorten the length of the bonding wire and make the length of the bonding wire generally uniform even when there are many electrode pads of the semiconductor chip mounted therein. Concerning package improvements.

（２）技術の背景 半導体チップは、半導体チップの機械的な固定や外的雰
囲気からの保護、半導体チップからの接続端子の引き出
し、放熱等の目的をもって、パッケージに収容して使用
される。そして、パッケージはセラミックパッケージ、
金属パッケージ等の気密封止型パッケージと、プラスチ
ックパッケージ等の樹脂封止型パッケージとに大別され
る０本発明は気密封止型パッケージ、特に、セラミック
パッケージの構造的改良である。(2) Background of the Technology Semiconductor chips are used by being housed in a package for purposes such as mechanically fixing the semiconductor chip, protecting it from external atmosphere, drawing out connection terminals from the semiconductor chip, and dissipating heat. And the package is a ceramic package,
Packages are broadly classified into hermetically sealed packages such as metal packages and resin sealed packages such as plastic packages.The present invention is a structural improvement of hermetically sealed packages, particularly ceramic packages.

半導体チップを搭載し、ポンティング工程を有するセラ
ミックパッケージ等においては、ポンディングワイヤの
長さが極力均一であることが望ましい。インピーダンス
整合を容易にし、信号波の反射の悪影響を免れる等のた
めである。In a ceramic package or the like that mounts a semiconductor chip and has a bonding process, it is desirable that the length of the bonding wire is as uniform as possible. This is to facilitate impedance matching and avoid the adverse effects of signal wave reflection.

（３）従来技術と問題点 従来技術におけるセラミックパッケージの１例のカバー
を取り外した状態における平面図とその垂直な面をもっ
て切断した断面図とを第１図、第２図に示す。図におい
て、１はセラミックパッケージ筐体の底部であり、その
中央に設けられたキャビティー２中に半導体チップ３が
搭載される。４はセラミックパッケージ筐体の側壁部で
あり、パッケージ内部の底部ｌ上から側壁部４及び底部
１内を通り外部のり一ド１２まで例えばタングステン等
からなる導電層５が配設されている。６はボンデインク
ワイヤであり、半導体チップのポンディングパッド７と
導電層５とを接続する。８はセラミックパッケージ筐体
のカバー、１１はリードである。図より明らかなように
、キャビティー２はお−むね方形とされており、半導体
チップは、底部ｌに設けられた方形のキャビティー２の
中に配置される。また、導電層５は底部ｌの方形のキャ
ビティー２を囲む領域に配列される。(3) Prior Art and Problems FIGS. 1 and 2 show a plan view of an example of a ceramic package according to the prior art with the cover removed, and a sectional view taken along a plane perpendicular to the plan view. In the figure, 1 is the bottom of a ceramic package housing, and a semiconductor chip 3 is mounted in a cavity 2 provided at the center thereof. Reference numeral 4 denotes a side wall portion of the ceramic package housing, and a conductive layer 5 made of, for example, tungsten is disposed from above the bottom l inside the package, passing through the side wall portion 4 and the bottom portion 1 to the external glue 12. A bonding wire 6 connects the bonding pad 7 of the semiconductor chip and the conductive layer 5. 8 is a cover of the ceramic package case, and 11 is a lead. As is clear from the figure, the cavity 2 is generally rectangular, and the semiconductor chip is placed in the rectangular cavity 2 provided at the bottom l. Also, the conductive layer 5 is arranged in a region surrounding the rectangular cavity 2 at the bottom l.

半導体チップにおいて、集積度を向上させ、多機能化を
計り、極めて多くの論理素子を有するようにすると、ポ
ンディングパッド７並びに導電層５の数が増加し、パッ
ケージ筐体も大きくならざるを得ない。そして、第３図
に示すようにキャビティー２の隅部分のパッケージ筐体
ｌ上に導電層５を配設しようとすると、この部分での導
電層５とポンディングパッド７の距離が特に長くなり、
ポンディングワイヤの長さを短く、かつ均一にすること
が困難であるという欠点がある。この欠点は、導電層５
の数かは１″６０以上になると特に問題となる。As semiconductor chips increase their degree of integration, become multi-functional, and have an extremely large number of logic elements, the number of bonding pads 7 and conductive layers 5 increases, and the size of the package casing also becomes larger. do not have. When attempting to arrange the conductive layer 5 on the package casing l at the corner of the cavity 2 as shown in FIG. 3, the distance between the conductive layer 5 and the bonding pad 7 at this portion becomes particularly long. ,
There is a drawback that it is difficult to make the length of the bonding wire short and uniform. This drawback is that the conductive layer 5
The number becomes particularly problematic when the number is 1"60 or more.

（４）発明の目的 本発明の目的は、上記の欠点を解消することにあり、ポ
ンディングパッドの数の多い半導体チップを搭載するこ
とができ、ポンディングワイヤの長さをお〜むね均一に
なしうる半導体装置用パッケージを提供することにある
。(4) Purpose of the Invention The purpose of the present invention is to eliminate the above-mentioned drawbacks, and to make it possible to mount a semiconductor chip with a large number of bonding pads, and to make the length of the bonding wires generally uniform. The object of the present invention is to provide a package for a semiconductor device that can be used.

（５）発明の構成 本発明の構成は、ポンディングワイヤが接続される複数
のリードのそれぞれの１端が半導体チップ搭載位置を囲
んでお＼むね八角形状に配置されてなる半導体装置用パ
ッケージにある。(5) Structure of the Invention The structure of the present invention is directed to a semiconductor device package in which one end of each of a plurality of leads to which bonding wires are connected is arranged in a roughly octagonal shape surrounding a semiconductor chip mounting position. be.

（６）発明の実施例 以Ｆ、図面を参照しつ覧本発明の実施例に係る半導体装
置用パッケージについてさらに説明する。(6) Embodiments of the Invention From now on, packages for semiconductor devices according to embodiments of the present invention will be further described with reference to the drawings.

第４図参照 図において、　１１はセラミックパッケージ筐体の底部
であり、その中央に設けられたキャビティー９中に半導
体チップ３が搭載される。４はセラミックパッケージ筐
体の側壁部であり、１０は導電層でありパッケージ内部
の底部１１から外部のり一ド１２まで配設・される、６
はポンディングワイヤであり、半導体チップのポンディ
ングパッド７と導電層ｌＯとを接続する。Referring to FIG. 4, 11 is the bottom of the ceramic package housing, and the semiconductor chip 3 is mounted in the cavity 9 provided at the center. 4 is a side wall of the ceramic package case; 10 is a conductive layer disposed from the bottom 11 inside the package to the external glue 12; 6;
is a bonding wire, which connects the bonding pad 7 of the semiconductor chip and the conductive layer IO.

図より明らかなように、キャビティー９は方形ではなく
、従来の各隅の部分を三角形状に減少した八角形状で、
底部１１の中央に形成される。半導体チップ３はキャビ
ティー９の中に設けられる。As is clear from the figure, the cavity 9 is not rectangular but has an octagonal shape with each corner of the conventional structure reduced to a triangular shape.
It is formed in the center of the bottom part 11. The semiconductor chip 3 is provided in the cavity 9.

導電層１０は、底部Ｉｔ上の、キャビティー９を囲む領
域に配列されるが、キャビティー９が八角形状であるか
ら、導電層ｌＯのポンディングワイヤ接続端は、半導体
チップ３の搭載位置を囲んでお＼むね八角形状に配置さ
れ、その結果、第５図の如く半導体チップ３の角の部分
のホンディングパッドに接続するポンディングワイヤ６
の長さは短くなり、ポンディングパッド７と導電層ｌＯ
の数が多くてもポンディングワイヤ６の全体をはＣ均一
にできる。また、底部１１の隅部分の表面も有効に利用
されることになり、より多くの導電層を配設しうること
になることは勿論である。The conductive layer 10 is arranged in a region surrounding the cavity 9 on the bottom It, but since the cavity 9 has an octagonal shape, the bonding wire connection end of the conductive layer IO is located at the mounting position of the semiconductor chip 3. The bonding wires 6 are arranged around the semiconductor chip 3 in a roughly octagonal shape, and are connected to the bonding pads at the corners of the semiconductor chip 3 as shown in FIG.
The length of the bonding pad 7 and the conductive layer lO become shorter.
Even if the number of bonding wires 6 is large, the entire bonding wire 6 can have a uniform C. Moreover, the surface of the corner portion of the bottom portion 11 is also effectively utilized, and it goes without saying that more conductive layers can be disposed.

なお、導電層のポンディングワイヤ接続端の配置位置は
正しく八角形状である必要はなく、第６図に示すように
半導体チップ３の角に対する部分を弧状にしていてもさ
しつかえない。Note that the arrangement position of the bonding wire connection end of the conductive layer does not necessarily have to be exactly octagonal, and the portion corresponding to the corner of the semiconductor chip 3 may be arcuate as shown in FIG.

（７〕発明の効果 以」−説明せるとおり、本発明によれば各導電層のポン
ディングワイヤ接続端が、半導体チップ搭載位置を囲ん
でおへむね八角形状に配置されているので、パッケージ
の底部の隅部分が有効に利用され、より多くの導電層を
配設することができてよリボンディングパッド数の多い
半導体チップを搭載することができる。また、ボンデイ
ンクワイヤの長さをおへむね均一かつ短くなすことがで
き、インピーダンス整合を容易にし、信号波の反射の悪
影響を免れることができる。すなわち１本発明によれば
多くの利益を有する半導体装置用パッケージを提供する
ことが可能となる。(7) Effects of the Invention - As explained, according to the present invention, the bonding wire connection ends of each conductive layer are arranged in an octagonal shape surrounding the semiconductor chip mounting position, so that the package The bottom corner is effectively used, allowing more conductive layers to be placed, and semiconductor chips with a larger number of bonding pads to be mounted.Also, the length of the bonding wire can be reduced. It is possible to make the package generally uniform and short, facilitate impedance matching, and avoid the adverse effects of signal wave reflection.In other words, according to the present invention, it is possible to provide a package for a semiconductor device that has many benefits. Become.

【図面の簡単な説明】[Brief explanation of drawings]

第１図、第２図は従来技術に係るセラミックパンケージ
の１例のカバーを取り外した状態における平面図とその
垂直な面をもって切断した断面図である。第３図は従来
技術に係るパッケージ内のキャビティーの隅の部分の図
である。第４図は本発明の一実施例に係る半導体装置用
パッケージのカバーを取り外した状態における平面図で
ある。第５図は本発明の一実施例に係る半導体装置用パ
ッケージ内のキャビティーの隅の部分の図である。第６
図は本発明の別の実施例に係る半導体パッケージ内のキ
ャビティーの隅の部分の図である。FIGS. 1 and 2 are a plan view of an example of a conventional ceramic pan cage with a cover removed, and a sectional view taken along a plane perpendicular to the plan view. FIG. 3 is a view of a corner of a cavity in a package according to the prior art. FIG. 4 is a plan view of the semiconductor device package according to an embodiment of the present invention with the cover removed. FIG. 5 is a diagram of a corner portion of a cavity in a package for a semiconductor device according to an embodiment of the present invention. 6th
The figure is a view of a corner portion of a cavity in a semiconductor package according to another embodiment of the present invention.

Claims (1)

【特許請求の範囲】[Claims] ポンディングワイヤが接続される複数の導電層のそれぞ
れのｌ端が半導体チップ搭載位置を囲んでおへむね六角
形状に配置されてなる半導体装置用パッケージ。A package for a semiconductor device in which the respective l ends of a plurality of conductive layers to which bonding wires are connected are arranged in a generally hexagonal shape surrounding a semiconductor chip mounting position.
JP59111395A 1984-05-31 1984-05-31 Package for mounting semiconductor Pending JPS60254755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59111395A JPS60254755A (en) 1984-05-31 1984-05-31 Package for mounting semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59111395A JPS60254755A (en) 1984-05-31 1984-05-31 Package for mounting semiconductor

Publications (1)

Publication Number Publication Date
JPS60254755A true JPS60254755A (en) 1985-12-16

Family

ID=14560064

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59111395A Pending JPS60254755A (en) 1984-05-31 1984-05-31 Package for mounting semiconductor

Country Status (1)

Country Link
JP (1) JPS60254755A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63276233A (en) * 1987-05-08 1988-11-14 Nec Corp Semiconductor device
US8754513B1 (en) * 2008-07-10 2014-06-17 Marvell International Ltd. Lead frame apparatus and method for improved wire bonding

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4924228U (en) * 1972-05-30 1974-03-01
JPS5744570B2 (en) * 1976-06-18 1982-09-22

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4924228U (en) * 1972-05-30 1974-03-01
JPS5744570B2 (en) * 1976-06-18 1982-09-22

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63276233A (en) * 1987-05-08 1988-11-14 Nec Corp Semiconductor device
US8754513B1 (en) * 2008-07-10 2014-06-17 Marvell International Ltd. Lead frame apparatus and method for improved wire bonding
US9202797B1 (en) 2008-07-10 2015-12-01 Marvell International Ltd. Lead frame apparatus and method for improved wire bonding

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