JPS59113650A - Lead frame for semiconductor device - Google Patents

Lead frame for semiconductor device

Info

Publication number
JPS59113650A
JPS59113650A JP57222875A JP22287582A JPS59113650A JP S59113650 A JPS59113650 A JP S59113650A JP 57222875 A JP57222875 A JP 57222875A JP 22287582 A JP22287582 A JP 22287582A JP S59113650 A JPS59113650 A JP S59113650A
Authority
JP
Japan
Prior art keywords
leads
flat board
plate type
metal flat
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57222875A
Other languages
Japanese (ja)
Inventor
Tomohito Izumida
泉田　智史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP57222875A priority Critical patent/JPS59113650A/en
Publication of JPS59113650A publication Critical patent/JPS59113650A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To facilitate the mounting of a high integrated chip, to form a firm construction not to generate an electric short between leads without thinning the leads, and to enable to form a semiconductor device in a thin type by a method wherein the plate type leads of the plural number made each edge to come close to a metal flat board to be fitted up with the semiconductor chip are kept in places according to an electrically insulating member filled up the gap between the leads and between the leads and the metal flat board. CONSTITUTION:A semiconductor chip 2 is fitted up to a metal flat board part 11, the electrodes thereof are bonded by bonding wires 3 to plate type metal leads 12, and the gap between the plate type leads, between the plate type leads and the metal flat board part 11 is molded to be fixed according to the synthetic resins 13 of an electrically insulating member. The flat board 11 thereof is formed in a square type, a circular type, etc. Moreover the plate type leads 12 can be formed also as pin parts 22' protruding from the side of the synthetic resins 13 part of a mold. At this case, pins (a) can be formed in a twisted pin type (b) twisting the shape (a) protruding the plate type lead 12, for example. Moreover, to fit up the semiconductor chips 2 on both the surfaces of the metal flat board part 51 of a lead frame, and to apply a package 10 after performation of wire bonding can be attained also.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は半導体装置用リードフレームの構造の改良Ｋ
かかシ、特に高出力トランジスタ、ＩＣ。[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to an improvement in the structure of a lead frame for a semiconductor device.
Especially high output transistors and ICs.

ＬＳＩ等微細ないし発熱の大きい半導体装置のリードフ
レームに適用される。It is applied to lead frames of semiconductor devices that are minute or generate a lot of heat, such as LSIs.

〔発明の技術的背景〕[Technical background of the invention]

半導体チップを取着する平板部（いわゆるチップベッド
）と、ここに取着された半導体チップの電極をこの周囲
に一端を配置する複数のリードとを備え、上記′１極を
リードの一端部にワイヤボンディングを施して電極を導
出するリードフレームの一例を第１図に、また、第２図
にリードフレームにグイボンディング、ワイヤボンディ
ングを施した状態を示す。すなわち、（刀はリードフレ
ームで、その中央の平板部（１ａ）に半導体チップ（２
）をボンディングし、その電極（２ａ）、（２ａ）・・
をｄ（ンデイングワイヤ（３）　、　（３）・・・によ
って各対応するリード（ｌｂ）、（ｌｂ）・・に接続し
導出している。It is equipped with a flat plate part (so-called chip bed) on which a semiconductor chip is attached, and a plurality of leads around which the electrodes of the semiconductor chip attached thereon are arranged, one end of which is placed at one end of the leads. FIG. 1 shows an example of a lead frame from which electrodes are led out by wire bonding, and FIG. 2 shows a state in which the lead frame is subjected to wire bonding and wire bonding. In other words, (the sword is a lead frame, and a semiconductor chip (2
), and the electrodes (2a), (2a)...
are connected to the corresponding leads (lb), (lb), . . . by connecting wires (3), (3), .

上述のリードフレーム（Ｌ）は一般に銅の薄板にプレス
またはエツチング、さらにはプレスにエツチングを併用
して形成される。The above-mentioned lead frame (L) is generally formed on a thin copper plate by pressing or etching, or by a combination of pressing and etching.

〔背景技術の問題点〕[Problems with background technology]

斜上の背景技術によるリードフレームは半導体チップの
集積度が向上するにしたがって導出電極数が増大し、各
電極間の間隔が狭小になる。このため、リードフレーム
の製造、取扱いが困難になる重大な欠点がある。また、
パッケージ材料が合成樹脂やセラミックスなどでなシ、
パッケージの構造と併せ半導体チップの発熱を発散させ
る点に問題があった。In the lead frame according to the above-mentioned background art, as the degree of integration of semiconductor chips increases, the number of lead-out electrodes increases and the interval between each electrode becomes narrower. For this reason, there is a serious drawback that manufacturing and handling of the lead frame becomes difficult. Also,
If the package material is not made of synthetic resin or ceramics,
There was a problem with the structure of the package as well as the dissipation of heat generated by the semiconductor chip.

〔発明の目的〕[Purpose of the invention]

この発明は上記従来の問題点を改良するだめの半導体装
置用リードフレームの構造を提供する。The present invention provides a structure of a lead frame for a semiconductor device that overcomes the above-mentioned conventional problems.

〔発明の概要〕[Summary of the invention]

半導体チップを取着する金属平板に一端を近接させ、上
記金属平板に対し非平行の複数リードがリード間および
金属平板との間に合成樹脂やセラミックスのような電気
絶縁部材が充填定位されていることを特徴とする半導体
装置用リードフレームの構造である。One end is placed close to a flat metal plate on which a semiconductor chip is attached, and a plurality of leads that are non-parallel to the flat metal plate are filled with an electrically insulating material such as synthetic resin or ceramics between the leads and the flat metal plate. This is a structure of a lead frame for a semiconductor device characterized by the following.

〔発明の実施例〕[Embodiments of the invention]

次にこの一珀明を実施例によって図面を透照して詳細に
説明する。第３図は半導体チップ（２）をとの取着部の
金属平板部ａυに取着し、その電極を金属の板状リード
１１Ｂ　、α４　、にボンディングワイヤ（３）。Next, this invention will be explained in detail by way of examples with reference to the drawings. In FIG. 3, a semiconductor chip (2) is attached to a metal flat plate part aυ of the attachment part, and its electrodes are connected to metal plate-shaped leads 11B, α4, with bonding wires (3).

（３）でボンディングし、板状リードの間、板状リード
と金属平板部ａυとの間を電気絶縁部材の一例の合成樹
脂ｕ東でモールドし固定させたものを示す。(3) is bonded, and the space between the plate-shaped leads and between the plate-shaped leads and the metal flat plate part aυ is molded and fixed with synthetic resin U-Higashi, which is an example of an electrically insulating material.

次に上記第３図に示した金属平板部住υは角型であった
が、これを円型に形成したものを第４図および第５図に
示す。なお、第５図は半導体チップの取着と、ワイヤボ
ンディングを施したものを透視的に示す。両図において
、（２Ｉ）は円型の金属平板部である点を除いては第３
図において説明したところと変わらないので、図面に同
じ符号を付して示し説明を省略する。Next, although the metal flat plate part shown in FIG. 3 was square, a circular shape is shown in FIGS. 4 and 5. Incidentally, FIG. 5 is a perspective view showing the attachment of a semiconductor chip and wire bonding. In both figures, (2I) is a circular metal flat plate part.
Since it is the same as that described in the drawings, the same reference numerals are attached to the drawings and the explanation thereof will be omitted.

次に第６図に示すものは、金属平板部Ｏυが千円形で１
側面にだけ板状リードａ”ａ　　ｕａ・・を延出させて
いる。これは上記第４図（第５図）に示すものがＤＩＰ
型に属するとするとき８　Ｉ　Ｐに属するものである。Next, the one shown in Figure 6 has a metal flat plate part Oυ of 1,000 circles.
A plate-shaped lead a"a ua... is extended only on the side surface. This is because the one shown in FIG. 4 (FIG. 5) above is
When it belongs to type 8, it belongs to type 8 IP.

さらに、第７図に示すものは上記第６図に示したものと
金属平板部（４１）が角型に形成されている点が異なっ
ている。Furthermore, the one shown in FIG. 7 differs from the one shown in FIG. 6 above in that the metal flat plate part (41) is formed into a square shape.

次に、第８図に示すものは第４図に示したものの板状リ
ード（２３、（２２）・・・をモールドの合成樹脂０罎
部の側面から突出させてピン部（２２’）、（２２’）
・・に形成している。図において、ビン（ａ　）　＋　
（ｂ　）はビン部の加工順序を示す。すなわち、板状リ
ードを突出させた形状（ａ）を捩シピン形状に成形を施
しくｂ）にする。さらに捩シ折曲してピン部（２２’）
、（２２’ル・・はＤＩＰ型のピ／と同様の形状を示す
。Next, the thing shown in FIG. 8 is the same as that shown in FIG. 4, but the plate-shaped leads (23, (22)... (22')
... is formed. In the figure, bin (a) +
(b) shows the processing order of the bottle part. That is, the shape (a) in which the plate-like leads protrude is formed into a torsion pin shape to form b). Further twist and bend the pin part (22')
, (22'le... indicates the same shape as the DIP type pi/.

また、第９図にはリードフレームの金属平板部５１）の
両面に半導体チップ（２）　、　（２）を取着け、ワイ
ヤボンディング後にパッケージ（樹脂モールド）　（１
Ｇを施したものを例示しだ。In addition, in FIG. 9, semiconductor chips (2), (2) are attached to both sides of a metal flat plate part 51) of a lead frame, and after wire bonding, a package (resin mold) (1) is attached.
This is an example of one with G applied.

さらに、第１０図には金属平板部を省いた構造で、中央
部には板状リードによる短絡を避けるため透孔（至）が
設けられている。Further, FIG. 10 shows a structure in which the flat metal part is omitted, and a through hole is provided in the center part to avoid short circuits due to the plate-like leads.

そして半導体チップは同図に破線（３ｏ）で示す位置に
取着されるものである。なお、第１１図および第１２図
にはリードフレームにパッケージングを施した状態、第
１３図ないし、第１５図にはビンを取着した状態を夫々
示す。また、第１５図に示すビンは配線用ビンとソケッ
ト用ビンとを設けたもので、半導体装置を積み重ねて回
路構成をなすものを示している。The semiconductor chip is mounted at the position indicated by the broken line (3o) in the figure. Note that FIGS. 11 and 12 show the lead frame in a packaged state, and FIGS. 13 to 15 show the state in which a bottle is attached, respectively. Moreover, the bin shown in FIG. 15 is provided with a wiring bin and a socket bin, and shows a circuit configuration formed by stacking semiconductor devices.

〔発明の効果ｊ この発明によれば、半導体チップのマウント部分を熱容
量の大きい金属板状部材をベッドにすることができるた
め、バイポーラＬＳＩ、高出力アンプ用ＩＣなどの高集
積チップの実装が容易にできる顕著な利点がある。また
、多くの電極を導出するリードを形成するにあたり、リ
ードを細くすることなく構成できるとともに、リード間
に電気短絡を生じない強固な構造である。さらに、半導
体装置が薄く形成できる利点もある。[Effect of the invention j According to this invention, since the mounting portion of the semiconductor chip can be made of a metal plate-like member with a large heat capacity as a bed, it is easy to mount highly integrated chips such as bipolar LSIs and ICs for high-output amplifiers. There are significant advantages that can be achieved. Further, when forming leads from which many electrodes are led out, the leads can be constructed without making them thinner, and the structure is strong enough to prevent electrical short circuits between the leads. Furthermore, there is an advantage that the semiconductor device can be formed thin.

【図面の簡単な説明】[Brief explanation of drawings]

第１図および第２図は従来のリードフレームにかかシ、
第１図はリードフレームの正面図、第２図はマウント後
の正面図、第３図以降はこの発明のリードフレームにか
かシ、第３図はｌ実施例のマウント後の正面図、第４図
、第６図、第７図。 第８図、第９図、第１０図はいずれも夫々が実施例を示
し、第４図は斜視図、第５図は第４図のリードフレーム
にマウント後の斜視図、第６図ないし第８図はいずれも
斜視図、第９図れ断面図、第１０図は斜視図、第１１図
および第１２図はバックージング後の斜視図、第１３図
ないし第１５図はビン取着を施した製品のいずれも斜視
図である。 ２．３０　　　　半導体チップ １１．２１．３１．４１．５１ 金属平板部 １２．２２　　　　板状リード １３　　　　　合成樹脂 ２０　　　通孔 代理人　弁理士　井　上　−男 第１図 第２図 第３図 第４図 第５図 １１１［ ３ 第６図 第７図 第８図 第９図 第１０図 第１１図 第１２図 第１３図 第１４図 第１５図Figures 1 and 2 show conventional lead frames and
FIG. 1 is a front view of the lead frame, FIG. 2 is a front view after mounting, FIG. Figure 4, Figure 6, Figure 7. 8, 9, and 10 each show an embodiment, FIG. 4 is a perspective view, FIG. 5 is a perspective view after mounting on the lead frame of FIG. 4, and FIGS. Figure 8 is a perspective view, Figure 9 is a sectional view, Figure 10 is a perspective view, Figures 11 and 12 are perspective views after backing, and Figures 13 to 15 are products with bottle attachment. Both are perspective views. 2.30 Semiconductor chip 11.21.31.41.51 Metal plate part 12.22 Plate lead 13 Synthetic resin 20 Through hole agent Patent attorney Mr. Inoue Figure 1 Figure 2 Figure 3 Figure 4 5 Figure 111 [ 3 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15

Claims (1)

【特許請求の範囲】[Claims] 半導体チップを取着する金属平板に一端を近接させ、上
記金属平板に対して非平行の複数板状リードがリード間
および金属平板との間に充填された電気絶縁部材によっ
て定位された半導体装置用リードフレーム。For semiconductor devices in which one end is placed close to a metal flat plate on which a semiconductor chip is attached, and a plurality of plate-shaped leads that are non-parallel to the metal flat plate are oriented by an electrically insulating member filled between the leads and between the metal flat plate. Lead frame.
JP57222875A 1982-12-21 1982-12-21 Lead frame for semiconductor device Pending JPS59113650A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57222875A JPS59113650A (en) 1982-12-21 1982-12-21 Lead frame for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57222875A JPS59113650A (en) 1982-12-21 1982-12-21 Lead frame for semiconductor device

Publications (1)

Publication Number Publication Date
JPS59113650A true JPS59113650A (en) 1984-06-30

Family

ID=16789253

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57222875A Pending JPS59113650A (en) 1982-12-21 1982-12-21 Lead frame for semiconductor device

Country Status (1)

Country Link
JP (1) JPS59113650A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
WO1997027627A1 (en) * 1996-01-25 1997-07-31 Advanced Micro Devices, Inc. Lead frame with circular lead tip layout and improved assembly

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4862322A (en) * 1988-05-02 1989-08-29 Bickford Harry R Double electronic device structure having beam leads solderlessly bonded between contact locations on each device and projecting outwardly from therebetween
WO1997027627A1 (en) * 1996-01-25 1997-07-31 Advanced Micro Devices, Inc. Lead frame with circular lead tip layout and improved assembly

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