JPS60251667A - Thin-film transistor - Google Patents
Thin-film transistorInfo
- Publication number
- JPS60251667A JPS60251667A JP10770784A JP10770784A JPS60251667A JP S60251667 A JPS60251667 A JP S60251667A JP 10770784 A JP10770784 A JP 10770784A JP 10770784 A JP10770784 A JP 10770784A JP S60251667 A JPS60251667 A JP S60251667A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- source
- film transistor
- gate electrode
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 30
- 239000010408 film Substances 0.000 claims abstract description 16
- 239000012535 impurity Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- 238000002513 implantation Methods 0.000 claims description 3
- 239000000758 substrate Substances 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract description 8
- 239000011574 phosphorus Substances 0.000 abstract description 8
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 abstract description 5
- XYFCBTPGUUZFHI-UHFFFAOYSA-N Phosphine Chemical compound P XYFCBTPGUUZFHI-UHFFFAOYSA-N 0.000 abstract description 4
- -1 phosphorus ions Chemical class 0.000 abstract description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract description 2
- 229910000073 phosphorus hydride Inorganic materials 0.000 abstract description 2
- 229910000077 silane Inorganic materials 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract 1
- 230000006837 decompression Effects 0.000 abstract 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 9
- 238000000034 method Methods 0.000 description 4
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 240000003473 Grevillea banksii Species 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は、絶縁基板上でゲート電極がソース・ドレイン
領域よりも上側にある薄膜トランジスターにおいて、高
濃度不純物が添加された半導体層からなるソース・ドレ
イン領域とゲート電極の重なり構造に関するものであり
、重なりの仕方またはプロセスの追加によって、高移動
度を有した自己整合型の薄膜トランジスターや高耐圧の
薄膜トランジスターな提供するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to a thin film transistor in which a gate electrode is located above a source/drain region on an insulating substrate, and in which the source/drain region is made of a semiconductor layer doped with a high concentration of impurities. The invention relates to an overlapping structure between a gate electrode and a gate electrode, and by changing the overlapping method or adding a process, a self-aligned thin film transistor with high mobility or a high breakdown voltage thin film transistor can be provided.
近年、絶縁基板上に堆積した非晶質シリコンや多結晶シ
リコンχ能動領域として用いた薄膜トランジスターは、
液晶表示装置、論理回路、イメージセンサ等への応用と
して使われている。中でも非晶質シリコンヶ用いると低
温で大面積化が容易にでき、低コストの製品が実現でき
るため、多結晶シリコンを用いたテバイスよりもいちは
やく装置開発が進められている状況である。In recent years, thin film transistors using amorphous silicon or polycrystalline silicon deposited on an insulating substrate as the active region,
It is used for applications such as liquid crystal display devices, logic circuits, and image sensors. Among these, the use of amorphous silicon makes it easy to increase the area at low temperatures and produce low-cost products, so equipment development is progressing faster than devices using polycrystalline silicon.
第１図は、従来の一般的な非晶質シリコンを用いた薄膜
トランジスターの断面図である。透明ガラス１上に、ゲ
ート電極２を堆イ貢しパターニングする。次にゲート絶
縁膜６と非晶質シリコン膜と高濃度不純物リンが象加さ
れたノース・ドレイン層とソース・ドレイン端子層乞順
次積層し、上側からソース電極端子７、ドレイン電極端
子８、ソース領域５、ドレイン領域６、非晶質シリコン
膜４乞パターン形成して完成する。この非晶質シリコン
薄膜トランジスターの大きな欠点は、次のごと（である
。FIG. 1 is a cross-sectional view of a conventional general thin film transistor using amorphous silicon. A gate electrode 2 is deposited and patterned on a transparent glass 1. Next, a gate insulating film 6, an amorphous silicon film, a north drain layer in which high-concentration impurity phosphorus is added, and a source/drain terminal layer are sequentially laminated, and from the top, a source electrode terminal 7, a drain electrode terminal 8, a source The region 5, the drain region 6, and the amorphous silicon film 4 are patterned and completed. The major drawbacks of this amorphous silicon thin film transistor are as follows.
１、 高い移動展が得られないため、高速のスイッチン
グ素子としては不適当である。1. It is unsuitable as a high-speed switching element because high transfer expansion cannot be obtained.
２ ソース・ドレイン領域乞パターン形成でつくるため
、元来ゲート′虹極との間に自己整合性がなく、大面積
になればなるほどそれは強調される。2. Since the source/drain region is formed by patterning, there is originally no self-alignment between the gate and the rainbow pole, and this becomes more pronounced as the area becomes larger.
本発明は、かかる欠点ビ除去したもので、その目的は、
高い移動度を得ることと同時に自己整合性を有する薄膜
トランジスターを提供することである。The present invention eliminates such drawbacks, and its purpose is to:
An object of the present invention is to provide a thin film transistor that has high mobility and self-alignment at the same time.
高い移動度を得るために、真性半導体薄膜として非晶質
シリコンでなく、多結晶シリコンを用いている。また多
結晶シリコンは、膜成長に伴って結晶粒径が増大し、欠
陥密度が′減少することからゲート電＆を上側に形成す
る構造にする。また自己整合性乞有するためには、あら
かじめ、オフセット領域（ゲート電極がソース・ドレイ
ン領域に重ならない部分）乞もうけておき、ゲート電極
のパターンヶマスクにしたイオン打込みによりソース・
ドレイン領域乞形成する方法ンとる。In order to obtain high mobility, polycrystalline silicon is used instead of amorphous silicon as the intrinsic semiconductor thin film. Furthermore, since the crystal grain size of polycrystalline silicon increases as the film grows and the defect density decreases, the structure is such that the gate electrode & is formed on the upper side. In addition, in order to ensure self-alignment, an offset region (a portion where the gate electrode does not overlap with the source/drain region) is prepared in advance, and ion implantation is performed using the pattern of the gate electrode as a mask.
How to form the drain region.
以下実施例に基づいて本発明の詳細な説明する。 The present invention will be described in detail below based on examples.
第２図は、真性半導体薄膜として多結晶シリコン膜４′
を用いた薄膜トランジスターの断面図である。まずソー
ス領域５、ドレイン領域、６１として昼濃度不純物リン
が添加された半導体薄膜ケ用いる。Figure 2 shows a polycrystalline silicon film 4' as an intrinsic semiconductor thin film.
FIG. First, a semiconductor thin film doped with day-concentration impurity phosphorus is used as the source region 5, drain region, and 61.
高濃度不純物リンの半導体薄膜は直接ホスフィンとシラ
ンを混合したガスで減圧ＣＶＤ法により堆積してもよい
が、真性多結晶シリコン薄膜にリンイオンを打込みして
もつ（ることかできる。次に真性多結晶シリコン膜４′
乞積層してバターニング後ゲート絶縁膜６とゲート電極
２を積層してコンタクトホール９を開口したのち、ソー
ス電極端子７、ドレイン電極端子８乞形成して完成する
。第３図は、第２図にはない自己整合性７有した薄膜ト
ランジスターの断面図である。第２図とは異なり、ゲー
ト電極２が、高濃度不純物乞添加した半４体ｉのソース
φドレイン領域５，６上に重ならない構造で、ゲート電
極２のパターン形成後リンのイオン打込みを行なうこと
により新たなソース参じレイン領域５／、 ６／Ｙつ（
ることで自己整合性を有するものである。A semiconductor thin film with a high concentration of impurity phosphorus may be deposited directly by low pressure CVD using a gas mixture of phosphine and silane, but it can also be deposited by implanting phosphorus ions into an intrinsic polycrystalline silicon thin film. Crystalline silicon film 4'
After stacking and patterning, the gate insulating film 6 and the gate electrode 2 are stacked, a contact hole 9 is opened, and a source electrode terminal 7 and a drain electrode terminal 8 are formed to complete the process. FIG. 3 is a cross-sectional view of a thin film transistor having self-alignment 7, which is not present in FIG. Unlike in FIG. 2, the structure is such that the gate electrode 2 does not overlap the source φ drain regions 5 and 6 of the semi-quaternary body doped with high concentration impurities, and phosphorus ions are implanted after patterning the gate electrode 2. By this, new source reference rain regions 5/, 6/Y (
By doing so, it has self-consistency.
以上のように本発明の構造は、高移動度を有した高速ス
イッチングが可能な薄膜トランジスターを作製できるば
かりでな（、イオン打込みのプロセスを入れることで自
己整合性を有するものである。また次のような句加効果
を生みだす。As described above, the structure of the present invention not only makes it possible to fabricate a thin film transistor with high mobility and high-speed switching (it also has self-alignment by incorporating an ion implantation process. It produces a haiku effect like .
１、 高濃度の不純物を添加したソ」ス・ドレイン領域
乞イオン打込みにより形成する場せにおいて、真性多結
晶シリコンの堆積と同時に、ソース・ドレイン領域を低
抵抗にする。（単位面積当り数キロオームのものが数百
オーム°になる。）そのためソース・ドレイン電極端子
との接触抵抗を十分小さくすることができる。1. In the case where a source/drain region doped with impurities at a high concentration is formed by ion implantation, the resistance of the source/drain region is made low at the same time as the intrinsic polycrystalline silicon is deposited. (The resistance of several kiloohms per unit area becomes several hundreds of ohms.) Therefore, the contact resistance with the source/drain electrode terminals can be made sufficiently small.
２、 真性多結晶シリコンの膜厚暑博（しても外部端子
との接触抵抗は変化しないため膜厚ン５００Ａ程度と薄
くすることが可能でオフ電流の低減とオン電流の増大が
おこりオンとオフの電流比の増大乞期待できる。2. Even if the film thickness of intrinsic polycrystalline silicon increases (even if the contact resistance with external terminals does not change, the film thickness can be made as thin as about 500A, which reduces the off-state current and increases the on-state current. We can expect an increase in the off-state current ratio.
＆ 第４図のような、ゲート電極２が高濃度不純物乞添
加した半導体層からなるドレイン領域上に重ならないオ
フセットゲート構造の薄膜トランシスターン用いれば、
ドレイン層表面近くの電界集中が緩和され耐圧が高くな
るため、エレクトロルミネッセンスのディスプレイの駆
動が可能である。& If a thin film transistor with an offset gate structure in which the gate electrode 2 does not overlap the drain region made of a semiconductor layer doped with high concentration impurities as shown in FIG. 4 is used,
Since the electric field concentration near the surface of the drain layer is relaxed and the withstand voltage is increased, it is possible to drive an electroluminescent display.
第１図は、従来の非晶質シ゛リコン乞用いた薄膜トラン
ジスターの断面図である。第２〜４図は、本発明による
多結晶シリコンケ用いた薄膜トランジスターの断面図で
あり、第２図は、自己整合性が無いもの、第３図は自己
整合性２有するもの、第４図は、オフセットゲート構造
のものである。
１・・・・・・透明ガラス ２・・・・・・ゲート電極
３・・・・・・ゲート絶縁膜 ４・・・・・・非晶質シ
リコン膜４′・・・・・・多結晶シリコン膜 ５・・・
・・・ソース領域５′・・・・・打込みで形成された新
たなソース領域６・・・・・・ドレイン領域
６′・・・・・・打込みで形成された新たなドレイン領
域７・・・・・・ソース電極端子
８・・・・・・ドレイン電極端子
９・・・・・・コンタクトホール。
以上
出願人 株式会社諏訪精工舎
代理人弁理士 最 上 務
第２図
第４図FIG. 1 is a cross-sectional view of a conventional thin film transistor using amorphous silicon. Figures 2 to 4 are cross-sectional views of thin film transistors using polycrystalline silicon according to the present invention. Figure 2 shows one without self-alignment, Figure 3 shows one with self-alignment 2, and Figure 4 shows one with self-alignment. , which has an offset gate structure. 1... Transparent glass 2... Gate electrode 3... Gate insulating film 4... Amorphous silicon film 4'... Polycrystalline Silicon film 5...
... Source region 5' ... New source region 6 formed by implantation ... Drain region 6' ... New drain region 7 formed by implantation . . . Source electrode terminal 8 . . . Drain electrode terminal 9 . . . Contact hole. Applicant: Suwa Seikosha Co., Ltd. Representative Patent Attorney Tsutomu Mogami Figure 2 Figure 4
Claims (4)
して用いた薄膜トランジスターにおいて、ソースφドレ
イン領域Ｚ高濃度不純物を添加した半導体層より形成し
、該領域の上に不純物を添加しない真性多結晶半導体層
とゲート絶縁膜層とゲート電極層乞順次積層した構造Ｚ
％徴とする薄膜トランジスター。(1) In a thin film transistor using a semiconductor thin film deposited on an insulating substrate as an active region, the source φ drain region Z is formed from a semiconductor layer doped with a high concentration of impurities, and an intrinsic multilayer transistor with no impurities added above the region is formed. Structure Z in which a crystalline semiconductor layer, a gate insulating film layer, and a gate electrode layer are sequentially laminated
Thin film transistor with % characteristics.
ある特許請求の範囲第１項記載の薄膜トランジスター。(2) The thin film transistor according to claim 1, wherein the intrinsic polycrystalline semiconductor layer is a polycrystalline silicon thin film.
た半導体層からなるドレイン領域上に重ならないオフセ
ットゲート構造をもつ特許請求の範囲第１項記載の薄膜
トランジスター。(3) The gate electrode has the above-mentioned high concentration impurity! The thin film transistor according to claim 1, having an offset gate structure that does not overlap the drain region made of the semiconductor layer doped with Iyl.
のソース・ドレイン領域上に重ならない構造で、かつソ
ース・ドレイン領域の不純物と同型のイオンの打込みｔ
ゲート電極をマスクに行ない、新たにソース・ドレイン
領域を形成した特許請求の範囲第１項記載の薄膜トラン
ジスター。(4) Implantation of ions of the same type as the impurity in the source/drain region in a structure in which the gate electrode does not overlap the source/drain region of the semiconductor layer to which the impurity concentration Z has been increased.
2. The thin film transistor according to claim 1, wherein source and drain regions are newly formed using the gate electrode as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10770784A JPS60251667A (en) | 1984-05-28 | 1984-05-28 | Thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10770784A JPS60251667A (en) | 1984-05-28 | 1984-05-28 | Thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60251667A true JPS60251667A (en) | 1985-12-12 |
Family
ID=14465903
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10770784A Pending JPS60251667A (en) | 1984-05-28 | 1984-05-28 | Thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60251667A (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61150278A (en) * | 1984-12-25 | 1986-07-08 | Toshiba Corp | Thin film transistor |
| JPS6386572A (en) * | 1986-09-30 | 1988-04-16 | Seiko Epson Corp | Thin film transistor |
| JPS6386571A (en) * | 1986-09-30 | 1988-04-16 | Seiko Epson Corp | Thin film transistor |
| JPS6386573A (en) * | 1986-09-30 | 1988-04-16 | Seiko Epson Corp | Thin film transistor |
| JPS6386570A (en) * | 1986-09-30 | 1988-04-16 | Seiko Epson Corp | Thin film transistor |
| JPS63107068A (en) * | 1986-09-30 | 1988-05-12 | Seiko Epson Corp | Thin film transistor |
| JPS63190386A (en) * | 1986-10-03 | 1988-08-05 | Seiko Epson Corp | Thin-film transistor and manufacture thereof |
| US4821091A (en) * | 1986-07-22 | 1989-04-11 | The United States Of America As Represented By The United States Department Of Energy | Polysilicon photoconductor for integrated circuits |
| JPH01136373A (en) * | 1987-11-24 | 1989-05-29 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of thin-film semiconductor device |
| JPH0230147A (en) * | 1988-07-19 | 1990-01-31 | Nec Corp | Manufacture of thin film transistor |
| JPH07183520A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Thin film transistor |
| US5648663A (en) * | 1985-08-05 | 1997-07-15 | Canon Kabushiki Kaisha | Semiconductor structure having transistor and other elements on a common substrate and process for producing the same |
| DE4445568C2 (en) * | 1994-12-19 | 2002-11-28 | Korea Electronics Telecomm | Method of manufacturing a thin film transistor |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58105574A (en) * | 1981-12-17 | 1983-06-23 | Seiko Epson Corp | Thin film transistor |
| JPS58115864A (en) * | 1981-12-28 | 1983-07-09 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
| JPS58123772A (en) * | 1982-01-19 | 1983-07-23 | Canon Inc | Semiconductor element |
| JPS58142566A (en) * | 1982-02-19 | 1983-08-24 | Seiko Epson Corp | Thin film semiconductor device |
-
1984
- 1984-05-28 JP JP10770784A patent/JPS60251667A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58105574A (en) * | 1981-12-17 | 1983-06-23 | Seiko Epson Corp | Thin film transistor |
| JPS58115864A (en) * | 1981-12-28 | 1983-07-09 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device |
| JPS58123772A (en) * | 1982-01-19 | 1983-07-23 | Canon Inc | Semiconductor element |
| JPS58142566A (en) * | 1982-02-19 | 1983-08-24 | Seiko Epson Corp | Thin film semiconductor device |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS61150278A (en) * | 1984-12-25 | 1986-07-08 | Toshiba Corp | Thin film transistor |
| US5648663A (en) * | 1985-08-05 | 1997-07-15 | Canon Kabushiki Kaisha | Semiconductor structure having transistor and other elements on a common substrate and process for producing the same |
| US4821091A (en) * | 1986-07-22 | 1989-04-11 | The United States Of America As Represented By The United States Department Of Energy | Polysilicon photoconductor for integrated circuits |
| JPS6386572A (en) * | 1986-09-30 | 1988-04-16 | Seiko Epson Corp | Thin film transistor |
| JPS6386571A (en) * | 1986-09-30 | 1988-04-16 | Seiko Epson Corp | Thin film transistor |
| JPS6386573A (en) * | 1986-09-30 | 1988-04-16 | Seiko Epson Corp | Thin film transistor |
| JPS6386570A (en) * | 1986-09-30 | 1988-04-16 | Seiko Epson Corp | Thin film transistor |
| JPS63107068A (en) * | 1986-09-30 | 1988-05-12 | Seiko Epson Corp | Thin film transistor |
| JPS63190386A (en) * | 1986-10-03 | 1988-08-05 | Seiko Epson Corp | Thin-film transistor and manufacture thereof |
| JPH01136373A (en) * | 1987-11-24 | 1989-05-29 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of thin-film semiconductor device |
| JPH0230147A (en) * | 1988-07-19 | 1990-01-31 | Nec Corp | Manufacture of thin film transistor |
| JPH07183520A (en) * | 1993-12-24 | 1995-07-21 | Nec Corp | Thin film transistor |
| DE4445568C2 (en) * | 1994-12-19 | 2002-11-28 | Korea Electronics Telecomm | Method of manufacturing a thin film transistor |
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