JPS60241146A - Fault detecting method - Google Patents

Fault detecting method

Info

Publication number
JPS60241146A
JPS60241146A JP59098280A JP9828084A JPS60241146A JP S60241146 A JPS60241146 A JP S60241146A JP 59098280 A JP59098280 A JP 59098280A JP 9828084 A JP9828084 A JP 9828084A JP S60241146 A JPS60241146 A JP S60241146A
Authority
JP
Japan
Prior art keywords
signal
line
terminal side
transmission
pio4
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59098280A
Other languages
Japanese (ja)
Inventor
Takeshi Yumura
湯村　武
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Sanyo Denki Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd, Sanyo Denki Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP59098280A priority Critical patent/JPS60241146A/en
Publication of JPS60241146A publication Critical patent/JPS60241146A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/17—Interprocessor communication using an input/output type connection, e.g. channel, I/O port
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Debugging And Monitoring (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE:To detect the fault of a device set at the reception side by checking the state of the cotrol signal of said device by means of a control line that is not used in a transmission mode prior to the transmission. CONSTITUTION:A control line 5 is allocated for input with a PIO3 at the host side and for output with a PIO4 at the terminal side respectively. Therefore the line 5 is set at a high level in case a power supply of the terminal side is not applied and the PIO4 is not set in any mode. Then the line 5 is changed to a low level only when the power supply is applied or the PIO4 is set in a prescribed mode. The level of the line 5 is checked at the host side before a signal ATN is produced from the PIO3. Then the signal ATN is transmitted if the line 5 is set at a low level. While it is decided that the terminal side has a fault when the line 5 is kept at a high level. Thus no transmission of the signal is carried out, and the prescribed error processing is carried out.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は例えばコンピュータシステムのホストとなる演
算処理装置と、フロッピーディスクドライブ、文字認識
装置等のインテリジェントターミナル装置との間で行わ
れるハンドシェイク通信における異常を検出する方法に
関し、更に詳述すればインテリジェントターミナル装置
が異常である場合に演算処理装置がハングアップする等
の事態を招来することを未然に防止し得る異常検知方法
を提案するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to handshake communication performed between an arithmetic processing unit serving as a host of a computer system and an intelligent terminal device such as a floppy disk drive or a character recognition device. More specifically, this paper proposes an anomaly detection method that can prevent situations such as hang-up of the processing unit when the intelligent terminal device is abnormal. be.

〔従来技術〕[Prior art]

前述の如きシステムにおけるハンドシェイク通信は、ホ
スト側からターミナル側に対してこれを呼出すための信
号を発し、ターミナル側から、データ受取の準備完了を
示す信号を得てデータを送り出すという手順で行われる
。従ってターミナル側に異常が存在する場合は、ホスト
側がハングアップしてしまう。Handshake communication in the system described above is carried out in the following steps: the host side issues a signal to call the terminal side, the terminal side receives a signal indicating that it is ready to receive data, and then sends out the data. . Therefore, if there is an abnormality on the terminal side, the host side will hang up.

このため、ホスト側において通信中断指示を行わせるべ
き所定のキーを操作することによりソフトウェア的にハ
ングアンプを防止することが考えられるが、逆に通信中
にこのキーを誤操作するとターミナル側がハングアンプ
するという虞れがある。またホスト側においてターミナ
ル側の状態を知るにはポート或いは割込み等の回路を付
加する必要があるという難点がある。For this reason, it is possible to prevent hangs using software by operating a predetermined key on the host side that should issue a communication interruption instruction, but conversely, if this key is pressed incorrectly during communication, the terminal side may hang. There is a possibility that. Another drawback is that it is necessary to add a port or interrupt circuit in order for the host side to know the status of the terminal side.

〔目的〕〔the purpose〕

本発明はこのような従来技術の問題点を解決するために
なされたものであって、特別な回路を追加することなく
、また複雑なソフトウェアの処理を要することなくター
ミナル側の状態を検知することができる異常検知方法を
提供することを目的とする。The present invention was made to solve the problems of the prior art, and it is possible to detect the status of the terminal side without adding a special circuit or requiring complicated software processing. The purpose of this study is to provide an anomaly detection method that can detect abnormalities.

〔構成〕〔composition〕

本発明に係る異常検知方法はハンドシェイクによる通信
の受信側装置の異常を検知する方法において、送信に先
立ち、受信側装置の制御用信号の状態を調べることを特
徴とする。An abnormality detection method according to the present invention is a method for detecting an abnormality in a receiving device in handshake communication, and is characterized by checking the state of a control signal of the receiving device prior to transmission.

〔実施例〕〔Example〕

以下本発明をその実施例を示す図面に基づいて詳述する
。DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

図面は本発明の実施例を示すブロック図である。The drawing is a block diagram showing an embodiment of the invention.

図において１はホスト側のＣＰＩＩ　（中央処理装置）
、２はターミナル側のＣＰＵであり、両者はホスト側、
ターミナル個人々のＰＩＯプログラマブル入出力装置３
，４を介して接続されてハンドシェイク通信を行う。Ｐ
ＩＯ３，４としては例えばインテル社製８２５５が用い
られる。ＰＩＯ３，４は夫々、３つのボート３Ａ、３Ｂ
、３Ｇ、４Ａ、４Ｂ、４Ｇを有し、３線ハンドシ工イク
通信を行うためにボー）３Ａ、３Ｂ　、４Ａ、４Ｂをデ
ータの人、出力に用い、ボート３Ｃ，４Ｇを通信の制御
用に用いることとし、ソフトウェアにてボート３Ａ、’
　４Ａをデータ入力用、ボート３Ｂ、４Ｂをデータ出力
用に割りつげ、更にボート３Ｃ，４Ｇの各８ビツトのう
ち、４ビツトを制御用信号入力用に、他の４ピノ１−を
制御用信号出力用に割りつＬＪる。そして両 ＰＩＯの入力用と出力用とを相互に接続する。In the figure, 1 is the CPII (central processing unit) on the host side.
, 2 is the CPU on the terminal side, and both are on the host side,
Terminal individual PIO programmable input/output device 3
, 4 to perform handshake communication. P
As the IO3 and IO4, for example, Intel 8255 is used. PIO3 and 4 are respectively three boats 3A and 3B.
, 3G, 4A, 4B, and 4G, and in order to perform 3-wire handshake communication, 3A, 3B, 4A, and 4B are used for data output, and boats 3C and 4G are used for communication control. We will use boat 3A,' in the software.
4A is allocated for data input, boats 3B and 4B are allocated for data output, and of the 8 bits each of ports 3C and 4G, 4 bits are allocated for control signal input, and the other 4 pins 1- are allocated for control signal input. Separate LJ for output. Then, the input and output terminals of both PIOs are connected to each other.

次に制御用信号の内容につき説明する。ＰＩＯ３が出力
する信号ＡＴＮはホスト側がターミナル側を呼び出すた
めの信号であり、送信が開始されることを報じる。ＰＩ
Ｏ４が出力する信号ＲＦＤはターミナル側でデータの受
取準備が完了したことを報じるための信号である。ＰＩ
Ｏ３が出力する信号ＤＡＶはホスト側が出力ボート３Ｂ
にデータをのせたことを報じる信号であり、ＰＩＯ４が
出力する信号ＤＡＣはターミナル側がデータを受取った
ことを報じる信号である。Next, the contents of the control signal will be explained. The signal ATN outputted by the PIO3 is a signal for the host side to call the terminal side, and reports that transmission is to be started. P.I.
The signal RFD output by O4 is a signal for reporting that the terminal side is ready to receive data. P.I.
The signal DAV output by O3 is output by the host side to output port 3B.
This is a signal that reports that data has been loaded onto the terminal, and the signal DAC output by PIO4 is a signal that reports that the terminal side has received data.

その他、ターミナル側からホスト側へデータを送信する
ことも有り、この場合は、データを出力ボートにのせた
ことを報じる信号ＤＡＶはＰＩＯ４から、また受取準備
の完了を示す信号ＲＦＤ、データ受取を示す信号ＤＡＣ
はＰＩＯ３から発せられる。なお上述の信号はいずれも
ハイアクティブである。In addition, data may be sent from the terminal side to the host side. In this case, the signal DAV reporting that data has been placed on the output boat is sent from PIO4, and the signal RFD indicating completion of reception preparation, indicating data reception. signal DAC
is emitted from PIO3. Note that all of the above-mentioned signals are high active.

上述したところから理解されるように送信の手順は以下
のようになる。即ち、ホスト側からデータを送信する場
合に、信号ＡＴＮをハイレベルとし、ターミナル側の信
号ＲＦＤがハイレヘルになるのを待つ。信号ＲＦＤがハ
イレベルになると、化カポ−）３Ｂにデータを出力する
と共に信号ＤＡＶをハイレベルにする。そしてターミナ
ル側からの信号ＤＡＣを待ってそのデータ受取を確認し
て一つのデータの送信が終了する。As understood from the above, the transmission procedure is as follows. That is, when transmitting data from the host side, the signal ATN is set to high level and waits until the signal RFD on the terminal side becomes high level. When the signal RFD goes high, data is output to the converter capacitor 3B and the signal DAV goes high. Then, it waits for the signal DAC from the terminal side, confirms the reception of the data, and completes the transmission of one data.

而してＰＩＯ３，４のボート３Ｃ，４Ｃを結ぶ制御ライ
ンの１本が使用されないままになっている。本発明はこ
の制御ライン５を利用して通信の可否を検知するもので
ある。この制御ライン５はホスト側のＰｒｏ　３には入
力用に、ターミナル側のＰＩＯ４には出力用に割付けら
れている。従ってターミナル側の電源が入って、Ｌ）な
い場合、ＰＩＯ４がモードセットされていない場合等に
あってはこの制御ライン５のレベルはハイレベルにある
。そして電源が入れられて、或いはＰｒｏ　４が所定の
モードにセットされてはじめて制御ライン５はローレベ
ルとなる。Therefore, one of the control lines connecting the boats 3C and 4C of PIOs 3 and 4 remains unused. The present invention utilizes this control line 5 to detect whether or not communication is possible. This control line 5 is assigned to the Pro 3 on the host side for input, and to the PIO 4 on the terminal side for output. Therefore, when the power on the terminal side is turned on and there is no L), or when the PIO 4 is not set to a mode, the level of this control line 5 is high. The control line 5 goes low only after the power is turned on or the Pro 4 is set to a predetermined mode.

本発明方法は送信に先立ち、つまりホスト側のｐｉｏか
ら信号ＡＴＮを発する前にホスト側にて制御ライン５０
レベルを調べ、これがローレベルにあれば前述した如き
手順にて送信を行う。これに対してハイレベルにあれば
ターミナル側に異常有りと判断して、送信は行わず、所
定のエラー処理を行う。これによりポスト側のハングア
ップは回避されることになる。In the method of the present invention, prior to transmission, that is, before issuing the signal ATN from PIO on the host side, the control line 50 is
The level is checked, and if it is low level, transmission is performed using the procedure described above. On the other hand, if it is at a high level, it is determined that there is an abnormality on the terminal side, no transmission is performed, and predetermined error handling is performed. This will avoid hang-ups on the post side.

〔効果〕〔effect〕

叙上の如き本発明方法による場合は受信側装置の異常に
よって送信側装置がハングアップするという事態の発生
は防止される。またこの防止のために特別な回路を設け
る必要がな（、また複雑なソフトウェア処理をも必要と
しない。なお本発明はコンピユークシステムにおける演
算処理装置とインテリジェントターミナル装置との間の
通信に限らず、ハンドシェイク通信一般に広く適用でき
る。According to the method of the present invention as described above, the occurrence of a situation in which the transmitting side device hangs up due to an abnormality in the receiving side device can be prevented. In addition, there is no need to provide a special circuit to prevent this (and no complicated software processing is required.The present invention is not limited to communication between an arithmetic processing unit and an intelligent terminal device in a computer system. , can be widely applied to handshake communication in general.

【図面の簡単な説明】[Brief explanation of drawings]

図面ば本発明の実施例を示すプロ・ツク図である。 １．２・・・ＣＰＵ　３．　４・・・ＰＩＯ５・・・制
御ライン特　許　出願人　三洋電機株式会社 代理人　弁理士　河　野　登　夫The drawing is a process diagram showing an embodiment of the present invention. 1.2...CPU 3. 4...PIO5...Control line patent Applicant: Sanyo Electric Co., Ltd. Agent Patent attorney: Noboru Kono

Claims (1)

【特許請求の範囲】[Claims] １、　ハンドシェイクによる通信の受信側装置の異常を
検知する方法において、送信に先立ち、受信側装置の制
御用信号の状態を調べることを特徴とする異常検知方法
。1. An abnormality detection method for detecting an abnormality in a receiving device in handshake communication, which is characterized by checking the state of a control signal in the receiving device prior to transmission.
JP59098280A 1984-05-15 1984-05-15 Fault detecting method Pending JPS60241146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59098280A JPS60241146A (en) 1984-05-15 1984-05-15 Fault detecting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59098280A JPS60241146A (en) 1984-05-15 1984-05-15 Fault detecting method

Publications (1)

Publication Number Publication Date
JPS60241146A true JPS60241146A (en) 1985-11-30

Family

ID=14215517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59098280A Pending JPS60241146A (en) 1984-05-15 1984-05-15 Fault detecting method

Country Status (1)

Country Link
JP (1) JPS60241146A (en)

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