JPS60234982A - Formation of pattern - Google Patents

Formation of pattern

Info

Publication number
JPS60234982A
JPS60234982A JP9103284A JP9103284A JPS60234982A JP S60234982 A JPS60234982 A JP S60234982A JP 9103284 A JP9103284 A JP 9103284A JP 9103284 A JP9103284 A JP 9103284A JP S60234982 A JPS60234982 A JP S60234982A
Authority
JP
Japan
Prior art keywords
etching
resist
etched
processed
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9103284A
Other languages
Japanese (ja)
Inventor
Takeshi Sugawara
毅 菅原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alps Alpine Co Ltd
Original Assignee
Alps Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alps Electric Co Ltd filed Critical Alps Electric Co Ltd
Priority to JP9103284A priority Critical patent/JPS60234982A/en
Publication of JPS60234982A publication Critical patent/JPS60234982A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/02Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process

Abstract

PURPOSE:To reduce the side etching and to form high-density patterns by curing a resist on a material to be processed which is side-etched during the etching, welding the resist to the side surface of the material to be processed, and etching again. CONSTITUTION:An etching resist 1 is formed on a material 2 to be processed on a substrate 3 in specified patterns, and the material is immersed in an etching liquid. The etching is temporarily stopped when about the half of the thicknes (t) of the material to be processed is etched. Then the etching is carried out at a temp. at which a resist flow of the etching resist 1 is caused, and the resist 1 shaped like an eaves is again welded to the material 2 to be processed. The etching is then started again. Consequently, the side etching A can be controlled to less than the half of the conventional side etching, and the minimum width D of the processed pattern can be made equal to the thickness (t) of the material 2 to be processed.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、フォトリソグラフィ技術およびエツチングを
用いて高密度配線を可能にするパターン形成方法に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a pattern forming method that enables high-density wiring using photolithography technology and etching.

〔発明の背景〕[Background of the invention]

従来、ウェット・エツチングによってパターン形成を行
なう場合には、第1図(a)に示すごとく、パターンと
して残したい被加工物2上にエツチングレジスト1をフ
ォトリングラフィ技術を用いて形成し、これをエツチン
グ液に浸しかつそれにより不要部を除去して所望のパタ
ーンを得ている。
Conventionally, when forming a pattern by wet etching, as shown in FIG. 1(a), an etching resist 1 is formed using photolithography technology on a workpiece 2 that is to be left as a pattern. The desired pattern is obtained by immersing it in an etching solution and thereby removing unnecessary parts.

ウェット書エツチングにおいて、エツチングは等方的に
進行するので、被加工物2の厚さをtとすると、エツチ
ング終了時点では、第2図に示すごとく、横方向にも概
ねtに等しいだけのエツチング(サイドエッチまたはオ
ーバーエッチ)Bが発生する。したがって、パターン幅
りが2を以下になると、このサイドエッチBが被加工物
2の全面にわたるようになるので、厚さtが保たれなく
なる。すなわち、被加工物2の厚さをtとすれば、最小
加エバターン幅は概略2tである。
In wet book etching, etching progresses isotropically, so if the thickness of the workpiece 2 is t, at the end of etching, as shown in FIG. 2, the etching is approximately equal to t in the lateral direction. (Side etch or over etch) B occurs. Therefore, if the pattern width becomes less than 2, the side etch B will cover the entire surface of the workpiece 2, and the thickness t will no longer be maintained. That is, if the thickness of the workpiece 2 is t, then the minimum processed evaporation width is approximately 2t.

〔発明の目的] 本発明の目的は、上記従来技術の欠点に鑑みてなされた
もので、サイドエッチを従来の半分以下に押えて高密度
配線を可能にするパターン形成方法を提供することにあ
る。
[Object of the Invention] The object of the present invention was made in view of the above-mentioned drawbacks of the conventional techniques, and it is an object of the present invention to provide a pattern forming method that enables high-density wiring by suppressing side etching to less than half of the conventional technique. .

〔発明の概要〕[Summary of the invention]

上記目的を達成するために、本発明によるパターン形成
方法は、被エツチング層上に所定パターンでレジストを
形成し、該レジストが形成されていない被エツチング層
を所定月までエツチングするとともに前記レジストで覆
われた被エツチング層の側面をサイドエツチングし、こ
の後エツチングを一旦停止してサイドエツチングされた
被エツチング層上のレジストをキュアすることによって
被エツチング層の側面な枳い、そしてこの後再び前記レ
ジストが形成されていない被エツチング層をエツチング
してなることを特徴とする。
In order to achieve the above object, a pattern forming method according to the present invention involves forming a resist in a predetermined pattern on a layer to be etched, etching the layer to be etched on which the resist is not formed to a predetermined extent, and covering it with the resist. The side surface of the layer to be etched is side-etched, and then the etching is temporarily stopped and the resist on the side-etched layer to be etched is cured to remove the side surface of the layer to be etched. It is characterized in that it is formed by etching a layer to be etched that does not have a layer formed thereon.

〔発明の実施例〕[Embodiments of the invention]

以下に本発明によるパターン形成方法をl$3図(a)
および(b)を用いて説明するが、該パターン形成方法
における前段は従来技術の形成方法と同一であるので第
1図(a)および(b)も併せて参照し、図中同一符号
を同一部分を示すものとする。
The pattern forming method according to the present invention is shown below in Figure 3 (a).
The first stage of the pattern forming method is the same as the forming method of the prior art, so please also refer to FIGS. shall indicate the part.

基板3上にパターンと[7て残したい被加工物(初エツ
チングi)2上に、第1F31(a)に示すごとく、エ
ツチングレジスト1を形成し、これをエツチング液に浸
して、エツチングが第1図(1))に示すごとく、被加
工物の厚さの約半分だけ進行したノ・−7エツチングの
状態で、一旦エッチングを停止し、エツチングレジスト
1がレジストフローを起す温度でキュアを行なう。する
と第3図(a)に示すごとく、ひさし状になったレジス
ト1が被加工物2に再び融着する。この後再びエツチン
グを再開すればエツチング終了時には第3図(b)に示
すごとくなる。
Form an etching resist 1 on the pattern on the substrate 3 and on the workpiece (initial etching i) 2 to be left as shown in 1F31(a), immerse it in an etching solution, and perform the etching process. As shown in Figure 1 (1)), in the No-7 etching state where approximately half the thickness of the workpiece has been etched, the etching is temporarily stopped and etching resist 1 is cured at a temperature that causes resist flow. . Then, as shown in FIG. 3(a), the eaves-shaped resist 1 is fused to the workpiece 2 again. If etching is restarted after this, the result will be as shown in FIG. 3(b) when etching is completed.

本発明の実施例において、エツチングレジストとしてエ
ツチング70−を起すフォトレジスト、例えば東京応化
製OMR−1’13を用いて、エツチング途中にキュ゛
アを行なうことによってサイドエッチA(第3図(b)
)を、第2図に示した従来のサイドエッチB(÷t)の
約半分υ下に押えることが可能となる。
In the embodiment of the present invention, a photoresist that causes etching 70-, such as OMR-1'13 manufactured by Tokyo Ohka Co., Ltd., is used as the etching resist, and by performing curing during etching, side etching A (see Fig. 3 (b)) is performed. )
) can be suppressed to approximately half υ of the conventional side etch B(÷t) shown in FIG.

したがって、被加工物2の厚さをtとすれば、最小加エ
バターン幅りは概略tとなり、第2図に関連して示した
従来の倍の高密度パターンの形成が可能となる。かかる
高密度パターンの配MKついての比較は写真を用いて行
なうのが最良ではあるが一例として第4図(a)および
(b)を用いてパターン密度を比較すると、サイドエッ
チの小さい本発明によるパターン間の間隔が約22μで
あるのに対し、−サイドエッチの大きい従来例におい【
は約41μとなり、本発明によれば高密度化が図れるこ
とは明らかである。なお、第4図(a)および(b)に
おいて被加工物2の厚さtは同一として比較している。
Therefore, if the thickness of the workpiece 2 is t, the minimum width of the processed evaporation is approximately t, making it possible to form a pattern with twice the density as in the conventional pattern shown in connection with FIG. Although it is best to compare the distribution MK of such high-density patterns using photographs, as an example, when comparing the pattern densities using FIGS. The spacing between patterns is approximately 22μ, whereas in the conventional example with large side etch,
is approximately 41μ, and it is clear that high density can be achieved according to the present invention. Note that in FIGS. 4(a) and 4(b), the thickness t of the workpiece 2 is the same for comparison.

さらに、上記実施例において、エツチング途中のキュア
は1回に限らず、レジストの損傷がないならば、繰り返
して出来るのて、サイドエッチをさらに小さくすること
ができる。
Furthermore, in the above embodiment, curing during etching is not limited to one time, but can be repeated if the resist is not damaged, thereby making it possible to further reduce side etching.

〔発明の効果〕〔Effect of the invention〕

叙上のごとく、本発明によれば、エツチング途中で、サ
イドエツチングされた被加工物(被エツチング層)上の
レジストをキュアすることによって被加工物の側面に融
着させて覆い、この後再びレジストが形成されていない
被加工物層をエツチングするので、サイドエツチングを
小さくすることができ、それにより高密度のパターンを
形成することができるという著効を有するパターン形成
方法を提供することができる。
As described above, according to the present invention, during etching, the resist on the side-etched workpiece (etched layer) is cured so as to be fused and covered with the side surface of the workpiece, and then the resist is re-etched. Since the workpiece layer on which no resist is formed is etched, it is possible to reduce side etching, thereby providing a pattern forming method that has the remarkable effect of forming a high-density pattern. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)e (b)および第2図は従来例を示す概
略図、第3図(a)および(blは本発明によるパター
ン形成方法を示す概略図、第4図(a)および(b)は
パターン密度を比較するために示すそれぞれ本発明によ
るパターン密度と従来例のパターン密度の概略図である
。 1・・・・・・レジスト、2・・・・・・被加工物(被
エツチング層)、A・・・−・・サイドエッチ、D・・
・・・・パターン幅、t・・・・・・被加工物の厚さ。 第1図 第2図 第3図 第4図 (b)
FIGS. 1(a) and 2(b) are schematic diagrams showing a conventional example, FIGS. 3(a) and (bl are schematic diagrams showing a pattern forming method according to the present invention, and FIGS. 4(a) and 2). (b) is a schematic diagram of the pattern density according to the present invention and the pattern density of a conventional example shown for comparison of pattern densities. 1... Resist, 2... Workpiece ( layer to be etched), A...- side etching, D...
...Pattern width, t...Thickness of the workpiece. Figure 1 Figure 2 Figure 3 Figure 4 (b)

Claims (1)

【特許請求の範囲】[Claims] 被エツチング層上に所定パターンでレジストを形成し、
該レジストが形成されていない被エツチング層を所定量
までエツチングするとともに前記レジストで覆われた被
エツチング層の側面をサイドエツチングし、この後エツ
チングを一旦停止してサイドエツチングされた前記被エ
ツチング層上のレジストをキュアすることによって前記
被エツチング層の側面を覆い、そしてこの後再び前記レ
ジストが形成されていない被エツチング層をエツチング
してなることを特徴とするパターン形成方法。
A resist is formed in a predetermined pattern on the layer to be etched,
The layer to be etched on which the resist is not formed is etched to a predetermined amount, and the side surface of the layer to be etched covered with the resist is side-etched, and then etching is temporarily stopped and the layer to be etched that has been side-etched is etched. A pattern forming method comprising: curing a resist to cover the side surfaces of the layer to be etched, and then etching the layer to be etched on which the resist is not formed again.
JP9103284A 1984-05-09 1984-05-09 Formation of pattern Pending JPS60234982A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9103284A JPS60234982A (en) 1984-05-09 1984-05-09 Formation of pattern

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9103284A JPS60234982A (en) 1984-05-09 1984-05-09 Formation of pattern

Publications (1)

Publication Number Publication Date
JPS60234982A true JPS60234982A (en) 1985-11-21

Family

ID=14015168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9103284A Pending JPS60234982A (en) 1984-05-09 1984-05-09 Formation of pattern

Country Status (1)

Country Link
JP (1) JPS60234982A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1143776A1 (en) * 1998-07-22 2001-10-10 Ibiden Co., Ltd. Printed-circuit board and method of manufacture thereof
JP2007317852A (en) * 2006-05-25 2007-12-06 Fujikura Ltd Printed circuit board and inter-board connecting structure
US8222531B2 (en) 2006-05-25 2012-07-17 Fujikura Ltd. Printed wiring board, method for forming the printed wiring board, and board interconnection structure
US8227710B2 (en) 2006-12-22 2012-07-24 Tdk Corporation Wiring structure of printed wiring board and method for manufacturing the same
KR101504348B1 (en) * 2007-02-28 2015-03-19 티디케이가부시기가이샤 Wiring structure, forming method of the same and printed wiring board

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1143776A1 (en) * 1998-07-22 2001-10-10 Ibiden Co., Ltd. Printed-circuit board and method of manufacture thereof
US6809415B2 (en) 1998-07-22 2004-10-26 Ibiden Co., Ltd. Printed-circuit board and method of manufacture thereof
EP1143776A4 (en) * 1998-07-22 2006-05-03 Ibiden Co Ltd Printed-circuit board and method of manufacture thereof
JP2007317852A (en) * 2006-05-25 2007-12-06 Fujikura Ltd Printed circuit board and inter-board connecting structure
US8222531B2 (en) 2006-05-25 2012-07-17 Fujikura Ltd. Printed wiring board, method for forming the printed wiring board, and board interconnection structure
US8492657B2 (en) 2006-05-25 2013-07-23 Fujikura Ltd. Printed wiring board, method for forming the printed wiring board, and board interconnection structure
US8227710B2 (en) 2006-12-22 2012-07-24 Tdk Corporation Wiring structure of printed wiring board and method for manufacturing the same
KR101412258B1 (en) * 2006-12-22 2014-06-25 티디케이가부시기가이샤 Wiring structure of printed wiring board and method for manufacturing the same
KR101504348B1 (en) * 2007-02-28 2015-03-19 티디케이가부시기가이샤 Wiring structure, forming method of the same and printed wiring board

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