JPS60234367A - Mis-type field effect transistor - Google Patents
Mis-type field effect transistorInfo
- Publication number
- JPS60234367A JPS60234367A JP59089415A JP8941584A JPS60234367A JP S60234367 A JPS60234367 A JP S60234367A JP 59089415 A JP59089415 A JP 59089415A JP 8941584 A JP8941584 A JP 8941584A JP S60234367 A JPS60234367 A JP S60234367A
- Authority
- JP
- Japan
- Prior art keywords
- concentration
- layer
- offset
- low
- relatively high
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000005669 field effect Effects 0.000 title claims description 5
- 239000012535 impurity Substances 0.000 claims description 13
- 238000009792 diffusion process Methods 0.000 claims description 6
- 229910052785 arsenic Inorganic materials 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 9
- 239000000758 substrate Substances 0.000 abstract description 8
- 150000002500 ions Chemical class 0.000 abstract description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000005530 etching Methods 0.000 abstract description 2
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 230000004913 activation Effects 0.000 abstract 2
- 230000015572 biosynthetic process Effects 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 12
- 230000007423 decrease Effects 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000005684 electric field Effects 0.000 description 2
- 241000277269 Oncorhynchus masou Species 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔技術分野〕
本発明は内部抵抗の低減と耐圧の向上を図ったオフセッ
ト構造のＭＩＳ型電界効果トランジスタ（ＭＩ ５ＦＥ
Ｔ ）Ｋ関するものである。[Detailed Description of the Invention] [Technical Field] The present invention relates to a MIS field effect transistor (MI 5FE) with an offset structure that reduces internal resistance and improves breakdown voltage.
T) This is related to K.
ＭＩＳＦＥＴのドレイン耐圧を向上するために、ゲート
電極とドレイン領域との間にオンセット領域を設けたＬ
Ｄ Ｄ （Ｌｉｇｈｌｙ Ｄｏｐｅｄ Ｄｒａｉｎ
）構造と称するオフセット構造のＭＩ ５ＦＥＴが提案
されて（・る（ＩＥＥＥ ＴＲＡＮＳＡＣＴＩＯＮＯＮ
ＥＬＥＣＴＲＯＮ ＤＥＶＩＣＥＳ、ＶＯＬ。In order to improve the drain breakdown voltage of MISFET, an onset region is provided between the gate electrode and the drain region.
D D (Lightly Doped Drain
) structure, an offset structure MI 5FET has been proposed (IEEE TRANSACTIONON
ELECTRON DEVICES, VOL.
ＥＤ ２９．ｐｐ ５９０−５９５．ＡＰＲＩＬ１９８
２）。例えば、第１図に示すように、半導体基板１の主
面上にゲート絶縁膜２を介してゲート電極３をバターニ
ング形成した上で不純物を低濃度てイオン打込みし、そ
の後ゲート電極３の側部忙サイドウオール４を形成して
今度は高濃度に不純物をイオン打込みすることにより、
低濃度のオフセット部５を介して高濃度のソース０ドレ
イン領域６を配置したり、ＤＤ構造のＭＩＳＦＥＴ７を
完成できる。ED 29. pp 590-595. APRIL198
2). For example, as shown in FIG. 1, a gate electrode 3 is patterned on the main surface of a semiconductor substrate 1 through a gate insulating film 2, and then impurity ions are implanted at a low concentration, and then the side of the gate electrode 3 is patterned. By forming the side wall 4 and implanting impurity ions at a high concentration,
A highly doped source 0 drain region 6 can be placed via a lightly doped offset portion 5, and a DD structure MISFET 7 can be completed.
このＬＤＤ構造によれば、低濃度に形成したオフセット
部５０作用によりドレイン領域６とゲート電極３との間
の電界を緩和してドレイン耐圧の向上を図る一方で、チ
ャネルをドレイン領域６に接続してＭＩＳＦＥＴの動作
を保障することになる。According to this LDD structure, the electric field between the drain region 6 and the gate electrode 3 is relaxed by the effect of the offset portion 50 formed at a low concentration, and the drain breakdown voltage is improved, while the channel is connected to the drain region 6. This ensures the operation of the MISFET.
しかしながら、このＬＤＤ構造について本発明者が検討
を加えたところ、オフセｙ）部５の濃度が高くなると耐
圧が低下されることになり、逆に濃度を低くするとオフ
セント部５の抵抗が増大してＭ Ｉ Ｓ Ｆ Ｅ ’ｒ
の相互コンダクタンス（ｇｍ）が低下され、両特性を共
に満足させるためにはオフセット部の濃度の設定が極め
て難かしいものになることが明らか圧なった。However, when the present inventor investigated this LDD structure, it was found that as the concentration of the offset portion 5 increases, the withstand voltage decreases, and conversely, as the concentration decreases, the resistance of the offset portion 5 increases. M I S F E 'r
It has become clear that the mutual conductance (gm) of the offset portion is reduced, and that it becomes extremely difficult to set the concentration of the offset portion in order to satisfy both characteristics.
一方、ＬＤＤ構造はオフセント部５を設けるためにＭＩ
５ＦＥＴの全長が大きくなり、素子の微細化に不利と
なる。特に、半導体装置（ＬＳＩ等）において耐圧が問
題となる素子数は全体の一部であるのに拘らず全素子を
ＬＤＤ構造にすることは高集積化の障害になり、かつ他
の素子のｇｍ向上の支障となる。このようなことから、
一部の素子のみをＬＤＤ構造とし、他の素子（耐圧に問
題の生じない素子）は通常のＭＩＳ構造にすることも考
えられているが、ソース・ドレイン領域の形成に際して
画素子を別個の工程で形成するのでは工程数を（・たず
らに増大して製造工率が低下する一方、画素子を同時に
形成するのでは不純物濃度が両者間で調整し難く、所望
の特性を得ることが難かしく・。On the other hand, in the LDD structure, in order to provide the offset portion 5,
The total length of the 5FET increases, which is disadvantageous to miniaturization of the element. In particular, in semiconductor devices (such as LSIs), even though the number of elements for which breakdown voltage is a problem is only a small part of the total, making all the elements have an LDD structure becomes an obstacle to high integration, and the gm of other elements It becomes a hindrance to improvement. From such a thing,
It is considered that only some elements have an LDD structure and other elements (elements that do not cause problems with withstand voltage) have a normal MIS structure. On the other hand, forming pixel elements at the same time makes it difficult to adjust the impurity concentration between them, making it difficult to obtain the desired characteristics. That's funny.
本発明の目的はドレイン耐圧を向上する一方で内部抵抗
を低減して相互コンダクタンスの向上を図り、かつＬＤ
Ｄ構造以外のＭ Ｉ Ｓ Ｆ Ｅ Ｔとの製造マツチン
グを可能にしく半導体装置の微細化および高集積化を達
成することのできるＭＩＳ型電界効果トランジスタを提
供することにある。The purpose of the present invention is to improve mutual conductance by reducing internal resistance while improving drain breakdown voltage.
It is an object of the present invention to provide an MIS type field effect transistor that can be manufactured and matched with MISFETs other than the D structure, and can achieve miniaturization and high integration of semiconductor devices.
本発明の前記ならび九そのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and nine other objects and novel features of the present invention are:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、オフセット構造のＭＩＳＦ：ＥＴのオフセッ
ト部に形成する不純物領域を比較的に濃度が高くかつ浅
く形成した層と、低濃度でかつ若干深（形成した層の２
層構造として構成することにより、全体としてＬＤＤ構
造による耐圧の向上を図ると共に比較的に高濃度の層に
より抵抗の低減を図ってｇｍの低下を防止し、かつ両層
の不純物濃度の自由度が増大できることから他の素子と
のマツチングを容易に行なうことができ、実質的に高集
積の半導体装置の製造を可能にするものである。In other words, the impurity region formed in the offset part of MISF:ET with an offset structure is a layer with a relatively high concentration and shallowly formed, and a layer with a low concentration and slightly deeper (two layers of the formed layer).
By configuring it as a layered structure, the LDD structure as a whole improves the breakdown voltage, and the relatively high concentration layer reduces the resistance to prevent a decrease in gm, and the degree of freedom in the impurity concentration of both layers is increased. Since it can be increased in number, it can be easily matched with other elements, making it possible to manufacture substantially highly integrated semiconductor devices.
第２図は本発明のＭＩＳＦＥＴの基本構成図であり、第
３図囚〜ＩｃＩはその製造工程図である。即ち、第３図
人のように、例えばＰ型シリコン基板１０の表面にゲー
ト絶縁膜１１を形成し、その上にメタル又はポリシリコ
ンのゲート電極１２をパターニング形成する。そして、
先ずＰ（りん）をセルフつライン法により低濃度にイオ
ン打込みし、次いでＡｓ（ひ素）を同様な方法により比
較的高い濃度にイオン打込みする。そして、これを活性
化すれば、ＰとＡｓの拡散速度の違いにより同図Ｂ）の
ように若干深い低濃度（Ｎ−）層１３と、浅（て比較的
高濃度（Ｎ）１４０層とからなる２層構造が形成できる
。次いで、全面にＣＶＤ法等によりＳ、 ｉ ０．膜１
５を形成しかつこれをＲＩＥエツチング処理することに
より同図［Ｃ１のようにゲート電極の両側にサイドウオ
ニル１６を形成する。その上で、Ａｓを今度は高濃度に
イオン打込みしかつこれを活性化すること匠より、第２
図に示すようにオフセット構造の高濃度（Ｎ＋）のソー
ス・ドレイン領域１７を形成でき、先のオフセット領域
の２層１３．１４とでＬＤＤ構造を構成する。因みに、
低濃度層１３のＰのドーズ量は５×１０〜Ｉ Ｘ ｌ
Ｏ”７ｃｍ”、比較的高濃度層１４のＡｓのドーズ量は
５×１０″〜２×１０Ｉｓ／ＣｒｒＩＩＣｒｒｆ＆。FIG. 2 is a basic configuration diagram of the MISFET of the present invention, and FIG. 3 is a diagram of its manufacturing process. That is, as shown in FIG. 3, a gate insulating film 11 is formed on the surface of, for example, a P-type silicon substrate 10, and a gate electrode 12 of metal or polysilicon is patterned thereon. and,
First, P (phosphorus) is ion-implanted to a low concentration by a self-line method, and then As (arsenic) is ion-implanted to a relatively high concentration by a similar method. If this is activated, due to the difference in the diffusion rate of P and As, a slightly deeper low concentration (N-) layer 13 and a shallower (relatively high concentration (N) 140 layer) are formed as shown in Figure B. A two-layer structure consisting of S, i0.
By forming a gate electrode 5 and subjecting it to RIE etching, side walls 16 are formed on both sides of the gate electrode as shown in C1 in the same figure. On top of that, Takumi instructed us to ion implant As at a high concentration and activate it.
As shown in the figure, a high concentration (N+) source/drain region 17 having an offset structure can be formed, and an LDD structure is formed with the two layers 13 and 14 of the offset region. By the way,
The dose of P in the low concentration layer 13 is 5×10 to I×l
O"7 cm", and the As dose amount of the relatively high concentration layer 14 is 5 x 10" to 2 x 10 Is/CrrIICrrf&.
ソース・ドレイン領域１７のＡｓのドーズ量は１Ｘｌ
０”７ｃｍとしている。また、各層１３゜１４および領
域１７の深さく第２図Ｄｔ 、Ｄ、。The dose of As in the source/drain region 17 is 1Xl
The depth of each layer 13° 14 and region 17 is 0"7cm.
Ｄａ）は夫々０．１ μｍ 、 ０．１５〜０．２ μ
ｍ、０．３ μｍ程度である。Da) is 0.1 μm and 0.15 to 0.2 μm, respectively.
m, approximately 0.3 μm.
したがって、この基本構成のＬＤＤ構造のＭＩＳＦＥＴ
によれば、ゲート電極１２Ｉ／ｃ対してソース−ドレイ
ン領域１７はオフセットされており、かつそのオフセン
ト領域の基板下側に向けて低濃度層１３が形成されてい
るので、ゲート、ドレイン間の電界の緩和を図り耐圧の
向上が達成できる。Therefore, the MISFET of LDD structure with this basic configuration
According to the above, the source-drain region 17 is offset with respect to the gate electrode 12I/c, and the low concentration layer 13 is formed toward the lower side of the substrate in the offset region, so that the electric field between the gate and the drain is reduced. It is possible to improve the withstand voltage by reducing the
一方、オフセット領域の基板表面側には比較的圧高い濃
度層１４が形成されているのでこの領域における抵抗の
増大を抑止し、相互コンダクタンス（ｇｍ）の低下を防
止することができる。これにより、相反する耐圧とｇｍ
の問題を一挙て解消することができる。On the other hand, since the relatively high concentration layer 14 is formed on the substrate surface side of the offset region, it is possible to suppress an increase in resistance in this region and prevent a decrease in mutual conductance (gm). As a result, conflicting pressure resistance and gm
problems can be solved all at once.
第４図および第５図は本発明をＥＰ−ＲＯＭに適用した
実施例であり、例えばＥＰＲＯＭのメモリセル２１にＸ
又はＹ選択用の低耐圧ＭＯ８ＦＥＴ２２．２２・・・と
高耐圧ＭＯ８ＦＥＴ２３を接続した回路構成とし、これ
を同一プロセスで製造する例である。即ち、メモリセル
２１としてフローティングゲート型ＭＯ８構造を、低耐
圧用２２には一般的なＭＯ８構造を、高耐圧用２３には
ＬＤＤ構造を夫々採用し、特に数の多いメモリセル２１
や低耐圧ＭＯ８ＦＥＴ２２の微細化による高集積化を図
っている。4 and 5 show embodiments in which the present invention is applied to an EP-ROM. For example, the memory cell 21 of the EPROM is
Alternatively, this is an example in which a circuit configuration in which low voltage MO8FETs 22, 22, . . . for Y selection and high voltage MO8FETs 23 are connected is manufactured in the same process. That is, a floating gate MO8 structure is adopted as the memory cell 21, a general MO8 structure is adopted as the low breakdown voltage 22, and an LDD structure is adopted as the high breakdown voltage 23.
High integration is being achieved by miniaturizing the MO8FET 22 and the low breakdown voltage MO8FET 22.
先ず、第５装置のようにメモリセル２１、低耐圧ＭＯ８
ＦＥＴ２２．高耐圧ＭＯ８ＦＥＴ２３いずれもＰ型シリ
コン基板２４上にゲート絶縁膜２５を形成し、その上に
ポリシリコン膜をパターニングしてゲート電極２６．２
７と７０−ティングゲート２８を形成する。表面を酸化
してＳｉＯｘ膜２９を形成後、セルファライン法により
ＰとＡｓを続いてイオン打込みする。Ｐのドーズ量は５
Ｘ１０ ７ｃｍ”、Ａｓのドーズ量は５ Ｘ １０”〜
Ｉ Ｘ １０” ／ ｃｍ”である。次にこれを活性化
して低濃度層３１と比較的高濃度層３２を形成した後に
、同図［Ｆ］）のように全面にポリシリコン膜を形成し
かつパターニングすることによりメモリセル２１の７０
−ティングゲート２８上にのみコントロールゲート３０
を形成する。そして、表面酸化後に同図ｔｃＩのように
７オトレジスト膜をパターニングして高耐圧ＭＯ８ＦＥ
Ｔ２３のゲート電極２６のドレイン側の部分にのるフォ
トレジストマスク３３を形成し、しかる上で全面にＡｓ
を高濃度にイオン打込みする。Ａｓのドーズ量は１×１
０” ／ ｃｒｎ’である。そして、これを活性化すれ
ば、同図ＣＤＩのように、夫々ソース・ドレイン領域３
４．３５．３６が形成できる。この場合、高耐圧ＭＯ８
ＦＥＴ２３のドレイン領域３４ａとゲート電極２６とは
オフセントされ、オフセット領域に形成された低濃度層
３１と比較的高濃度層３２とで２層のＬＤＤ構造とされ
ている。また、メモリセル２１と低耐圧ＭＯ８ＦＥＴ２
２のソース・ドレイン領域３６．３５は前述の比較的高
濃度層３２を吸収した非オフセント構造であるが、Ｐと
Ａｓの拡散の相違により夫々２層、Ａｓ層３１゜３６と
３１．３５の２層構造とされる。このため、必要なチャ
ネル長Ｌｅｆｆを得るため九は△Ｌ（２層の長さ）だけ
ゲート長Ｌｇを太きくしなければならないが、Ｐのドー
ズ量を例えば前述のように設定すれば△Ｌを最小限に抑
えた状態で高耐圧ＭＯ８ＦＥＴ２３に必要なソース・ド
レイン領域（特にドレイン領域３４ａとオフセント領域
の各層３１．３２）の不純物濃度を得ることができ、全
てのＭＯＳＦＥＴのマツチングをとることができる。First, like the fifth device, the memory cell 21, low breakdown voltage MO8
FET22. In both high-voltage MO8FETs 23, a gate insulating film 25 is formed on a P-type silicon substrate 24, and a polysilicon film is patterned on it to form a gate electrode 26.2.
7 and 70-ting gates 28 are formed. After the surface is oxidized to form the SiOx film 29, P and As ions are successively implanted by the self-line method. The dose of P is 5
x10 7cm", As dose is 5 x 10"~
I x 10"/cm". Next, after activating this and forming a low concentration layer 31 and a relatively high concentration layer 32, a polysilicon film is formed on the entire surface and patterned as shown in FIG.
- control gate 30 only on the controlling gate 28;
form. After the surface oxidation, the 7 photoresist film is patterned as shown in the figure tcI to form a high voltage MO8FE.
A photoresist mask 33 is formed on the drain side portion of the gate electrode 26 of T23, and then As is applied to the entire surface.
ion implantation to a high concentration. The dose of As is 1×1
0''/crn'.If this is activated, the source and drain regions 3 are activated, as shown in CDI in the same figure.
4.35.36 can be formed. In this case, high voltage MO8
The drain region 34a of the FET 23 and the gate electrode 26 are offset, and a two-layer LDD structure is formed with a low concentration layer 31 and a relatively high concentration layer 32 formed in the offset region. In addition, the memory cell 21 and the low voltage MO8FET2
The source/drain regions 36.35 of No. 2 have a non-offcent structure absorbing the relatively high concentration layer 32 described above, but due to the difference in diffusion of P and As, two layers, As layers 31.degree. 36 and 31.35, respectively. It has a two-layer structure. Therefore, in order to obtain the necessary channel length Leff, the gate length Lg must be increased by △L (the length of the second layer), but if the P dose is set as described above, △L can be increased. It is possible to obtain the impurity concentration of the source/drain region (especially the drain region 34a and each layer 31, 32 of the offset region) necessary for the high voltage MO8FET 23 while minimizing it, and it is possible to match all MOSFETs. .
本実施例によれば、メモリセル２１．低耐圧ＭＯ８ＦＥ
Ｔ２２ 、高耐圧ＭＯ８ＦＥＴ２３を夫々同一の不純物
イオン打込み、拡散工程で形成でき、しかも高耐圧ＭＯ
８ＦＥＴ２３はオフセット領域を２層構造のＬＤＤ構造
とする一方、メモリセル２１、低耐圧ＭＯ８２２におい
ては非オフセント構造で各素子の長さを必要最小限の長
さに形成でき、かつ全ての素子において所要の不純物濃
度を確保することができる。勿論、高耐圧ＭＯ８ＦＥＴ
２３にあっては、前例と同様に耐圧の向上を図る一方で
相互コンダクタンスの低下を防止することができるので
ある。According to this embodiment, memory cell 21. Low voltage MO8FE
T22 and high voltage MO8FET23 can be formed by the same impurity ion implantation and diffusion process, and high voltage MO8FET23 can be formed by the same impurity ion implantation and diffusion process.
The 8FET 23 has an offset region with a two-layer LDD structure, while the memory cell 21 and low voltage MO 822 have a non-offset structure, which allows each element to be formed to the minimum required length, and all elements have the required length. It is possible to ensure an impurity concentration of . Of course, high voltage MO8FET
In the case of No. 23, it is possible to improve the withstand voltage and prevent a decrease in mutual conductance, as in the previous example.
（１）オフセント構造のＭＩＳＦＥＴのオフセット領域
を比較的に深い低濃度層と、浅くかつ比較的に高濃度の
層とで２層構造に構成しているので、低濃度層の作用に
よって耐圧の向上を図る一方で、比較的高濃度層の作用
によって低抵抗化を図り相互コンダクタンスの低下を防
止でき、相反する問題を一挙に解決することができる。(1) The offset region of the MISFET with an offset structure has a two-layer structure consisting of a relatively deep low-concentration layer and a shallow relatively high-concentration layer, so the breakdown voltage is improved by the effect of the low-concentration layer. On the other hand, the relatively high concentration layer can lower the resistance and prevent a decrease in mutual conductance, thereby solving the contradictory problems at once.
＋２１ オフセット領域を２層構造としているので、不
純物濃度、特に低濃度層の濃度に自由度が生じ、通常の
ＭＩＳＦＥＴとのマツチングがとれて同一工程での製造
が可能となり、製造効率の向上が達成できる。+21 Since the offset region has a two-layer structure, there is a degree of freedom in the impurity concentration, especially the concentration in the low concentration layer, and it can be matched with normal MISFETs and can be manufactured in the same process, achieving improved manufacturing efficiency. can.
（３１オフセット構造と非オフセット構造の各ＭＯ８Ｆ
ＥＴを同一工程でかつ良好なマツチングで形成できるの
で、耐圧を必要としないＭＯＳＦＥＴを全て非オフセッ
ト構造にして素子の微細化を図り、高集積化を達成でき
る。(Each MO8F of 31 offset structure and non-offset structure
Since the ETs can be formed in the same process and with good matching, all MOSFETs that do not require breakdown voltage can have a non-offset structure, allowing for miniaturization of elements and achieving high integration.
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。たとえば、不純物のド
ーズ量や各層の深さ寸法等は要求される特性に応じて適
宜変更できる。Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the dose of impurities, the depth of each layer, etc. can be changed as appropriate depending on the required characteristics.
また、オフセット構造の製造プロセスも従来利用されて
いる方法をそのまま利用することができる。Furthermore, the manufacturing process for the offset structure can be performed using conventional methods as is.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるＥＦＲＯＭに適用し
た場合について説明したが、それに限定されるものでは
なく、高耐圧ＭＩ ５ＦＥＴと低耐圧ＭＩＳＦＥＴが存
在して（・る半導体装置の全てに適用することができる
。The above explanation has mainly been about the case where the invention made by the present inventor is applied to EFROM, which is the field of application that formed the background of the invention, but it is not limited to this, and there are high voltage MI 5FETs and low voltage MISFETs. It can be applied to all semiconductor devices.
第１図はＬＤＤ構造を説明する断面図、第２図は本発明
の基本構造の断面図、
第３図囚〜ｔｅｌはその製造方法を示す断面工程図、第
４図は一実施例の回路の一部を示す図、第５図囚〜ＩＤ
Ｉはその製造工程および完成状態を示すための断面工程
図である。
１０・・・シリコン基板、１１・・ゲート絶縁膜、１２
・・・ゲート電極、１３・・低濃度層、１４・・比較的
高濃度層、１６・・サイドウオール、１７・・ソース・
ドレインｆｌＬ２１・・・メモリセル（ＦＡＭＯ８）、
２２・・・低耐圧ＭＯ８ＦＥＴ、２３・・・高耐圧ＭＯ
３ＦＥＴ、２４・・・Ｐ型シリコン基板、２５・・・ゲ
ート絶縁膜、２６．２７・・・ゲート電極、２８・・・
フローティングゲート、２９・・・Ｓｉｎ、膜、３０・
・コントロールゲート、３１・・・低濃度層、３２・・
・比較的高濃度層、３３・・フォトレジスト膜、３４゜
３５．３６・・ソース・ドレイン領域、３４ａ・・・ド
代坤へ 升岬士 尚 橘 門 大
箱 １ 図
？
第 ２ 図
２Fig. 1 is a sectional view explaining the LDD structure, Fig. 2 is a sectional view of the basic structure of the present invention, Fig. 3 is a sectional process diagram showing its manufacturing method, and Fig. 4 is a circuit of one embodiment. Diagram showing a part of Figure 5 Prisoner ~ ID
I is a sectional process diagram showing the manufacturing process and completed state. 10... Silicon substrate, 11... Gate insulating film, 12
...Gate electrode, 13..Low concentration layer, 14..Relatively high concentration layer, 16..Side wall, 17..Source.
Drain flL21...memory cell (FAMO8),
22...Low voltage MO8FET, 23...High voltage MO
3FET, 24... P-type silicon substrate, 25... Gate insulating film, 26.27... Gate electrode, 28...
floating gate, 29...Sin, film, 30.
・Control gate, 31...Low concentration layer, 32...
・Relatively high concentration layer, 33... Photoresist film, 34° 35. 36... Source/drain region, 34a... To Shirokon Masu Misaki Nao Tachibana Mon Large box 1 Figure? Figure 2 2
Claims (1)
少なくともいずれか一方の領域をオフセット配置すると
共に、オフセット領域を比較的深い低濃度層と、浅（か
つ比較的高濃度の層とで２層構造に構成したことを特徴
とするＭＩＳ型電界効果トランジスタ。 ２ ドレイン領域のみをオフセットに構成し、このオフ
セント領域を２層構造にしてなる特許請求の範囲第１項
記載のＭＩＳ型電界効果トランジスタ。 ８ りん等の拡散速度の大きい不純物を低濃度層として
用い、これよりも拡散速度の小さなひ素等の不純物を比
較的に高濃度な層およびソース・ドレイン傾城圧用いて
なる特許請求の範囲第１項又は第２項記載のＭＩＳ型電
界効果トランジスタ。[Claims] 1. At least one of the source and drain regions is offset from the gate electrode, and the offset region is formed by forming a relatively deep low concentration layer and a shallow (and relatively high concentration layer). 2. The MIS type field effect transistor according to claim 1, wherein only the drain region is configured in an offset manner, and this offset region has a two-layer structure. 8. A patent in which an impurity with a high diffusion rate, such as phosphorus, is used as a low concentration layer, and an impurity with a low diffusion rate, such as arsenic, is used in a relatively high concentration layer and source/drain slope pressure. MIS type field effect transistor according to claim 1 or 2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59089415A JPS60234367A (en) | 1984-05-07 | 1984-05-07 | Mis-type field effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59089415A JPS60234367A (en) | 1984-05-07 | 1984-05-07 | Mis-type field effect transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60234367A true JPS60234367A (en) | 1985-11-21 |
| JPH0564458B2 JPH0564458B2 (en) | 1993-09-14 |
Family
ID=13970015
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59089415A Granted JPS60234367A (en) | 1984-05-07 | 1984-05-07 | Mis-type field effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60234367A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0195607A2 (en) * | 1985-03-20 | 1986-09-24 | Fujitsu Limited | Semiconductor device |
| JPS62134974A (en) * | 1985-12-04 | 1987-06-18 | アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド | Field effect device |
| JPS634668A (en) * | 1986-06-25 | 1988-01-09 | Toshiba Corp | Mos type semiconductor device |
| US5424234A (en) * | 1991-06-13 | 1995-06-13 | Goldstar Electron Co., Ltd. | Method of making oxide semiconductor field effect transistor |
| WO1997036331A1 (en) * | 1996-03-25 | 1997-10-02 | Advanced Micro Devices, Inc. | REDUCING REVERSE SHORT-CHANNEL EFFECT WITH LIGHT DOSE OF P WITH HIGH DOSE OF As IN N-CHANNEL LDD |
| WO2003105235A1 (en) * | 2002-06-10 | 2003-12-18 | 日本電気株式会社 | Semiconductor device including insulated-gate field-effect transistor and its manufacturing method |
-
1984
- 1984-05-07 JP JP59089415A patent/JPS60234367A/en active Granted
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0195607A2 (en) * | 1985-03-20 | 1986-09-24 | Fujitsu Limited | Semiconductor device |
| US4928163A (en) * | 1985-03-20 | 1990-05-22 | Fujitsu Limited | Semiconductor device |
| JPS62134974A (en) * | 1985-12-04 | 1987-06-18 | アドバンスト・マイクロ・デイバイシズ・インコ−ポレ−テツド | Field effect device |
| JPS634668A (en) * | 1986-06-25 | 1988-01-09 | Toshiba Corp | Mos type semiconductor device |
| JPH084112B2 (en) * | 1986-06-25 | 1996-01-17 | 株式会社東芝 | MOS semiconductor device |
| US5424234A (en) * | 1991-06-13 | 1995-06-13 | Goldstar Electron Co., Ltd. | Method of making oxide semiconductor field effect transistor |
| WO1997036331A1 (en) * | 1996-03-25 | 1997-10-02 | Advanced Micro Devices, Inc. | REDUCING REVERSE SHORT-CHANNEL EFFECT WITH LIGHT DOSE OF P WITH HIGH DOSE OF As IN N-CHANNEL LDD |
| US5920104A (en) * | 1996-03-25 | 1999-07-06 | Advanced Micro Devices, Inc. | Reducing reverse short-channel effect with light dose of P with high dose of as in n-channel LDD |
| WO2003105235A1 (en) * | 2002-06-10 | 2003-12-18 | 日本電気株式会社 | Semiconductor device including insulated-gate field-effect transistor and its manufacturing method |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0564458B2 (en) | 1993-09-14 |
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