JPS62262462A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62262462A JPS62262462A JP10469086A JP10469086A JPS62262462A JP S62262462 A JPS62262462 A JP S62262462A JP 10469086 A JP10469086 A JP 10469086A JP 10469086 A JP10469086 A JP 10469086A JP S62262462 A JPS62262462 A JP S62262462A
- Authority
- JP
- Japan
- Prior art keywords
- region
- insulating film
- under
- gate electrode
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 20
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000012535 impurity Substances 0.000 claims abstract description 6
- 230000002265 prevention Effects 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 230000003647 oxidation Effects 0.000 abstract description 4
- 238000007254 oxidation reaction Methods 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 3
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000002513 implantation Methods 0.000 abstract description 2
- 150000002500 ions Chemical class 0.000 abstract description 2
- 238000001947 vapour-phase growth Methods 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 abstract 1
- 238000000059 patterning Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract 1
- 239000010408 film Substances 0.000 description 27
- 230000005855 radiation Effects 0.000 description 15
- 230000000694 effects Effects 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［発明の目的］
（産業上の利用分野）
本発明はＭＯＳ型（絶縁ｆート型）半導体装置に係り、
特に耐放射線性が強化されたＭＯＳ トラン１１；
″射されると、酸化膜中に固定電荷が発生して表面、；
＊、’ｑが生成され゛るので、閾値電圧ｖＴＨが変動（
具立一
体的には、ＮチャネルＮＯ３）ランジスタのｖ、Ｈハ浅
くなり、ＰチャネルＭＯ８）ランジスタのｖＴＨは深く
なる）し、チャネル移動度が劣化する。この閾値変動を
抑制するために、従来はプロセス温度の低温化等により
素子・９ラメータ変動の抑制が図られている。[Detailed description of the invention] [Object of the invention] (Industrial application field) The present invention relates to a MOS type (insulated gate type) semiconductor device,
In particular, the MOS transistor 11 has enhanced radiation resistance. When exposed to radiation, a fixed charge is generated in the oxide film and the surface
*, 'q are generated, so the threshold voltage vTH fluctuates (
Specifically, v and H of the N-channel transistor NO3) become shallower, and vTH of the P-channel MO8 transistor becomes deeper), and the channel mobility deteriorates. In order to suppress this threshold value variation, it has conventionally been attempted to suppress element/9-meter variation by lowering the process temperature or the like.
ところで、放射線による閾値電圧ｖＴＨの変動は酸化膜
厚の２〜３乗に比例することが発表されておｌ） （Ｇ
＠Ｆ’＊Ｄｅｒｂｓｎｗｉｅｋ ｅｔ ａｌ、、ＩＥＥ
Ｅ ＴｒａｎｓｓＮｕｃｌａＳｃｉ、、ＮＳ−２５、Ｎ
Ｏ，６，Ｐ２１５１．１９７５）、厚いフィールド酸化
膜を介して形成される寄生フィールドトランジスタにお
いては上記■ＴＨが著しく低下する。したがって、放射
線照射を受けた場合に上−じる。By the way, it has been announced that the fluctuation of the threshold voltage vTH due to radiation is proportional to the second to third power of the oxide film thickness.
@F'*Derbsnwiek et al,, IEE
E TranssNuclaSci, NS-25, N
In a parasitic field transistor formed through a thick field oxide film, the above-mentioned (1) TH is significantly reduced. Therefore, if you have been exposed to radiation, please apply.
また、０ＮＯ８（相補性絶縁ケ゛−ト型）構造を有する
集積回路においては、放射線の照射を受けると、入出力
回路のみならず内部回路においても放射線照射によシ発
生した電荷をトリガとしてラッチアップ現象が生じると
いう問題がある。In addition, when an integrated circuit with a 0NO8 (complementary insulating gate type) structure is exposed to radiation, not only the input/output circuit but also the internal circuit will latch up due to the charge generated by the radiation exposure. The problem is that a phenomenon occurs.
（発明が解決しようとする問題点） 本発明は、上記したように放射線照射によｙ−Ｉ。(Problem that the invention attempts to solve) In the present invention, as described above, y-I is produced by radiation irradiation.
ＭＯＳトランジスタのゲート電極端部下に存在子゛るか
、ＣＭＯＳトランジスタにおけるラッチアップが発生す
るという問題点を解決すべくなされたもので、放射線照
射によるＮＯ８）ランジスタのソース・ドレイン間リー
ク電流の発生を阻止し得ると共に０ＮＯ８）ランジスタ
におけるラッチアップの阻止および高密度化を実現し得
る絶縁ゲート型半導体装置を提供することを目的とする
＠
［発明の溝成コ
（問題点を解決するための手段）
本発明のＮＯ８型半導体装置は、Ｐ形半導体基板上に形
成されたＮチャネルＮＯ８）ランジスタにおけるゲート
！極端部下の絶Ｒ膜をゲート絶縁膜と同程度の薄い膜厚
で形成し、この薄い膜厚の絶縁膜下の半導体基板領域表
面に基板の不純物濃度よシ低濃度のＰ−領域を形成して
なることを特徴とする。This was developed to solve the problem of latch-up occurring in CMOS transistors due to presence of an element under the end of the gate electrode of MOS transistors, and to prevent the generation of leakage current between the source and drain of NO8) transistors due to radiation irradiation. It is an object of the present invention to provide an insulated gate type semiconductor device that can prevent latch-up in a transistor and realize high density. The NO8 type semiconductor device of the present invention is a gate type transistor in an N channel NO8 type transistor formed on a P type semiconductor substrate. An absolute R film at the lower extreme is formed with a thickness as thin as that of the gate insulating film, and a P- region with a lower impurity concentration than that of the substrate is formed on the surface of the semiconductor substrate region under this thin insulating film. It is characterized by being
、」゛、（作用）
リ ゲート電極端部下の絶縁膜が薄いので、この、門、
い絶縁膜部分では放射線照射による固定電荷の一１′
発生量が少なく、しかも、この薄い絶縁膜の下の基板表
面をＰ−領域としているのでゲート電極端部下に寄生フ
ィールドトランジスタが形成されなぐなｐ 、 ＮＯ８
トランジスタのゲート電極端部下でのソース・ドレイン
間リーク電流が生じなくなシ、耐放射腺性が向上する。,'゛,(effect) Since the insulating film under the end of the gate electrode is thin, this gate,
In the thin insulating film part, the amount of fixed charge generated by radiation irradiation is small, and since the substrate surface under this thin insulating film is a P- region, a parasitic field transistor is not formed under the edge of the gate electrode. p, NO8
No leakage current occurs between the source and drain under the end of the gate electrode of the transistor, and radiation resistance is improved.
（実施例）
以下、図面を参照して本発明の一実施例を詳細に説明す
る。第１図（、）はＣＭＯＳ集積回路におけるＮチャネ
ルＮＯ８）ランジスタを取シ出して示す平面パターンで
あり、そのゲート電ＷＬ４の長手方向における縦断面構
造を第１図（ｂ）に示している。即ち、１はＰ形牛導体
基板（たとえばシリコン基板）、２は上記基板１の表面
に選択酸化法によって形成されたフィールド酸化膜、３
は素子領域となる基板表面にドライ酸化法によって形成
されたゲート絶縁膜（ＳｉＯ２膜）、４は酸化膜上の全
面に気相成荒
・；１
）Ｃ
スフとして不純物イオン（たとえばヒ素イオン）が注入
されて形成されたＮ”ＦＪのソース領域およびト：レイ
ン領域であり、このソース領域５とドレイ１エ
ン領域６との間のチャネル領域は前記ケ゛−ト電極、Ｌ
ｌｌ
３の形成前にＮＯ３）ランジスタ閾値電圧制御のだめに
不純物イオンの注入が行なわれている。そして、図示し
ないが、基板上の全面に層間絶縁膜が堆積されたのちり
７０−処理が行なわれ、コンタクトホールの開孔、アル
ミニラ−配線およびアルミニワム電極の形成が行なわれ
ている。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1(,) is a planar pattern showing an N-channel transistor No. 8 in a CMOS integrated circuit, and FIG. 1(b) shows a vertical cross-sectional structure in the longitudinal direction of the gate electrode WL4. That is, 1 is a P-type conductive substrate (for example, a silicon substrate), 2 is a field oxide film formed on the surface of the substrate 1 by selective oxidation, and 3 is
4 is a gate insulating film (SiO2 film) formed by dry oxidation on the surface of the substrate that will become the element region; 4 is a vapor phase growth film formed on the entire surface of the oxide film; The source region and the drain region of N''FJ are formed by implantation, and the channel region between the source region 5 and the drain region 6 is connected to the gate electrode, L
Before the formation of ll3, impurity ions are implanted to control the threshold voltage of the NO3 transistor. Although not shown, an interlayer insulating film is deposited on the entire surface of the substrate and then subjected to a dust treatment 70 to form contact holes, aluminum wires, and aluminum wires.
さらに、不発明においては、前記ゲート電極３の長手方
向の端部下の絶縁膜３′は前記ゲート酸化膜３と同時に
形成されることによってｒ−）酸化膜３と同程度（通常
は同じ）の薄い膜厚で形成されている。そして、このゲ
ート電極端部下の絶縁膜３”Ｆの基板領域からｒ−）電
極４の長手方向に直交する方向の一定距離範囲における
ソース領域５およびドレイン領域６の外側に接する基板
表面に、基板１と同一導電型であって不純物濃度の低い
ｒ領域７が形成されている。そして、とのＰ−領領７の
外側に接すると共に素子形成領域の周囲をとのコンタク
トがとられている。Further, in the present invention, the insulating film 3' under the longitudinal end of the gate electrode 3 is formed at the same time as the gate oxide film 3, so that the insulating film 3' has the same degree (usually the same) as the r-) oxide film 3. It is formed with a thin film thickness. Then, the substrate surface in contact with the outside of the source region 5 and drain region 6 in a certain distance range in a direction perpendicular to the longitudinal direction of the r-) electrode 4 from the substrate region of the insulating film 3''F under the end of the gate electrode is applied. An r region 7 having the same conductivity type as 1 and having a low impurity concentration is formed.The r region 7 is in contact with the outside of the P- region 7 and is in contact with the periphery of the element formation region.
また、上記実施例では、ソース領域５およびドレイン領
域６の各他端側（チャネル領域とは反対側の端部）をガ
ードパント８から離して設けたが、ガートバンド８に接
して設けるように変形してもよい・
上記実施例のＭＯＳ トランジスタの構造によれば、ゲ
ート電極端部下に薄い？３緑膜３′を介してｒ領域７が
形成されておシ、寄生フィールドトランジスタは形成さ
れないので、放射線照射を受けた場合でもＭＯＳ ）ラ
ンノスタのソース・ドレイン間のリーク電流の発生が抑
制され、正常なトランジスタ動作が得られるようになる
。Further, in the above embodiment, the other ends of the source region 5 and the drain region 6 (ends opposite to the channel region) are provided apart from the guard pant 8, but it is preferable to provide the source region 5 and the drain region 6 in contact with the guard band 8.・According to the structure of the MOS transistor in the above embodiment, there is a thin layer under the end of the gate electrode. 3. Since the r region 7 is formed through the green film 3', no parasitic field transistor is formed, so even when exposed to radiation, the occurrence of leakage current between the source and drain of the MOS (MOS) lannostar is suppressed. Normal transistor operation can now be obtained.
また、上記実施例のＭＯＳトランジスタの構造を、放射
線照射をトリがとしてラッチアップが生じ易い０ＭＯ８
）ランジスタにおけるＰウェル領域に形成されるＮチャ
ネルトランジスタに適用した場合、そのソース領域５を
ガートバンド８と共通に配線しておくことにより、ソー
ス領域（Ｎ＋領領域５と一ルドトランジスタが形成され
ないことと相俟りて総合的に耐放射線性が向上する。し
かも、上記ラッチアップ防止用のガードパント８は前記
ｒ領域７に隣接して形成されているので、高密度化が可
能になり、集積度が高く耐放射線性が強化された０ＭＯ
８構造を実現することができる。In addition, the structure of the MOS transistor in the above embodiment was changed to 0MO8, which is prone to latch-up when exposed to radiation.
) When applied to an N-channel transistor formed in the P-well region of a transistor, by wiring the source region 5 in common with the guard band 8, the source region (N+ region 5 and the pulled transistor are not formed). Together with this, the radiation resistance is improved overall.Furthermore, since the guard pant 8 for preventing latch-up is formed adjacent to the r region 7, it is possible to increase the density. 0MO with high integration and enhanced radiation resistance
8 structures can be realized.
なお、本発明は上記実施例に限られるものではなく、第
２図（ａ） 、 （ｂ） ＃ （ｃ）に示すように変形
実施してもよい。即ち、第２図のＭＯＳ ）ランジスタ
の構造が前述した第１図のＭＯＳ ）ランジスタの構造
に比べて異なるのは、（１）ガートバンド８′ｔ−フィ
ールド酸化膜２の下に形成しないでｒ−ト酸化膜３の端
部に位置する薄い絶縁ＭＸ３’の下の基板表面に形成し
た点、（２）ｒ−ト電極４の一端部とフィールド酸化膜
２との間に間隙を設けている点であり、その他は第１図
中と同一であるので、同一符号を付している。このよう
な構造によっても、前記実施例と同様な効果が得られる
ものであり、この場合にはガートバンド８／をフィール
ド酸化膜２の形成後（たとえば０ＭＯ８、＠造の場合に
はＰチャネルトランジスタのソース、ドレイン用のＰ領
域の形成時と同時）に形成することが可能になる。なお
、本！！Ｉ −ｙｓ ＊ ｗ ：＋ Ｌ ｐｅａ ｍ
Ｉｙ ｘ＋＋ｙ ＋ｆ％ ＋７ Ｗ ａｔ； ｙ
ｒ ｔｖ ＋ ＋イン領域６をＰ領域のガードパント
８１に接して設けるように変形してもよい。It should be noted that the present invention is not limited to the above-mentioned embodiment, and may be modified as shown in FIGS. 2(a), 2(b) and 2(c). That is, the structure of the MOS transistor shown in FIG. 2 is different from the structure of the MOS transistor shown in FIG. - A point formed on the substrate surface under the thin insulation MX3' located at the end of the field oxide film 3; (2) a gap is provided between one end of the field oxide film 2 and the r-field oxide film 2; Since the other parts are the same as in FIG. 1, the same reference numerals are given. Even with such a structure, the same effect as in the embodiment described above can be obtained. This makes it possible to form the P regions for the source and drain at the same time as the P regions for the source and drain. In addition, a book! ! I −ys * w :+ L pea m
Iy x++y +f% +7 W at; y
The r tv + +in region 6 may be modified so as to be provided in contact with the guard pant 81 of the P region.
〜、−また、本発明はＭＯＳ型集積回路に限らず、少数
＋７−１
７−１９ｌトランジスタを同一半導体基板上に荷する上
述したように本発明のＭＯＳ型半導体装置によれば、放
射線照射を受けてもＭＯＳ ）ランゾスタのゲート端部
下におけるソース・ドレイン間リーク電流の発生を阻止
することができ、０ＭＯ３構造のトランジスタにあって
は放射線照射をトリガとするラッチアップの阻止および
一高密度化を実現できるという効果が得られる。~, - Furthermore, the present invention is not limited to MOS type integrated circuits, but the MOS type semiconductor device of the present invention in which a small number of +7-1 to 7-19l transistors are mounted on the same semiconductor substrate as described above can prevent radiation irradiation. It can prevent the occurrence of leakage current between the source and drain under the gate end of the Lanzostar (MOS), and can prevent latch-up triggered by radiation irradiation and increase density in transistors with 0MO3 structure. The effect is that it can be realized.
第１図（、）は本発明のＭＯＳ型半導体装置の一実施例
の要部を示す平面・９タ一ン図、第１図（ｂ）は同図（
、）のＢ −Ｂ／ｉに沿う断面図、第２図（、）は同じ
く他の実施例の要部を示す平面・ンターン図、第２図（
ｂ） ＃ （（りはそれぞれ同図（、）のＢ −Ｂ’ｉ
”９ｙ、Ｃ−Ｃ’％に沿う断面図である。
１−Ｐ形シリコン基板、２・・・フィールド酸化膜、３
・・・ゲート酸化膜、３′・・・ｒ−）酸化膜端部の薄
い（ａ）
（ｂ）
第１図FIG. 1(,) is a plan view showing the main part of an embodiment of the MOS type semiconductor device of the present invention, and FIG. 1(b) is the same figure ().
, ) is a cross-sectional view taken along B-B/i of FIG.
b) # ((ri is B −B'i in the same figure (,)
"9y, is a cross-sectional view along C-C'%. 1-P type silicon substrate, 2... field oxide film, 3
...Gate oxide film, 3'...r-) Thin edge of oxide film (a) (b) Fig. 1
Claims (5)
トランジスタにおけるゲート電極端部下の絶縁膜をゲー
ト絶縁膜と同程度の薄い膜厚で形成し、この薄い膜厚の
絶縁膜下の半導体基板領域表面に半導体基板の不純物濃
度より低濃度のＰ＾−領域を形成してなることを特徴と
する半導体装置。(1) N-channel MOS formed on a P-type semiconductor substrate
An insulating film under the end of the gate electrode in a transistor is formed to have a thickness as thin as that of the gate insulating film, and a P^- concentration lower than the impurity concentration of the semiconductor substrate is formed on the surface of the semiconductor substrate region under this thin insulating film. A semiconductor device characterized by forming a region.
ンジスタ領域の周囲を囲む配置で前記Ｐ形半導体基板の
表面に上記半導体基板より不純物濃度の濃いＰ＾＋領域
からなるラッチアップ防止用のガードバンドがさらに形
成され、このガードバンドに接地電位が与えられること
を特徴とする前記特許請求の範囲第１項記載の半導体装
置。(2) A latch-up prevention guard consisting of a P^+ region having a higher impurity concentration than the semiconductor substrate on the surface of the P-type semiconductor substrate, which is arranged to be in contact with the outside of the P^- region and to surround the periphery of the MOS transistor region. 2. The semiconductor device according to claim 1, further comprising a band, and a ground potential is applied to the guard band.
部に形成されていることを特徴とする前記特許請求の範
囲第２項記載の半導体装置。(3) The semiconductor device according to claim 2, wherein the P^+ region is formed in a part under the field oxide film.
酸化膜との間に形成されていることを特徴とする前記特
許請求の範囲第２項記載の半導体装 置。(4) The semiconductor device according to claim 2, wherein the P^+ region is formed between the P^- region and a field oxide film.
ウェル領域であり、前記Ｐ＾＋領域は上記Ｐ形ウェル領
域に形成されたＮチャネルＭＯＳトランジスタのソース
領域と共通に接地電位が与えられることを特徴とする前
記特許請求の範囲第２項記載の半導体装置。(5) The P-type semiconductor substrate is a P-type well region in a CMOS structure, and the P^+ region is given a common ground potential with the source region of the N-channel MOS transistor formed in the P-type well region. The semiconductor device according to claim 2, characterized in that:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10469086A JPS62262462A (en) | 1986-05-09 | 1986-05-09 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10469086A JPS62262462A (en) | 1986-05-09 | 1986-05-09 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62262462A true JPS62262462A (en) | 1987-11-14 |
Family
ID=14387466
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10469086A Pending JPS62262462A (en) | 1986-05-09 | 1986-05-09 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62262462A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01228174A (en) * | 1988-03-08 | 1989-09-12 | Nec Corp | Semiconductor device |
| US5670816A (en) * | 1989-04-07 | 1997-09-23 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2000040798A (en) * | 1998-05-19 | 2000-02-08 | Nec Corp | Semiconductor device and manufacture thereof |
| US6320245B1 (en) | 1998-05-19 | 2001-11-20 | Nec Corporation | Radiation-hardened semiconductor device |
| US7808056B2 (en) | 2006-10-30 | 2010-10-05 | Nec Electronics Corporation | Semiconductor integrated circuit device |
| JP2011134784A (en) * | 2009-12-22 | 2011-07-07 | Brookman Technology Inc | Insulated gate semiconductor device and insulated gate semiconductor integrated circuit |
-
1986
- 1986-05-09 JP JP10469086A patent/JPS62262462A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01228174A (en) * | 1988-03-08 | 1989-09-12 | Nec Corp | Semiconductor device |
| US5670816A (en) * | 1989-04-07 | 1997-09-23 | Kabushiki Kaisha Toshiba | Semiconductor device |
| JP2000040798A (en) * | 1998-05-19 | 2000-02-08 | Nec Corp | Semiconductor device and manufacture thereof |
| US6320245B1 (en) | 1998-05-19 | 2001-11-20 | Nec Corporation | Radiation-hardened semiconductor device |
| US7808056B2 (en) | 2006-10-30 | 2010-10-05 | Nec Electronics Corporation | Semiconductor integrated circuit device |
| JP2011134784A (en) * | 2009-12-22 | 2011-07-07 | Brookman Technology Inc | Insulated gate semiconductor device and insulated gate semiconductor integrated circuit |
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