JPS60213053A - Semiconductor memory element - Google Patents
Semiconductor memory elementInfo
- Publication number
- JPS60213053A JPS60213053A JP59069048A JP6904884A JPS60213053A JP S60213053 A JPS60213053 A JP S60213053A JP 59069048 A JP59069048 A JP 59069048A JP 6904884 A JP6904884 A JP 6904884A JP S60213053 A JPS60213053 A JP S60213053A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- capacitor
- oxide film
- resist
- diffused
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
- H10B12/038—Making the capacitor or connections thereto the capacitor being in a trench in the substrate
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
【発明の詳細な説明】
（技術分野）
この発明は半導体メモリ素子、詳しくはＭＩＳダイナミ
ックメモリ素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to semiconductor memory devices, and more particularly to MIS dynamic memory devices.
（従来技術）
従来より１トランノスタ１キヤノぐシタ型のＭＯＳダイ
ナミックメモリは高集積化に適している為、広く用いら
れているがＩＭビット級のいわゆる超超ＬＳＩでは最早
、平面的なキヤ・ぞシタでは充分な容量が得られず、実
現が困難な状況にある。そこで立体的にキャノ９シタを
形成し容量を増加させる方法の１つとして半導体基板に
溝を堀って溝側面にもＭＯＳキャノヤシタを形成する提
案がなされている。しかしながら、この方法では、溝形
成の際のエツチングによるダメージや応力によって良質
の酸化膜が得られない欠点があった。(Prior art) MOS dynamic memory with one transistor and one transistor has been widely used because it is suitable for high integration, but in IM bit class so-called super-ultra LSIs, planar capacitors are no longer used. It is difficult to realize this because sufficient capacity cannot be obtained in the city. Therefore, as one method for increasing the capacitance by three-dimensionally forming a canopy, a proposal has been made to dig a groove in a semiconductor substrate and form a MOS canopy on the side surface of the groove. However, this method has the disadvantage that a good quality oxide film cannot be obtained due to damage and stress caused by etching during trench formation.
これを改善するため、日経エレクトロニクス１９８２．
１２．２０ Ｐ ７４〜７５に開示されているように絶
縁層をｓ ｉｏ ２／Ｓ ｔ ！、Ｎ４／ｓ ！０２
という３層構造にしたものがある。しかし、試作結果は
リフレッシュ時間のばらつきが大きく、従来の七ルより
も短いというものでアシ、絶縁層が３層で製造上簡単で
ないという欠点があった。To improve this, Nikkei Electronics 1982.
12.20 P74-75, the insulating layer is sio2/St! , N4/s! 02
There is one that has a three-layer structure. However, the prototype results showed that the refresh time varied widely, was shorter than the conventional 7-layer, and had the drawbacks that it was not easy to manufacture because it had three layers of insulation.
（発明の目的）
この発明の目的は高集積化が可能で、しかも簡単な工程
で製造することができる半導体メモリ素子を実現するこ
とにある。(Objective of the Invention) An object of the present invention is to realize a semiconductor memory element that can be highly integrated and manufactured in a simple process.
（発明の構成）
本発明は第１導電型の半導体基板に設けられた溝の内壁
に２Ｘ１０１９ｃｍ−’以上の濃度の第２導電型の不純
物を拡散した第２導電型層と、この第２導電型層上に設
けられた誘電体層と、この誘電体層上に設けられたノリ
ンリコンとからなるキヤ・ぐシタを有したことを特徴と
する半導体メモリ素子にある。(Structure of the Invention) The present invention includes a second conductivity type layer in which impurities of a second conductivity type with a concentration of 2X1019 cm-' or more are diffused into the inner wall of a groove provided in a semiconductor substrate of a first conductivity type; A semiconductor memory element is characterized in that it has a capacitor made up of a dielectric layer provided on a mold layer and a non-contact layer provided on the dielectric layer.
（実施例）
以下この発明の一実施例を説明するＯ
第１図はこの発明の一実施例を説明する平面図、第２図
は第１図のＸ −Ｘ／線における断面図である。(Embodiment) An embodiment of the present invention will be described below. FIG. 1 is a plan view illustrating an embodiment of the invention, and FIG. 2 is a sectional view taken along the line X-X/ in FIG. 1.
ここで、１はＰ型シリコン単結晶基板、２はチャネルス
トップＰ＋層、３はフィールド酸化膜、４はキヤ・ぐシ
タ用の溝である。溝の内壁は１刈０２０ｄ３の濃度のす
層となっており、キヤ・ぞシタＣ１の一方の電極を形成
し、トランスファケ°−トトランジスタＴ、の一方の拡
散層１０に接続されている。Here, 1 is a P-type silicon single crystal substrate, 2 is a channel stop P+ layer, 3 is a field oxide film, and 4 is a groove for a capacitor. The inner wall of the groove is a layer having a concentration of 020d3, which forms one electrode of the capacitor C1 and is connected to one diffusion layer 10 of the transfer transistor T.
キャパシタＣ１は１層５、誘電体である窒化シリコン膜
６及び接地電極であるぼりシリコン７から形成されてい
る。トランスファケ゛−トトランジスタＴｌのキャノｅ
シタ自と反対側の１層１０はコンタクトホール１２を介
してビット線１３に接続されている。トランスフアク９
−トトランノスタＴ。The capacitor C1 is formed of a single layer 5, a silicon nitride film 6 as a dielectric, and a silicon nitride film 7 as a ground electrode. Canon e of transfer gate transistor Tl
One layer 10 on the side opposite to the top layer 10 is connected to a bit line 13 via a contact hole 12. Transfac 9
-Totrannosta T.
のケ°−ト電極９はアドレス線としても働き、このアド
レス線がハイレベルになるとトランスフアク０−トトラ
ンノスタＴ１が導通し、ビット線ノ３の情報がキャパシ
タＣ＋に書きこまれ、又逆にキヤ・ぐシタＣ１の内容が
ビット線１３に読み出される。The gate electrode 9 also works as an address line, and when this address line becomes high level, the transfer transistor T1 becomes conductive, and the information on the bit line No. 3 is written to the capacitor C+, and vice versa. - The contents of the data register C1 are read out to the bit line 13.
第３図に第２図の電気的等価回路図を示す。第３図にお
けるＣ２は１層５と基板との間に形成されるＰＮ接合容
量である。FIG. 3 shows an electrical equivalent circuit diagram of FIG. 2. C2 in FIG. 3 is a PN junction capacitance formed between the first layer 5 and the substrate.
次に上述したダイナミックメモリ素子の製造方法につい
て説明する。第４図（Ａ） −（Ｅ）は本実施例の製造
工程説明図である。Ｐ型シリコン半導体基板１上に選択
酸化法を用いて、フィールド酸化膜３、及びチャネルス
トップＰ＋層２を形成する。（第４図（４）参照）次に
溝４を形成する為、レノスト５ノをノやターニングシ、
このレノストノやターンをマスクにしてＣＢ ｒ Ｆ
ｓガスを用いた反応性イオンエツチング装置によシ異方
性エツチングを行い深さ２μｍの溝４を形成する（第４
図（Ｂ）参照）。レノス） ５１を除去後、熱酸化によ
り３００乃至５００Ｘの酸化膜５２をシリコン基板表面
に成長させ、Ｎ型不純物を拡散させる領域の酸化膜５２
を取り除き、ＰＯＣｌ２を拡散源として酸化膜５２の開
孔部よシリン（Ｐ）を拡散させて１層５を形成する。こ
の時温度は８５０℃、キャリアガスはＮ２と０２で、リ
ンの基板表面濃度は１×１Ｏ２０ｃＩＩＬ−６とする。Next, a method of manufacturing the above-mentioned dynamic memory element will be explained. FIGS. 4A to 4E are explanatory diagrams of the manufacturing process of this embodiment. A field oxide film 3 and a channel stop P+ layer 2 are formed on a P-type silicon semiconductor substrate 1 using a selective oxidation method. (See Figure 4 (4)) Next, in order to form the groove 4, cut the renost 5 and turn the grooves.
CB r F using this lens and turn as a mask
Anisotropic etching is performed using a reactive ion etching device using s gas to form grooves 4 with a depth of 2 μm (fourth
(See figure (B)). After removing the oxide film 51 (Renos) 51, a 300 to 500X oxide film 52 is grown on the silicon substrate surface by thermal oxidation, and the oxide film 52 is grown in the region where N-type impurities are to be diffused.
is removed, and syringe (P) is diffused through the openings of the oxide film 52 using POCl2 as a diffusion source to form one layer 5. At this time, the temperature is 850° C., the carrier gas is N2 and 02, and the substrate surface concentration of phosphorus is 1×1 O20cIIL-6.
リン拡散時にシリコン表面につく図示しない薄い酸化膜
を取り除くと第４図（Ｃ）のような形状となる。次にキ
ャパシタの誘電体となる窒化シリコン膜６を減圧ＣＶＤ
法（化学的気相成長法）により２００乃至５００Ｘの膜
厚で全面に堆積させる。If a thin oxide film (not shown) that is formed on the silicon surface during phosphorus diffusion is removed, a shape as shown in FIG. 4(C) is obtained. Next, the silicon nitride film 6, which will become the dielectric of the capacitor, is deposited by low pressure CVD.
(chemical vapor deposition method) to a film thickness of 200 to 500× over the entire surface.
窒化シリコン膜のリーク電流を減少させる為、８５０乃
至９５０°Ｃウェット酸素雰囲気で窒化シリコン膜上に
図示しない２０乃至４０Ｘの酸化膜をつける。続いてキ
ヤ・ぐシタの接地電極となるリン（Ｐ）あるいはヒ素（
Ａ８）を高濃度にドープした７１？リシリコン７を減圧
ＣＶＤ法により全面に堆積させる。この時、溝４が完全
に埋まるように膜厚を設定し、全面を異方性エツチング
し、溝４以外の部分で必要な膜厚となるようにする。こ
の後図示しないレジストをパクーニングし、このレノス
トパターンをマスクにして、ＣＦ４及び０２ガスを用い
たドライエツチング装置でＩリシリコン７をエツチング
し、窒化シリコン膜６上の図示しない酸化膜を緩衝フッ
酸溶液でエツチングし、更にト°ライエツチング装置で
窒化シリコン膜６をエツチングする。図示しないレジス
ト及びＮ型不純物拡散時にマスクに使用した酸化膜５２
を除去すると第４図（至）の形状となる。以上の工程で
キヤ・ＰシタＣ１が形成されて、続いてトランスファダ
ートＴ１を形成する。熱酸化により、３００乃至５００
Ｘのケゝ−ト酸化膜８を成長させ、その上にトランスフ
ァｒ−）電極及びアドレス線となるモリブデン７リサイ
ド（ＭＯ３＋２） ９をス・ぐツタ法により３００Ｘ被
着させ、″図示しないレノストをノやターニングしこの
レジストノやターンをマスクにして、ＣＦ４及び０２ガ
スを用いたドライエツチング装置でエツチングする。図
示しないレジストパターンを除去後、Ｉリシリコン７及
びシリサイド９をマスクにしてＡ８を５ＸｌＯｔｏｎｓ
、そｉのドーズ量でイオン注入してｒ層ノ０を形成する
。（第４図（Ｆ：）参照）絶縁膜１ノとしてＰＳＧ （
リンシリカガラス）をＣＶＤ法によりＭ厚８０００Ｘ堆
積させ、コンタクトホールノ２を必要な場所に開孔し、
アルミをスノぞツタ法によシ膜厚１００００Ｘつけツク
ターニングを行いビット線１３とする。最後に保護膜１
４としてＰＳＧをつけメモリ素子形成を完了する。（第
２図参照）以上説明した本実施例ではＰ型シリコン基板
を用いたＮチャネルプロセスであったがＮ型基板あるい
は絶縁基板中に設けられたＰウェル中にメモリセルを形
成する事や不純物及び電源の陰性を適当に反転させるこ
とによりＰチャネルプロセスでも可能である。また、１
層５として本実施例では濃度を１×１０２０ｃｍ−３と
したが、２ Ｘ １０”ｃｍ−３以上の高濃度ならばよ
い。In order to reduce the leakage current of the silicon nitride film, a 20 to 40X oxide film (not shown) is formed on the silicon nitride film in a wet oxygen atmosphere at 850 to 950°C. Next, phosphorus (P) or arsenic (
71 which is highly doped with A8)? Silicon 7 is deposited over the entire surface by low pressure CVD. At this time, the film thickness is set so that the groove 4 is completely filled, and the entire surface is anisotropically etched so that the required film thickness is obtained in the portions other than the groove 4. Thereafter, a resist (not shown) is patterned, and using this renost pattern as a mask, the I-resilicon 7 is etched using a dry etching device using CF4 and 02 gases, and the oxide film (not shown) on the silicon nitride film 6 is etched with buffered hydrofluoric acid. Etching is performed using a solution, and the silicon nitride film 6 is further etched using a etching device. Oxide film 52 used as a mask during resist and N-type impurity diffusion (not shown)
When is removed, the shape shown in FIG. 4 (to) is obtained. Through the above steps, the carrier/Pitter C1 is formed, and then the transfer dart T1 is formed. 300 to 500 by thermal oxidation
A gate oxide film 8 of Using the resist holes and turns as a mask, etching is performed using a dry etching device using CF4 and 02 gas.After removing the resist pattern (not shown), using I silicon 7 and silicide 9 as masks, A8 is etched with 5XlOtons.
, the ion implantation is performed at a dose of i to form the r layer No0. (See Figure 4 (F:)) PSG (
phosphorous silica glass) was deposited to a thickness of 8000× by the CVD method, and contact holes No. 2 were opened at the required locations.
A film of 10,000× of aluminum was applied using the snow vine method and then turned to form the bit line 13. Finally, protective film 1
At step 4, PSG is attached to complete the memory element formation. (See Figure 2) Although this embodiment described above was an N-channel process using a P-type silicon substrate, it was not possible to form a memory cell in a P-well provided in an N-type substrate or an insulating substrate, or to use impurities. Also possible is a P-channel process by suitably reversing the negative power supply. Also, 1
In this embodiment, the concentration of the layer 5 is 1 x 1020 cm-3, but it may be as high as 2 x 10'' cm-3 or higher.
さらに、誘電体としては窒化シリコン膜以外にＳ ＋
０２やＳ ｉ Ｏ２と窒化シリコン膜の複合膜等を使用
することも可能である。又、アドレス線としては抵抗が
低ければポリシリコンやポリサイド構造、更に低抵抗が
必要な場合にはタングステン等の高融点金属を用いても
よい。Furthermore, as a dielectric material, S +
It is also possible to use a composite film of 02 or S i O2 and a silicon nitride film. Further, as the address line, a polysilicon or polycide structure may be used if the resistance is low, and a high melting point metal such as tungsten may be used if an even lower resistance is required.
（発明の効果）
この発明では２ Ｘ １０”Ｃ！ＩＬ””以上の濃度に
ドープされたＮ＋叶層を基板に堀られた溝の内壁に形成
して、キャパシタの一方の電極とし、接地電極としてポ
リシリコンを使用している為、次のような利点がある。(Effects of the Invention) In this invention, an N+ layer doped to a concentration of 2 x 10"C!IL"" or higher is formed on the inner wall of a groove dug in the substrate, and serves as one electrode of the capacitor, and as a ground electrode. Since polysilicon is used as the material, it has the following advantages.
キヤ・ぐシタの一方の電極は高濃度にドープされたシリ
コン基板であるため、半導体は縮退した状態にあり、導
体的性質を示す。この為キヤ・ｅシタはＭＩＳ構造でな
く誘電体を２つの導体ではさんだ構造と考えられ、ダイ
ナミックメモリのキヤ・９シタとしてＭＩＳキャパシタ
を用いる場合、特に考慮しなくてはならない半導体、絶
縁体界面の準位等は問題とならず、従って界面準位の少
ないシリコン−８ｉ Ｏ２の紹み合せ以外に窒化シリコ
ン等の高誘電体の使用が容易に可能となる利点がある。One electrode of the capacitor is a heavily doped silicon substrate, so the semiconductor is in a degenerate state and exhibits conductive properties. For this reason, a capacitor/e-capacitor is considered to have a structure in which a dielectric material is sandwiched between two conductors, rather than an MIS structure, and when using a MIS capacitor as a capacitor in a dynamic memory, special consideration must be given to the interface between the semiconductor and the insulator. The level of , etc. is not a problem, and therefore, there is an advantage that a high dielectric material such as silicon nitride can be easily used in addition to the introduction of silicon-8i O2, which has few interface states.
第１図は本発明の一実施例を説明する平面図、第２図は
第１図のｘ −ｘ’線における断面図、第３図は第２図
の電気的等価回路図、第４図囚〜（匂は本発明の一実施
例の製造工程説明図である。
・ぐシタ用の溝、５・・・１層、６・・・窒化シリコン
膜、２・・・ぼりシリコン、８・・・ケ°−ト酸化膜、
９・・・ケ゛−ト電極、）０・・・１層、１ノ・・絶縁
膜、１２・・コンタクトホール、１３・・・ビット線、
１４・・・保護膜、輸・・・キャパシタ、Ｃ２・・容量
、Ｔｌ・・・トランスファグートトランノスタ。
特許出願人 沖電気工業株式会社
第３図
Ｃ８
第４図
第４図FIG. 1 is a plan view illustrating an embodiment of the present invention, FIG. 2 is a sectional view taken along line x-x' in FIG. 1, FIG. 3 is an electrical equivalent circuit diagram of FIG. 2, and FIG. 4 (The odor is an explanatory diagram of the manufacturing process of an embodiment of the present invention. Groove for groove, 5... 1 layer, 6... silicon nitride film, 2... silicon nitride, 8...・・Keto oxide film,
9...Kate electrode, )0...1 layer, 1...Insulating film, 12...Contact hole, 13...Bit line,
14...Protective film, transfer...capacitor, C2...capacitance, Tl...transfergate trannostar. Patent applicant Oki Electric Industry Co., Ltd. Figure 3 C8 Figure 4 Figure 4
Claims (1)
０ ｃｍ 以上の濃度の第２導電型の不純物を拡散した
第２導電型層と、 この第２導電型層上に設けられた誘電体層と、この誘電
体層上に設けられたポリシリコンとからなるキャｉｅシ
タを有したことを特徴とする半導体メモリ素子。[Claims] The inner wall of the groove provided in the semiconductor substrate of the first conductivity type is
A second conductivity type layer having a second conductivity type impurity diffused at a concentration of 0 cm or more, a dielectric layer provided on the second conductivity type layer, and a polysilicon layer provided on the dielectric layer. What is claimed is: 1. A semiconductor memory device characterized by having a capacitor consisting of a capacitor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59069048A JPS60213053A (en) | 1984-04-09 | 1984-04-09 | Semiconductor memory element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59069048A JPS60213053A (en) | 1984-04-09 | 1984-04-09 | Semiconductor memory element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60213053A true JPS60213053A (en) | 1985-10-25 |
Family
ID=13391300
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59069048A Pending JPS60213053A (en) | 1984-04-09 | 1984-04-09 | Semiconductor memory element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60213053A (en) |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE33261E (en) * | 1984-07-03 | 1990-07-10 | Texas Instruments, Incorporated | Trench capacitor for high density dynamic RAM |
| US4958206A (en) * | 1988-06-28 | 1990-09-18 | Texas Instruments Incorporated | Diffused bit line trench capacitor dram cell |
| US4978634A (en) * | 1989-07-25 | 1990-12-18 | Texas Instruments, Incorporated | Method of making trench DRAM cell with stacked capacitor and buried lateral contact |
| US5013676A (en) * | 1987-04-27 | 1991-05-07 | Nec Corporation | Structure of MIS-type field effect transistor and process of fabrication thereof |
| US5017506A (en) * | 1989-07-25 | 1991-05-21 | Texas Instruments Incorporated | Method for fabricating a trench DRAM |
| US5057887A (en) * | 1989-05-14 | 1991-10-15 | Texas Instruments Incorporated | High density dynamic ram cell |
| US5066609A (en) * | 1988-07-25 | 1991-11-19 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device including a trench capacitor |
| US5089868A (en) * | 1989-05-22 | 1992-02-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with improved groove capacitor |
| US5102817A (en) * | 1985-03-21 | 1992-04-07 | Texas Instruments Incorporated | Vertical DRAM cell and method |
| US5105245A (en) * | 1988-06-28 | 1992-04-14 | Texas Instruments Incorporated | Trench capacitor DRAM cell with diffused bit lines adjacent to a trench |
| US5109259A (en) * | 1987-09-22 | 1992-04-28 | Texas Instruments Incorporated | Multiple DRAM cells in a trench |
| US5111259A (en) * | 1989-07-25 | 1992-05-05 | Texas Instruments Incorporated | Trench capacitor memory cell with curved capacitors |
| US5208657A (en) * | 1984-08-31 | 1993-05-04 | Texas Instruments Incorporated | DRAM Cell with trench capacitor and vertical channel in substrate |
| US5225363A (en) * | 1988-06-28 | 1993-07-06 | Texas Instruments Incorporated | Trench capacitor DRAM cell and method of manufacture |
| US5545290A (en) * | 1987-07-09 | 1996-08-13 | Texas Instruments Incorporated | Etching method |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58137245A (en) * | 1982-02-10 | 1983-08-15 | Hitachi Ltd | Semiconductor memory and its manufacture |
-
1984
- 1984-04-09 JP JP59069048A patent/JPS60213053A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58137245A (en) * | 1982-02-10 | 1983-08-15 | Hitachi Ltd | Semiconductor memory and its manufacture |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE33261E (en) * | 1984-07-03 | 1990-07-10 | Texas Instruments, Incorporated | Trench capacitor for high density dynamic RAM |
| US5208657A (en) * | 1984-08-31 | 1993-05-04 | Texas Instruments Incorporated | DRAM Cell with trench capacitor and vertical channel in substrate |
| US5102817A (en) * | 1985-03-21 | 1992-04-07 | Texas Instruments Incorporated | Vertical DRAM cell and method |
| US5013676A (en) * | 1987-04-27 | 1991-05-07 | Nec Corporation | Structure of MIS-type field effect transistor and process of fabrication thereof |
| US5545290A (en) * | 1987-07-09 | 1996-08-13 | Texas Instruments Incorporated | Etching method |
| US5109259A (en) * | 1987-09-22 | 1992-04-28 | Texas Instruments Incorporated | Multiple DRAM cells in a trench |
| US5105245A (en) * | 1988-06-28 | 1992-04-14 | Texas Instruments Incorporated | Trench capacitor DRAM cell with diffused bit lines adjacent to a trench |
| US5225363A (en) * | 1988-06-28 | 1993-07-06 | Texas Instruments Incorporated | Trench capacitor DRAM cell and method of manufacture |
| US4958206A (en) * | 1988-06-28 | 1990-09-18 | Texas Instruments Incorporated | Diffused bit line trench capacitor dram cell |
| US5066609A (en) * | 1988-07-25 | 1991-11-19 | Kabushiki Kaisha Toshiba | Method of manufacturing a semiconductor device including a trench capacitor |
| US5057887A (en) * | 1989-05-14 | 1991-10-15 | Texas Instruments Incorporated | High density dynamic ram cell |
| US5089868A (en) * | 1989-05-22 | 1992-02-18 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device with improved groove capacitor |
| US5017506A (en) * | 1989-07-25 | 1991-05-21 | Texas Instruments Incorporated | Method for fabricating a trench DRAM |
| US5111259A (en) * | 1989-07-25 | 1992-05-05 | Texas Instruments Incorporated | Trench capacitor memory cell with curved capacitors |
| US4978634A (en) * | 1989-07-25 | 1990-12-18 | Texas Instruments, Incorporated | Method of making trench DRAM cell with stacked capacitor and buried lateral contact |
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