JPS60208843A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60208843A JPS60208843A JP6519284A JP6519284A JPS60208843A JP S60208843 A JPS60208843 A JP S60208843A JP 6519284 A JP6519284 A JP 6519284A JP 6519284 A JP6519284 A JP 6519284A JP S60208843 A JPS60208843 A JP S60208843A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- silicon
- silicon semiconductor
- shaped groove
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
発明の技術分野
本発明は半導体装置の製造方法、特にシリコン半導体基
板への素子分離形成方法に係る。DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming element isolation on a silicon semiconductor substrate.
従来技術と問題点
半導体集積回路では複数菓子の間を絶縁する必要があ夛
、従来、ＰＮ接合による分離、選択酸化膜による分離、
Ｕ字溝や７字溝による分離などが利用されている。選択
酸化法は絶縁が完全で、耐圧が高く、工程も簡単である
ことから広く利用されている。しかし、酸化膜の成長が
等方向であるために酸化膜の必要な厚さに比例して横方
向にも酸化が進行し、かつバーズビークも大きいので、
集積度増加に難点がある。その点、溝埋込みによる分離
、特にＵ字溝形の分離では、絶縁性、耐圧性に優れ、か
つ溝の幅も溝の深さとは一応独立に狭くすることが可能
である。Conventional technology and problems In semiconductor integrated circuits, it is often necessary to insulate between multiple confections. Conventionally, isolation using a PN junction, isolation using a selective oxide film,
Separation using U-shaped grooves or 7-shaped grooves is used. The selective oxidation method is widely used because of its complete insulation, high breakdown voltage, and simple process. However, since the oxide film grows in the same direction, oxidation progresses laterally in proportion to the required thickness of the oxide film, and the bird's beak is also large.
There are difficulties in increasing the degree of integration. In this respect, isolation by trench embedding, particularly U-shaped isolation, has excellent insulation and voltage resistance, and the width of the trench can be narrowed independently of the depth of the trench.
しかし、Ｕ字溝形分離においてもなお酸化によるバーズ
ビークが存在し、それ以上集積度が上がらないという問
題がある。すなわち、シリコン基層にＵ字溝を形成し、
溝表面を酸化してから溝内を多結晶シリコンで埋めるが
、溝を埋めた多結晶シリコンの頂部は再び酸化する必要
があるので、この表面酸化の際、酸化膜が素子形成領域
上までのびて所謂、バーズビークを形成する。However, even in the U-shaped trench isolation, bird's beaks due to oxidation still exist, and there is a problem that the degree of integration cannot be increased any further. That is, a U-shaped groove is formed in the silicon base layer,
After oxidizing the trench surface, the inside of the trench is filled with polycrystalline silicon, but the top of the polycrystalline silicon that filled the trench needs to be oxidized again, so during this surface oxidation, the oxide film does not extend to the top of the element formation area. This forms a so-called bird's beak.
また、Ｕ字溝を選択エピタキシャル法で埋める素子分離
方法も提案されているが、同様に、最後に表面を酸化す
るのでバーズビークが発生する。Furthermore, an element isolation method has been proposed in which the U-shaped groove is filled by a selective epitaxial method, but similarly, bird's beaks occur because the surface is oxidized at the end.
発明の目的
本発明の目的は、以上の如き従来技術に鑑み、素子分離
におけるバーズビークの発生を抑えて、素子分離の幅を
小さくシ、集積回路の集積度増加に寄与することにある
。OBJECTS OF THE INVENTION In view of the above-mentioned prior art, an object of the present invention is to suppress the occurrence of bird's beak in element isolation, reduce the width of element isolation, and contribute to an increase in the degree of integration of integrated circuits.
発明の構成
上記目的を達成するために、本発明では、選択エピタキ
シャル成長法でＵ字溝を埋める前に、シリコン半導体基
層の素子形成領域およびＵ字溝の側壁に窒化シリコン膜
を予め形成しておく。こうすることによって、選択エピ
タキシャル成長法で溝内を埋めた後、表面を酸化しても
、窒化膜が存在するために酸化膜の成長がそこで停止す
る。その結果、バーズビークの発生は防止される。Structure of the Invention In order to achieve the above object, in the present invention, before filling the U-shaped groove by selective epitaxial growth, a silicon nitride film is formed in advance on the element formation region of the silicon semiconductor base layer and on the side walls of the U-shaped groove. . By doing so, even if the surface is oxidized after filling the trench by selective epitaxial growth, the growth of the oxide film will stop there because of the presence of the nitride film. As a result, the occurrence of bird's beak is prevented.
また、本発明では、エピタキシャル成長が起きるべきで
ない領域を（すべて）窒化シリコン膜で覆う形になるの
で、酸化シリコンを使用する場合よシも、選択エピタキ
シャル成長が優れている。Further, in the present invention, since (all) regions where epitaxial growth should not occur are covered with a silicon nitride film, selective epitaxial growth is superior even when silicon oxide is used.
発明の実施例
図面を参照して説明する。第１図を参照すると、ｐ−形
シリコン基板１にイオン打ち込みしてｎ＋＋込層２を形
成し、ｎ″′形エピタキシャル層３を成長して、シリコ
ン半導体本体を形成する。素子分離用のＵ字溝を形成す
るために、エピタキシャル層３の表面に５ｉｎ２膜４お
よびＳ ｉ ｓｌ’Ｊ４膜５を形成し、それをパターニ
ングする。この、バターニングしたＳｉ３Ｎ、膜５をマ
スクとしてシリコン半導体本体を異方性エツチングする
。このエツチングによって幅２〜３μｍ１深さ４〜５μ
ｍ のＵ字溝６を形成する。このＵ字溝６はｎ＋形埋込
層２よシ深く形成する。Embodiments of the invention will be described with reference to the drawings. Referring to FIG. 1, ions are implanted into a p-type silicon substrate 1 to form an n++ doped layer 2, and an n''' type epitaxial layer 3 is grown to form a silicon semiconductor body. In order to form a groove, a 5in2 film 4 and a SiSl'J4 film 5 are formed on the surface of the epitaxial layer 3, and patterned.The silicon semiconductor body is formed using the patterned Si3N film 5 as a mask. Anisotropic etching is performed.This etching results in a width of 2 to 3 μm and a depth of 4 to 5 μm.
A U-shaped groove 6 of m is formed. This U-shaped groove 6 is formed deeper than the n+ type buried layer 2.
第２図を参照すると、先に形成した５ｔ３Ｎ４膜５およ
び５ｉ０２膜４を除去し、再び全面にＳｉＯ□膜７およ
びＳｉ３Ｎ、膜８を減圧ＣＶＤ法によってそれぞれ厚さ
０．３μｍおよび０．２μｍ程度形成する。このＳｉＯ
２膜７およびＳｉ３Ｎ４膜８は素子形成領域即ちｎ−形
エピタキシャル層３の表面のみならず、Ｕ字溝の内壁（
特に側壁）にも形成することが必須である。Referring to FIG. 2, the previously formed 5t3N4 film 5 and 5i02 film 4 are removed, and a SiO□ film 7, a Si3N film 8, and a film 8 are formed on the entire surface again by low pressure CVD to a thickness of about 0.3 μm and 0.2 μm, respectively. Form. This SiO
The Si3N4 film 7 and the Si3N4 film 8 cover not only the surface of the element formation region, that is, the n-type epitaxial layer 3, but also the inner wall of the U-shaped groove (
In particular, it is essential to form it also on the side walls.
第３図を参照すると、Ｕ字溝６の底の部分の５ｔ３Ｎ、
膜８および５ｉｎ２膜７を異方性コントロールエツチン
グによって選択的に除去し、シリコン基板１を露出させ
る。続いて、Ｕ字溝の底のシリコン基板１に例えばヒ素
イオンを打ち込んでｐ＋形領領域チャンネルストッパ）
９を形成する。Referring to FIG. 3, 5t3N at the bottom of the U-shaped groove 6,
Film 8 and 5in2 film 7 are selectively removed by anisotropic controlled etching to expose silicon substrate 1. Next, for example, arsenic ions are implanted into the silicon substrate 1 at the bottom of the U-shaped groove to form a p+ type region (channel stopper).
form 9.
第４図を参照すると、Ｕ字溝の底に露出したシリコン基
板１とＵ字溝の底以外の表面を覆うＳｉ３Ｎ４膜８の表
面状態の相違を利用し、反応ガス、圧力、温度等をコン
トロールして、露出シリコン表面だけの選択的なエピタ
キシャル成長を行なう。選択エピタキシャル成長自体は
既に慣用されている技術である。この選択エピタキシャ
ル成長法を利用すれば、シリコンはＵ字溝内だけに堆積
（成長）し、Ｓｉ３Ｎ、膜上には一切堆積（付着）しな
い。従って、従来の多結晶シリコンの埋め込み法の場合
のように、Ｕ字溝内の埋込み後素子形成領域上に堆積し
た多結晶シリコンを除去する工程は必要でない。更に、
Ｕ字溝内に埋込まれたものも、選択エピタキシャル成長
法によれば均一なものが得られ、多結晶シリコンの充填
の場合のように不均一ではない。Ｕ字溝内の選択成長（
ノンドープまたはｐ−形）シリコン１０は溝を全部埋め
る少し前で停止して、次の工程で表面酸化による体積膨
張分を見込んでおく。Referring to FIG. 4, the reaction gas, pressure, temperature, etc. are controlled by utilizing the difference in surface condition between the silicon substrate 1 exposed at the bottom of the U-shaped groove and the Si3N4 film 8 covering the surface other than the bottom of the U-shaped groove. Then, selective epitaxial growth is performed only on the exposed silicon surface. Selective epitaxial growth itself is already a commonly used technique. If this selective epitaxial growth method is used, silicon will be deposited (grown) only within the U-shaped groove, and will not be deposited (adhered) at all on the Si3N film. Therefore, unlike the conventional polycrystalline silicon burying method, there is no need for a step of removing the polycrystalline silicon deposited on the element formation region after burying in the U-shaped trench. Furthermore,
The material filled in the U-shaped groove can also be uniform by selective epitaxial growth, and is not non-uniform as in the case of filling with polycrystalline silicon. Selective growth within the U-shaped groove (
The silicon 10 (non-doped or p-type) is stopped just before the trench is completely filled to allow for volume expansion due to surface oxidation in the next step.
第５図を参照すると、Ｕ字溝内に選択成長したシリコン
１０の表面を酸化して厚さ０、ｌ−ｐｍ程度の５ｉｏ２
膜１１を形成する。このとき、Ｕ字溝内のシリコン１０
と素子形成領域３のシリコンの間にはＳｉ３Ｎ４膜８が
、存在するので、Ｕ字溝内のシリコン１０の酸化は縦方
向にだけ逆打し、横方向には進行しない。すなわち、バ
ーズビークは発生しない。Referring to FIG. 5, the surface of the silicon 10 selectively grown in the U-shaped groove is oxidized to form a 5io2 layer with a thickness of about 0, l-pm.
A film 11 is formed. At this time, silicon 10 inside the U-shaped groove
Since the Si3N4 film 8 exists between the wafer and the silicon in the element forming region 3, the oxidation of the silicon 10 in the U-shaped groove reverses only in the vertical direction and does not proceed in the horizontal direction. In other words, bird's beak does not occur.
従来、Ｕ字溝に多結晶シリコンを埋め込んで表面を酸化
した場合、片側幅０．３μｍ程度のバーズビークが発生
していたので、本発明によシ両側で０．６μｍ程度の寸
法縮少が達成されている。Conventionally, when polycrystalline silicon was buried in a U-shaped groove and the surface was oxidized, a bird's beak with a width of about 0.3 μm on one side was generated, so the present invention achieves a size reduction of about 0.6 μm on both sides. has been done.
発明の効果
以上の説明から明らかな通勺、本発明によれば、集積回
路の素子分離の幅を低減することかできるので、集積度
増加に寄与する。Effects of the Invention The general rule that is clear from the above explanation is that according to the present invention, the width of element isolation of an integrated circuit can be reduced, thereby contributing to an increase in the degree of integration.
第１図〜第５図は本発明の詳細な説明するための半導体
装置の工程順断面図である。
１・・・シリコン基板、３・・・エピタキシャル層、６
・・・Ｕ字溝、７・・・ＳｉＯ□膜、８・・・Ｓｉ３Ｎ
、膜、９・・・チャンネルストッパ、１０・・・選択成
長エピタキシャルシリコン、１１・・・表面酸化膜。
特許出願人
富士通株式会社
特許出願代理人
弁理士 青 木 朗
弁理士 西舘和之
弁理士 内田幸男
弁理士 山 口 昭 之1 to 5 are cross-sectional views of a semiconductor device in order of steps for explaining the present invention in detail. 1... Silicon substrate, 3... Epitaxial layer, 6
...U-shaped groove, 7...SiO□ film, 8...Si3N
, film, 9... Channel stopper, 10... Selectively grown epitaxial silicon, 11... Surface oxide film. Patent applicant Fujitsu Limited Patent agent Akira Aoki Patent attorney Kazuyuki Nishidate Patent attorney Yukio Uchida Akira Yamaguchi
Claims (1)
ン半導体基層の素子形成領域および該Ｕ字溝内の表面を
窒化シリコン膜で散り工程、該窒化シリコン膜の該Ｕ字
溝の底の部分を選択的に除去して前記シリコン半導体基
層を露出させる工程、該Ｕ字溝内にシリコン半導体を選
択的にエピタキシャル成長して該Ｕ字溝を埋める工程、
そして該Ｕ字溝内の該シリコン半導体の表面を酸化する
工程を含むことを特徴とする半導体装置の製造方法。a step of forming a U-shaped groove in a silicon semiconductor base layer, a step of scattering a silicon nitride film over the element formation region of the silicon semiconductor base layer and the surface inside the U-shaped groove, and a step of covering the bottom portion of the U-shaped groove in the silicon nitride film. selectively removing to expose the silicon semiconductor base layer; selectively epitaxially growing silicon semiconductor within the U-shaped groove to fill the U-shaped groove;
A method for manufacturing a semiconductor device, comprising the step of oxidizing the surface of the silicon semiconductor within the U-shaped groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6519284A JPS60208843A (en) | 1984-04-03 | 1984-04-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6519284A JPS60208843A (en) | 1984-04-03 | 1984-04-03 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60208843A true JPS60208843A (en) | 1985-10-21 |
Family
ID=13279806
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6519284A Pending JPS60208843A (en) | 1984-04-03 | 1984-04-03 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60208843A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020053560A (en) * | 2000-12-27 | 2002-07-05 | 박종섭 | Method for forming a separation film of a semi-conductor device |
| KR20030000966A (en) * | 2001-06-27 | 2003-01-06 | 주식회사 하이닉스반도체 | Method for manufacturing an isolation layer of semiconductor device |
| KR20030000134A (en) * | 2001-06-22 | 2003-01-06 | 주식회사 하이닉스반도체 | Forming method for field oxide of semiconductor device |
| KR100383758B1 (en) * | 2000-12-29 | 2003-05-14 | 주식회사 하이닉스반도체 | Method of forming an isolation layer in a semiconductor device |
| KR20040038119A (en) * | 2002-10-31 | 2004-05-08 | 주식회사 하이닉스반도체 | Method for forming the Isolation Layer of Semiconductor Device |
| JP2004336008A (en) * | 2003-04-16 | 2004-11-25 | Fuji Electric Holdings Co Ltd | Reverse blocking insulated gate type bipolar transistor and its fabrication method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5432984A (en) * | 1977-08-19 | 1979-03-10 | Hitachi Ltd | Integrated circuit device |
| JPS58197838A (en) * | 1982-05-14 | 1983-11-17 | Nec Corp | Manufacture of semiconductor device |
-
1984
- 1984-04-03 JP JP6519284A patent/JPS60208843A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5432984A (en) * | 1977-08-19 | 1979-03-10 | Hitachi Ltd | Integrated circuit device |
| JPS58197838A (en) * | 1982-05-14 | 1983-11-17 | Nec Corp | Manufacture of semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020053560A (en) * | 2000-12-27 | 2002-07-05 | 박종섭 | Method for forming a separation film of a semi-conductor device |
| KR100383758B1 (en) * | 2000-12-29 | 2003-05-14 | 주식회사 하이닉스반도체 | Method of forming an isolation layer in a semiconductor device |
| KR20030000134A (en) * | 2001-06-22 | 2003-01-06 | 주식회사 하이닉스반도체 | Forming method for field oxide of semiconductor device |
| KR20030000966A (en) * | 2001-06-27 | 2003-01-06 | 주식회사 하이닉스반도체 | Method for manufacturing an isolation layer of semiconductor device |
| KR20040038119A (en) * | 2002-10-31 | 2004-05-08 | 주식회사 하이닉스반도체 | Method for forming the Isolation Layer of Semiconductor Device |
| JP2004336008A (en) * | 2003-04-16 | 2004-11-25 | Fuji Electric Holdings Co Ltd | Reverse blocking insulated gate type bipolar transistor and its fabrication method |
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