JPS60198870A - Photosensor element - Google Patents
Photosensor elementInfo
- Publication number
- JPS60198870A JPS60198870A JP59055768A JP5576884A JPS60198870A JP S60198870 A JPS60198870 A JP S60198870A JP 59055768 A JP59055768 A JP 59055768A JP 5576884 A JP5576884 A JP 5576884A JP S60198870 A JPS60198870 A JP S60198870A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- region
- upper electrode
- photoelectric conversion
- conductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 claims abstract description 31
- 230000003287 optical effect Effects 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000004020 conductor Substances 0.000 claims description 32
- 239000004065 semiconductor Substances 0.000 claims 4
- 239000012780 transparent material Substances 0.000 claims 1
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 63
- 238000005530 etching Methods 0.000 description 4
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000002474 experimental method Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- 229910001220 stainless steel Inorganic materials 0.000 description 2
- 239000010935 stainless steel Substances 0.000 description 2
- 229910001887 tin oxide Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 230000004298 light response Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910001120 nichrome Inorganic materials 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000002966 varnish Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/08—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
- H01L31/10—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by potential barriers, e.g. phototransistors
- H01L31/101—Devices sensitive to infrared, visible or ultraviolet radiation
- H01L31/102—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier
- H01L31/105—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type
- H01L31/1055—Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier the potential barrier being of the PIN type the devices comprising amorphous materials of Group IV of the Periodic Table
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Electromagnetism (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Light Receiving Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Facsimile Heads (AREA)
Abstract
Description
【発明の詳細な説明】 （発明の技術分野） この発明は光センサ素子に関する。[Detailed description of the invention] (Technical field of invention) The present invention relates to optical sensor elements.
（従来技術の説明）
従来から、ファクシミリの読取部等に使用される多くの
タイプの光センサ素子が提案されている。その−例を第
１図（Ａ）及び（Ｂ）に示す。(Description of Prior Art) Many types of optical sensor elements have been proposed for use in facsimile reading units and the like. An example thereof is shown in FIGS. 1(A) and 1(B).
第１図（Ａ）は−個の光センサ素子、例えば、光電変換
部としてｐｉｎダイオードを構成する層を具えた素子及
び同図（Ｂ）は複数個のこのような光センサ素子を配列
した状態をそれぞれ示す断面図である。これら図におい
て、ｌは透明基板で、２はガラス等の透明基板部分、３
は基板の一部分として被着形成された透明の導電体層で
下部電極を形成している。４は光電変換部としてのｐｉ
ｎｌｎタイオード〜７は、このｐｉｎダイオードを形成
している、例えば、アモルファスシリコン（ａ−３ｉ）
等を用いて順次に形成されている光導電層で５はｐ型ａ
−Ｓｉ層、６はｉ型（真性）ａ−８ｉ層及び７はｎ５ａ
−９ｉ層である。８はこの光電変換部４のｎｙ！！ｉａ
−５ｉ層７上に設けられた上部電極であり、平面的に
見て、その電極領域は下側の各光導電層５〜７の領域よ
りも内側に引っ込んだ構造となっている。Figure 1 (A) shows - photosensor elements, for example, an element comprising a layer constituting a pin diode as a photoelectric conversion part, and Figure 1 (B) shows a state in which a plurality of such photosensor elements are arranged. FIG. In these figures, l is a transparent substrate, 2 is a transparent substrate portion such as glass, and 3 is a transparent substrate.
The lower electrode is formed by a transparent conductive layer deposited as part of the substrate. 4 is pi as a photoelectric conversion section
nln diode~7 is made of, for example, amorphous silicon (a-3i) forming this pin diode.
5 is a p-type a photoconductive layer formed sequentially using
-Si layer, 6 is i type (intrinsic) a-8i layer and 7 is n5a
-9i layer. 8 is ny! of this photoelectric conversion section 4! ! ia
-5i This is an upper electrode provided on the layer 7, and when viewed in plan, the electrode region is recessed inward from the regions of the lower photoconductive layers 5 to 7.
次に、この従来例の動作につき説明する。Next, the operation of this conventional example will be explained.
今、透明基板ｌ側から光電変換部４であるｐｉｎダイオ
ードに光りが照射されたとする。このダイオード４中に
入射光りの光強度に応じた電子−正孔対が発生し、これ
ら電子、正孔を上部電極８と下部電極３との間で電流と
して取り出すことが出来る。この場合、ｐ１ｎダイオー
ド４は逆バイアスで用いられ、光照射のない場合は、電
極間に電流はほとんど流れないので、これら電極３及び
８間の電流により光りの照射を検出することが出来る。Now, assume that light is irradiated onto the PIN diode, which is the photoelectric conversion unit 4, from the side of the transparent substrate l. Electron-hole pairs are generated in the diode 4 according to the intensity of the incident light, and these electrons and holes can be taken out as a current between the upper electrode 8 and the lower electrode 3. In this case, the p1n diode 4 is used with a reverse bias, and when there is no light irradiation, almost no current flows between the electrodes, so that the light irradiation can be detected by the current between the electrodes 3 and 8.
ところで、第１図（Ａ）に示すように、上部電極８の領
域の周囲の側縁は、平面的に見て、ｐｉｎダイオード４
の各光導電層の側縁よりも内側に距離文だけ後退してい
る。その理由は、これら光導電層５〜７をパターニング
した後、上部電極８のパターニングを行う時、この電極
８と光導電層５〜７との大きさが同じであると、マスク
ずれにより下部電極３に上部電極材料が接して短絡を起
してしまうので、この短絡の発生を回避する必要がある
からであり、また、その場合、マスクずれが生しないと
しても、光導電層５〜７の膜厚は合計して最大でもＩｇ
ｍ程度にすぎず、上部電極８の領域と、これら光導電層
５〜７の領域とが平面的に晃で同一の大きさであると、
これら光導電層の端面付近の欠陥部を通して両電極３及
び８との間の漏れ電流が増大してしまい、光センサ素子
としての特性が極めて悪くなるからである。By the way, as shown in FIG. 1(A), the side edges around the area of the upper electrode 8 are similar to the pin diode 4 when viewed in plan.
is set back a distance inward from the side edges of each photoconductive layer. The reason for this is that when patterning the upper electrode 8 after patterning the photoconductive layers 5 to 7, if the electrode 8 and the photoconductive layers 5 to 7 have the same size, mask misalignment will cause the lower electrode to This is because the upper electrode material comes into contact with the photoconductive layers 5 to 7 and causes a short circuit, so it is necessary to avoid the occurrence of this short circuit. The maximum total film thickness is Ig
m, and if the area of the upper electrode 8 and the areas of these photoconductive layers 5 to 7 are the same size in plan view,
This is because the leakage current between the electrodes 3 and 8 increases through the defective portions near the end faces of the photoconductive layer, resulting in extremely poor characteristics as a photosensor element.
このような理由により、ｐｉｎダイオードの周囲の側縁
と電極８とは距離文だけ離れた構造となっている。しか
し、側縁から文の距離の範囲内のＰｌｎタイオードの領
域は上部電極８と接触していないので、この領域には両
電極３及び８間のバイアス電圧がほとんどかからず、こ
れがため、距離又の範囲の光導電層内で発生した電子や
正孔に対してバイアス電圧が印加されないため、これら
電子や止孔が両電極３及び８に達する時間が極めて長く
、従って、入射光りのオン・オフに対する両電極間電流
の応答速度（光応答）が遅いという欠点があった。For this reason, the side edge around the pin diode and the electrode 8 are separated by a distance. However, since the region of the Pln diode within the distance from the side edge is not in contact with the upper electrode 8, this region receives almost no bias voltage between both electrodes 3 and 8, and this causes the distance Since no bias voltage is applied to the electrons and holes generated within the photoconductive layer in the range shown in FIG. There was a drawback that the response speed (photoresponse) of the current between both electrodes to OFF was slow.
（発明の目的）
この発明の目的は光応答速度の速い光センサ素子を提供
することにある。(Object of the Invention) An object of the present invention is to provide an optical sensor element with a fast optical response speed.
（発明の構成）
この目的の達成を図るため、この発明は、一方の表面側
に下部電極用導電性部分を少なくとも有する基板と、こ
の基板の導電性表面上に形成した光電変換部と、この光
電変換部上に形成した上部電極用導電体層とを具え、平
面的に見て、この上部電極用導電体層の領域がこの光電
変換部の領域内に位置させて成る光センサ素子において
、この光電変換部の、この上部電極用導電体層の領域と
の接触面での領域を、この上部電極用導電体層の領域の
形状と同一形状とし、この光電変換部の、この上部電極
用導電体層の領域との接触面から厚さの少なくとも一部
分にわたる平面的に見た領域をこの光電変換部の残部の
領域よりも狭小としたことを特徴とする。(Structure of the Invention) In order to achieve this object, the present invention provides a substrate having at least a conductive portion for a lower electrode on one surface side, a photoelectric conversion portion formed on the conductive surface of this substrate, and a photoelectric conversion portion formed on the conductive surface of this substrate. An optical sensor element comprising a conductor layer for an upper electrode formed on a photoelectric conversion part, and in which a region of the conductor layer for an upper electrode is located within a region of the photoelectric conversion part when viewed in plan, The region of this photoelectric conversion section at the contact surface with the region of this upper electrode conductor layer is made to have the same shape as the region of this upper electrode conductor layer, and the region of this photoelectric conversion section is The photoelectric converter is characterized in that a region extending from the contact surface with the conductive layer region to at least a portion of the thickness is narrower than the remaining region of the photoelectric conversion section.
（実施例の説明） 以下図面につきこの発明の詳細な説明する。(Explanation of Examples) The invention will now be described in detail with reference to the drawings.
第２図及び第３図はこの発明の実施例をそれぞれ示す略
図的断面図である。尚、これらの図において、断面を表
わすハツチング等について一部分を省略して示している
。FIGS. 2 and 3 are schematic cross-sectional views showing embodiments of the present invention, respectively. Note that in these figures, hatchings and the like representing cross sections are partially omitted.
先ず、第２図の実施例から説明する。First, the embodiment shown in FIG. 2 will be explained.
この実施例では、上述した従来の光センサ素子と同様に
、透明基板１０の透明基板部分１１上にこの基板の一部
分を構成する透明導電体層を形成しこの導電体層を下部
電極１２となし、この下部電極１２の表面上に光電変換
部１３として、ｐ型ａ−３ｉ層１４、ｉ型ａ−Ｓｉ層１
５及びｎ型ａ−８ｉ層１６から成るｐｉｎダイオードを
、形成して設けである。In this embodiment, similarly to the conventional optical sensor element described above, a transparent conductor layer constituting a part of the substrate is formed on the transparent substrate portion 11 of the transparent substrate 10, and this conductor layer is used as the lower electrode 12. , a p-type a-3i layer 14 and an i-type a-Si layer 1 are formed on the surface of this lower electrode 12 as a photoelectric conversion section 13.
A PIN diode consisting of 5 and n-type A-8i layers 16 is formed and provided.
このｎ型ａ−３ｉ層１８上には、平面的に見て光電変換
部１３の領域よりも狭小の領域を有する上側電極用導電
体層Ｉ７を設けているが、この実施例の場合には、光電
変換部１３を構成しているｎ型ａ −Ｓｉ層１６の平面
的に見た領域の形状は、上部電極用導電体層１７の領域
と接触している接触面においてはもとより、上部電極用
導電体層１？との接触面からその厚さ全体にわたる領域
において上部電極用導電体層１７の領域の形状と同一形
状となして、光電変換部１３の残部のｉｙ！１ａ−９ｉ
層１５及びｐ型ａ −９ｉ層１４の各領域よりも狭小と
なした構造となっている。On this n-type a-3i layer 18, an upper electrode conductor layer I7 having an area narrower than the area of the photoelectric conversion section 13 in plan view is provided. The shape of the region of the n-type a-Si layer 16 constituting the photoelectric conversion section 13 when viewed in plan is not only the shape of the region in contact with the region of the upper electrode conductor layer 17 but also the upper electrode conductor layer 1? The remaining iy! of the photoelectric conversion section 13 is made to have the same shape as the region of the upper electrode conductor layer 17 in the region extending from the contact surface to the entire thickness thereof. 1a-9i
It has a structure that is narrower than each region of the layer 15 and the p-type a-9i layer 14.
このような構造を形成するには、一旦、従来と同様にし
て基板部分ｌｌ上に、下部電極用の導電性部分である導
電体層１２、ｐｉｎダイオード１３の各ａ−９ｉ＠１４
〜１Ｂ及びｎ型ａ −３ｉ層１８の領域の内側にこの領
域よりも狭小の領域を有する上部電極用導電体層１７を
形成し、然る後、この実施例では、この導電体層１７を
マスクとして、この導電体層１７の領域外の露出してい
るｎ、ｌａ −５ｉ層！６の領域の部分をエツチングに
より除去する。このエツチング処理を、例えば、ＣＦ４
ガス或いはその他の好適なガスを用いたプラズマエツチ
ングとすると容易に行うことが出来て好適である。In order to form such a structure, the conductor layer 12, which is the conductive part for the lower electrode, and the pin diode 13, each a-9i@14, are first formed on the substrate part ll in the same manner as in the conventional method.
A conductor layer 17 for an upper electrode having a region narrower than this region is formed inside the region of the ~1B and n-type a-3i layers 18, and then, in this example, this conductor layer 17 is As a mask, the exposed n, la -5i layer outside the area of this conductor layer 17! 6 is removed by etching. This etching process is performed using, for example, CF4
Plasma etching using a gas or other suitable gas is preferred because it can be easily performed.
このようなエツチングに際して、上部電極用導電体層１
７自体をマスクとして使用しているので、従来のように
マスクずれ等が生じることがない。During such etching, the upper electrode conductor layer 1
Since the mask 7 itself is used as a mask, there is no possibility of mask displacement as in the conventional case.
また、このエツチングにより、多少は下側のｉ型ａ−５
ｉ層１５までをエツチングしても差支えない。Also, due to this etching, the lower i type a-5
There is no problem even if up to the i-layer 15 is etched.
第３図はこの発明の他の実施例を示す８２図と同様な実
施例であり、第２図の構成成分と同様な構成成分につい
ては同一の符合を付して示す。この実施例の場合には、
基板１８の一部分１８をガラスとかアルミナとかで形成
し１表面側の下部電極用導電性部分２０を、例えば、ニ
クロム、クロム、モリブデン、ステンレス、アルミニウ
ム及びその他の金属のうちのいずれか一種又は二種以上
の金属から成る導電体層とする。一方、上部電極用導電
体層２１を透明導電体層とし、これを、例えば、酸化イ
ンジウムと酸化スズ（Ｓｎ０２ ）との混合物から成っ
ている、いわゆるＩＴＯと称されている導電性材ネ」及
び酸化スズ（Ｓｎ０２ ）の導電性材料の一方から成る
単独層又は両方の導電材料の各層から成る二層にして形
成することが出来る。FIG. 3 shows an embodiment similar to FIG. 82 showing another embodiment of the present invention, and components similar to those in FIG. 2 are denoted by the same reference numerals. In this example,
A portion 18 of the substrate 18 is formed of glass or alumina, and the conductive portion 20 for the lower electrode on the surface side is made of, for example, one or two of nichrome, chromium, molybdenum, stainless steel, aluminum, and other metals. The conductive layer is made of the above metal. On the other hand, the conductive layer 21 for the upper electrode is a transparent conductive layer, which is made of a conductive material called ITO, which is made of a mixture of indium oxide and tin oxide (Sn02), for example. It can be formed as a single layer of one of the conductive materials, tin oxide (Sn02), or as a double layer of each layer of both conductive materials.
或いは又、図示せずも、この二層（１９及び２０）構造
の基板を用いる代わりに、基板全体をステンレスとかア
ルミニウムとか或いはその他好適な導電性材料で形成し
ても良い。Alternatively, although not shown, instead of using this two-layer (19 and 20) structure substrate, the entire substrate may be made of stainless steel, aluminum, or other suitable conductive material.
上述した各実施例では、上部電極１７または２１と接触
しているｎまたはＰ型ａ−９ｉ層１６を平面的に見た時
の領域の形状をその厚さ全体にわたり上部電極の形状と
同一となしているか、このａ −５ｉ層１Ｂの平面的に
見た領域の形状が、光等の放射の照射によって発生した
電子及び正孔に対してバイアス電圧が有効に作用出来る
ように、上部電極との接触面から基板側に向って連続的
に又は段階的に大きくなしていく構造であってもよい。In each of the embodiments described above, the shape of the region of the n- or p-type a-9i layer 16 in contact with the upper electrode 17 or 21 when viewed in plan is the same as the shape of the upper electrode throughout its thickness. The shape of the region of the a-5i layer 1B in plan view is such that the bias voltage can effectively act on the electrons and holes generated by the irradiation of radiation such as light. The structure may be such that the size increases continuously or stepwise from the contact surface toward the substrate.
さらに、上述した各実施例において、ｐｉｎタイオード
１３を構成するｐ型及びｎ型ａ−Ｓｉ層１４及び１６の
導電型を反転させた構造としても良い。Furthermore, in each of the embodiments described above, the conductivity types of the p-type and n-type a-Si layers 14 and 16 constituting the pin diode 13 may be reversed.
さらに、上述した実施例では、光電変換部としてｐｉｎ
ダイオードにつき説明したが、これに限定されないこと
勿論であり、外部からの放射を受けて電子−正孔対を形
成する別の光電変換層で形成しても良い。その場合、電
子及び正孔がバイアス電圧の作用を受けて急速に電流と
して取り出せるようにするため、光電変換層の、上部電
極用導電体層の領域との接触面での領域を、上部電極用
導電体層の領域の形状と同一形状とすると共に。Furthermore, in the embodiment described above, a pin is used as a photoelectric conversion section.
Although the diode has been described, it is needless to say that the diode is not limited thereto, and may be formed of another photoelectric conversion layer that forms electron-hole pairs upon receiving radiation from the outside. In that case, in order to allow electrons and holes to be rapidly taken out as current under the action of a bias voltage, the area of the photoelectric conversion layer at the contact surface with the area of the conductor layer for the upper electrode is The shape is the same as the shape of the region of the conductor layer.
光電変換層の、上部電極用導電体層の領域との接触面か
ら厚さの少なくとも一部分にわたる平面的に見た領域を
光電変換層の基板側の残部の領域よりも狭小とする。A region of the photoelectric conversion layer extending from the contact surface with the region of the conductor layer for the upper electrode and at least part of the thickness is made narrower than the remaining region of the photoelectric conversion layer on the substrate side.
さらに、上述したこの発明の光センサ素子の大気に露出
している部分に酸化シリコン、窒化シリコン、ワニス等
の表面保護膜を被着することが出来る。Furthermore, a surface protective film of silicon oxide, silicon nitride, varnish, etc. can be applied to the portion of the above-described optical sensor element of the present invention that is exposed to the atmosphere.
尚、上述した光センサ素子は単体で使用することはもと
より、複数個配列させて用いても良い。Note that the above-mentioned optical sensor elements may be used not only singly but also in a plurality of arrays.
次に、上述した実施例の光センサ素子と従来の光センサ
素子とにつき、光応答時間の比較実験を行ったところ、
次表１に示すような結果が得られた。この実験は、光源
として波長ｆｉ５０ ｒ＋＋ｗの発光ダイオード（ＬＥ
Ｄ）を用い、１０ｍ５ｅｃ（７）オン及び１０ｍ５ｅｃ
のオフで発光させた繰り返しパルス食用いて行った。一
方、使用したセンサ素子のｐｉｎダイオードの形状は、
直径３１１Ｉｎの円形でかつ文＝ ０．２５ｍｒａであ
った。Next, an experiment was conducted to compare the optical response times of the optical sensor element of the above-mentioned example and the conventional optical sensor element.
The results shown in Table 1 below were obtained. In this experiment, a light emitting diode (LE) with wavelength fi50 r++w was used as a light source.
D), 10m5ec (7) on and 10m5ec
This was done using repeated pulsed food that was turned on and off. On the other hand, the shape of the pin diode of the sensor element used is
It was circular with a diameter of 311 inches and a length of 0.25 mra.
表Ｉ
この表Ｉからも明らかなように、この発明の光センサ素
子の光応答速度は、バイアス電圧Ｏｖでは従来の１／４
、また、バイアス電圧−３ｖでは従来の１／２０となっ
ていることが分かる。Table I As is clear from Table I, the optical response speed of the optical sensor element of the present invention is 1/4 that of the conventional one at bias voltage Ov.
, and it can be seen that at a bias voltage of -3V, it is 1/20 of the conventional one.
（発明の効果）
上述した説明からも明らかなように、この発明の光セン
サ素子の構造によれば、上部電極の下側の光電変換部の
部分のうち、平面的に見てこの上部電極と接触していな
い領域であってかつバイアス電圧が印加されない部分を
除去した構造となっているので、光によって発生した電
子及び正孔の全てが印加バイアス電圧によって効果的に
上部及び下部電極に流れて電流となり、これがため、従
来に比べて光応答速度が極めて速くなるという利点があ
る。(Effects of the Invention) As is clear from the above description, according to the structure of the optical sensor element of the present invention, of the portion of the photoelectric conversion section below the upper electrode, the upper electrode and Since the structure is such that the areas that are not in contact and where no bias voltage is applied are removed, all electrons and holes generated by light can effectively flow to the upper and lower electrodes by the applied bias voltage. This has the advantage that the light response speed is extremely fast compared to the conventional method.
従って、この発明の光センサ素子はその光応答速度が著
しく速いので、高速度ファクシミリの読取部に適用して
頗る好適である。Therefore, since the optical sensor element of the present invention has an extremely fast optical response speed, it is particularly suitable for application to the reading section of a high-speed facsimile.
第１図（Ａ）及び（Ｂ）は従来の光センサ素子の説明に
供する断面図、
第２図及び第３図はこの発明の光センサ素子の実施例を
説明するための略図的断面図である。
１Ｏ１１８・・・基板、 １１・・・透明基板部分１２
・・・（透明な）下部電極用導電体層１３・・・光電変
換部（例えば、ｐｉｎダイオード）１４・・・（第一導
電型の）ａ−９ｉ層１５・・・（真性型）ａ−９ｉ層
１６・・・（第二導電型の）ａ−９ｉ層１７．２１・・
・上部電極用導電体層
１８・・・基板の一部分
２０・・・下部電極用導電体層。
第１図
１１１１
第２図
ム
第３図
ム
手続補正書
昭和６０年１月１０日
特許庁長官 志賀 学 殿
光センサ素子
３補正をする者
事件との関係 特許出願人
住所（〒−１０５）
東京都港区虎ノ門１丁目７番１２号
名称（０２８）沖電気工業株式会社
代表者 橋本 南海男
４代理人 〒１７０ ｔｘ （８８Ｂ）５５８３住所
東京都豊島区東池袋１丁目２０番地５池袋ホワイトハウ
スビル８０５号
明細書の発明の詳細な説明の欄
７補正の内容
（１）、明細書の第１２頁第８行の「光応答速度は」を
「光応答時間はＪと訂正する。FIGS. 1(A) and (B) are cross-sectional views for explaining a conventional optical sensor element, and FIGS. 2 and 3 are schematic cross-sectional views for explaining an embodiment of the optical sensor element of the present invention. be. 1O118...Substrate, 11...Transparent substrate portion 12
... (transparent) lower electrode conductor layer 13 ... photoelectric conversion section (for example, pin diode) 14 ... (first conductivity type) a-9i layer 15 ... (intrinsic type) a -9i layer 16... (second conductivity type) a-9i layer 17.21...
- Upper electrode conductor layer 18...Part of the substrate 20...Lower electrode conductor layer. Figure 1 1111 Figure 2 Figure 3 Procedural amendment January 10, 1985 Manabu Shiga, Commissioner of the Patent Office Relationship with the case of the person making the optical sensor element 3 amendment Patent applicant address (〒-105) Tokyo 1-7-12 Toranomon, Miyakominato-ku Name (028) Oki Electric Industry Co., Ltd. Representative Nankai Hashimoto 4 Agent 170 TX (88B) 5583 Address
1-20-5 Higashiikebukuro, Toshima-ku, Tokyo Ikebukuro White House Building No. 805 Contents of amendment (1) in Column 7 of the detailed description of the invention, "The optical response speed is" on page 12, line 8 of the specification "The optical response time is corrected to J.
Claims (1)
有する基板と、該基板の導電性表面上に形成した光電変
換部と、該光電変換部上に形成した上部電極用導電体層
とを具え、平面的に見て、前記上部電極用導電体層の領
域が前記光電変換部の領域内に位置させて成る光センサ
素子において、 該光電変換部の、前記上部電極用導電体層の領域との接
触面での領域を、前記上部電極用導電体層の領域の形状
と同一形状とし、該光電変換部の、前記」二部電極用導
電体層の領域との接触面から厚さの少なくとも一部分に
わたる平面的に見た領域を該光電変換部の残部の領域よ
りも狭小とした ことを特徴とする光センサ素子。 ２、特許請求の範囲第１項記載の光センサ素子において
、前記下部電極用導電性部分を放射透過性導電体層とし
、前記基板の残部を放射透過性材料で構成したことを特
徴とする光センサ素子。 ３、特許請求の範囲第１項記載の光センサ素子において
、前記上部電極用導電体層を放射透過性の導電体層とし
たことを特徴とする光センサ素子。 ４、特許請求の範囲第１項記載の光センサ素子において
、前記基板の全体を導電性基板としたことを特徴とする
光センサ素子。 ５、特許請求の範囲第１項〜第４項のいずれか一つに記
載の光センサ素子において、前記光電変換部を前記基板
側から第一導電型の非晶質半導体層と、真性非晶質半導
体層と、第二導電型の非晶質半導体層とで構成したこと
を特徴とする光センサ素子。[Claims] 1. A substrate having at least a conductive portion for a lower electrode on one surface side, a photoelectric conversion section formed on the conductive surface of the substrate, and an upper electrode formed on the photoelectric conversion section. A photosensor element comprising: a conductor layer for upper electrode, and in which a region of the conductor layer for upper electrode is located within a region of the photoelectric conversion section when viewed in plan; The region of the contact surface with the region of the conductor layer for the upper electrode is made to have the same shape as the region of the conductor layer for the upper electrode, and the region of the photoelectric conversion section with the region of the conductor layer for the two-part electrode is made to have the same shape as the region of the conductor layer for the upper electrode. An optical sensor element characterized in that a region extending from a contact surface to at least a portion of the thickness in a plan view is narrower than the remaining region of the photoelectric conversion section. 2. The optical sensor element according to claim 1, wherein the conductive portion for the lower electrode is a radiation-transparent conductor layer, and the remainder of the substrate is made of a radiation-transparent material. sensor element. 3. The optical sensor element according to claim 1, wherein the upper electrode conductive layer is a radiation-transparent conductive layer. 4. The optical sensor element according to claim 1, wherein the entire substrate is a conductive substrate. 5. In the optical sensor element according to any one of claims 1 to 4, the photoelectric conversion section is formed from an amorphous semiconductor layer of a first conductivity type and an intrinsic amorphous semiconductor layer from the substrate side. 1. A photosensor element comprising a crystalline semiconductor layer and an amorphous semiconductor layer of a second conductivity type.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59055768A JPS60198870A (en) | 1984-03-23 | 1984-03-23 | Photosensor element |
| US07/204,942 US4885622A (en) | 1984-03-23 | 1988-06-06 | Pin photodiode and method of fabrication of the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59055768A JPS60198870A (en) | 1984-03-23 | 1984-03-23 | Photosensor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60198870A true JPS60198870A (en) | 1985-10-08 |
Family
ID=13008042
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59055768A Pending JPS60198870A (en) | 1984-03-23 | 1984-03-23 | Photosensor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60198870A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63114058U (en) * | 1987-01-16 | 1988-07-22 | ||
| JPS63142862U (en) * | 1987-03-12 | 1988-09-20 |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5463690A (en) * | 1978-05-22 | 1979-05-22 | Yamazaki Shunpei | Photovoltaic force generating semiconductor and method of producing same |
| JPS5631908A (en) * | 1979-08-14 | 1981-03-31 | Plasser Bahnbaumasch Franz | Track running machine for cutting irregularity of rail head surface |
-
1984
- 1984-03-23 JP JP59055768A patent/JPS60198870A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5463690A (en) * | 1978-05-22 | 1979-05-22 | Yamazaki Shunpei | Photovoltaic force generating semiconductor and method of producing same |
| JPS5631908A (en) * | 1979-08-14 | 1981-03-31 | Plasser Bahnbaumasch Franz | Track running machine for cutting irregularity of rail head surface |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63114058U (en) * | 1987-01-16 | 1988-07-22 | ||
| JPS63142862U (en) * | 1987-03-12 | 1988-09-20 |
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